JPH08340488A - Solid-state image pickup device - Google Patents

Abstract

PURPOSE: To eliminate deterioration in smear resistance when a partial /M read is made and reduce the dark current at the time of low-illuminance image pickup operation. CONSTITUTION: A unit bit of a vertical scanning circuit consists of a shift register 1, and a level mixer circuit 2 which is equipped with 6 control switches 3-1 to 3-6 and one inverter and inputs four voltages VAC, VRD, VRS, and VOF to be outputted to a vertical selection line and a control clock Φ cont and its inverse for controlling output timing. In a line selection period wherein a partial read is unnecessary, the over flow voltage VOF is always outputted to the vertical selection line 5 for an unselected line to prevent deterioration in smear resistance.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state image pickup device using an image pickup device such as a CMD (Charge Modulation Device) in which a source / drain current is modulated by the amount of charges generated and accumulated by light irradiation as pixels. Regarding

[0002]

2. Description of the Related Art Conventionally, various solid-state image pickup devices including an image pickup device having a MIS type light receiving / accumulating portion are known. Among them, there are MIS type light receiving / accumulating portions and an internal amplification function. There is a solid-state image pickup device using an image pickup element having. One example is a solid-state image pickup device using a CMD image pickup element proposed by the applicant of the present invention, which is described in detail in, for example, the technical report "1 inch 2 million pixel CMD image sensor" of the Television Society (Ogata et al., 1992.2). ing.

Next, the basic structure of a solid-state image pickup device using such a CMD image pickup element will be described with reference to FIG. First, the pixels 11 made up of CMD are arranged two-dimensionally to form a sensor array
A common bias 19 is applied to each drain of the CMD pixels. Further, each CMD pixel is formed on the same substrate, and a substrate bias is applied although not shown. In the sensor array 12, the gate electrodes of the pixels 11 in the row direction are connected to the common vertical selection line 15, and the source electrodes of the pixels 11 in the column direction are connected to the common vertical signal line 16. The vertical selection line 15 is connected to the vertical scanning circuit 13, and the vertical signal line
16 is a horizontal selection switch driven by the horizontal scanning circuit 14.
It is connected to the signal line 18 via 17.

Next, the pixel selection operation of the solid-state image pickup device having the above-mentioned structure will be described. For column selection, the shift register built in the horizontal scanning circuit 14 is a horizontal selection switch.
This is done by sequentially opening and closing 17 and connecting each vertical signal line 16 to the signal line 18 in order. Row selection will be described with reference to FIGS. 8 and 9. FIG. 8 shows pulse waveforms applied to the selected row and the non-selected row of the vertical selection line 15 in the horizontal blanking period and the effective signal output period, respectively. This pulse contains four types of voltages, that is, VAC (accumulation voltage), VRD (readout voltage), VOF (overflow voltage), and VRS (reset voltage).

Next, FIG. 9 showing the potential distribution in the pixel in the state where the above pulse voltage is applied to the gate electrode.
Based on the above, the role of each of the above voltages will be schematically described. That is, in the state (A) in which the storage voltage VAC is applied, a deep well type potential is formed, and the photogenerated holes are held in the gate electrode. The circles in the figure represent holes. In this case, the source / drain is blocked by this deep potential, and almost no current flows. That is, the vertical selection line to which the accumulated voltage VAC is applied becomes a non-selection line. Read voltage V
In the state (B) in which RD is applied, a well-type potential shallower than that in the state (A) is formed. In this case, a current can flow between the drain and the source. At this time, the holes generated by light are held in the gate electrode, and the current between the drain and the source reflects the number of held holes. That is, the read voltage V
The vertical selection line to which RD is applied is in the selected state. Therefore, control of row selection in the valid signal output period is performed by applying the read voltage VRD to the selected row and applying the storage voltage VAC to all the other rows. In the state (C) in which the reset voltage VRS is applied, the well-type potential does not exist, and the held holes are ejected. This reset operation initializes the pixel group for which the read operation has been performed, and the reset voltage VRS is as shown in FIG.
It is applied to the vertical selection line during the horizontal blanking period immediately after being selected.

The basic operation is to store these accumulation states (A),
In addition to the read state (B) and the reset state (C), there is the overflow operation mode shown in the state (D) of FIG. In this operation, the overflow voltage VOF is applied to the vertical selection line. In the state (D) in which the overflow voltage VOF is applied, a well type potential is formed. The need for overflow operation is
This is due to the difference in the depth of the potential well between the accumulated state (A) and the read state (B). That is, the maximum number of holes that can be treated as a signal is determined by the depth of the potential in the read state (B).
Except for the purpose of not passing a current between the drain and the source, it is not necessary to form a deep well type potential as shown in FIG. Moreover, the excessive holes accumulated in the potential well formed deeper than necessary becomes a factor that deteriorates smear characteristics. Therefore, as shown in FIG. 8, it is necessary to increase the depth of the potential well for each horizontal blanking period to the same depth as that in the state where the read voltage VRD is applied to discharge excess holes. Becomes

Since the overflow voltage VOF for performing a reliable overflow operation depends on the drain and source potentials in the horizontal blanking period, it does not always become the same as the read voltage VRD.

A vertical scanning circuit for selecting a row as described above includes a shift register having the same number of bits as the number of scanning rows and a control for outputting the above-mentioned four kinds of voltages to the vertical selection line at a predetermined timing. It is composed of a circuit. Figure
10 shows a concrete example of the configuration of a unit bit in such a vertical scanning circuit.
As detailed in the issue. The unit bit of this vertical scanning circuit is composed of a shift register unit 1 and a level mix circuit 2, and the level mix circuit 2 is composed of six control switches 3-1 to 3-6 and one inverter. ing. Each control switch is, for example, an MO
It is formed by an S transistor.

The level mix circuit 2 has four voltages VAC, VRD, VRS and V to be output to the vertical selection line.
The normal and inversion clocks of the basic clock Φ2 for controlling the OF and the output timing are input, and the output of the level mix circuit 2 is connected to the vertical selection line 5. Then, the control switches 3-1 and 3-6
Is the control switch 3-2 while the clock Φ2 is at the L level.
And 3-5 are turned on during the period when the clock Φ2 is at the H level, the control switch 3-3 is turned on during the period when the shift register output 4 is at the H level, and the control switch 3-4 is turned on while the shift register output 4 is at the L level. , Shall be turned off during the period when opposite levels are given. The shift register output 4 is H level in the selected row and L level in the non-selected row.
The level shall be output.

Next, based on the operation timing chart of FIG.
The operation of the vertical scanning circuit having the above configuration will be described. Clock Φ
Reference numeral 1 is a clock that is at H level during the horizontal flyback period, clock Φ2 is a clock that is at L level for a certain period within the horizontal flyback period, and the shift register performs the shift operation in synchronization with the falling edge of the clock Φ1. When not selected, the shift register output 4 is at L level, so the control switch 3-
3 is off and the control switch 3-4 is on. In this case, in the horizontal blanking period, the control switch 3-6 is turned on while the clock Φ2 is at the L level, the overflow voltage VOF is output to the vertical selection line 5, and the clock Φ2 is output.
2 is at H level, the control switch 3-5 is turned on and the accumulated voltage VAC is output to the vertical selection line 5. During the effective signal output period, the control switch 3-5 is turned on and the accumulated voltage VAC is vertical. It is output to the selection line 5.

On the other hand, when selected, the shift register output 4 is at H level.
Since it is at the level, the control switch 3-3 is turned on and the control switch 3-4 is turned off. In this case, in the horizontal blanking period, the control switch 3-1 is turned on during the period when the clock Φ2 is at the L level, the reset voltage VRS is output to the vertical selection line 5, and the control is performed during the period when the clock Φ2 is at the H level. The switch 3-2 turns on, and the read voltage VRD
Is output to the vertical selection line 5, and during the effective signal output period, the control switch 3-2 is turned on to read the read voltage VRD.
Is output to the vertical selection line 5. By the above control, the gate control pulse indicated by ΦG is applied to the vertical selection line 5
Is applied to

[0012]

In the solid-state image pickup device, for the purpose of reducing the amount of information or improving the frame rate, a part for extracting a part of the signal of pixels (photoelectric conversion elements) arranged in a matrix. Reading is performed. As one of the methods, Japanese Patent Laid-Open No. 63-153971 discloses a method of increasing the clock frequency of the vertical scanning circuit in the operation of selecting an unnecessary line from which a signal is not read.

However, when this operation is performed in the solid-state image pickup device using the CMD as the pixel described above, the overflow operation is not performed and the smear resistance is deteriorated when the unnecessary line is selected.
This problem will be described with reference to FIG. Figure 12 shows
Clock Φ of vertical scanning circuit when partial reading is performed
1, Φ2, and a vertical selection line signal (gate control pulse) ΦG are shown. In FIG. 12, the signal reading period is a period in which a line required as a signal is selected, while the unnecessary line selection period is a period in which a line not used as a signal is selected. In partial reading, this unnecessary line selection period is a wasteful period,
The frequency of the clock of the vertical scanning circuit is increased to shorten this period. However, if the frequency of the clock of the vertical scanning circuit is increased, the L level period of the clock Φ2 becomes shorter, and the vertical selection line signal ΦG is originally VOF during this period.
However, the overflow operation is not performed as a result of not rising to the VOF. Therefore, smear resistance deteriorates when partial reading is performed.

The rising time of the vertical selection line signal ΦG is shortened by reducing the load on the vertical selection line and increasing the drive capability of the level mix circuit. However, the load on the vertical selection line depends on the number of pixels and cannot be easily reduced. Further, in order to increase the drive capability of the level mix circuit, the circuit size becomes large, such as increasing the size of the transistor, which cannot be easily done.

In addition to the above problems, there are the following problems. In the solid-state imaging device, even when no light is incident, carriers generated at the semiconductor substrate and the semiconductor / insulating film interface accumulate in the light receiving portion during the accumulation period, and the dark current due to this causes a fixed pattern noise, Particularly in low-illuminance imaging, it is desirable to suppress dark current as much as possible because signal reading is performed once every several frames to increase the accumulation time.

The dark current in the solid-state image pickup device using the CMD described above as a pixel changes depending on the electric field strength near the edge of the drain region, and the dark current increases as the potential difference between the gate and drain increases. I know that.
As can be seen from FIG. 9 and FIG. 11, the potential difference between the gate and the drain is largest when the gate potential is the storage voltage VAC. In low-illuminance imaging in which several frames are accumulated, dark current becomes a problem because the period during which the gate potential becomes the accumulation voltage VAC becomes long.

The present invention has been made in order to solve the above problems in the conventional solid-state image pickup device. The smear resistance does not deteriorate when partial reading is performed in the solid-state image pickup device, and several frames are accumulated. It is an object of the present invention to provide a solid-state image pickup device using a CMD image pickup element or an image pickup element similar thereto as a pixel, which can reduce dark current in low-illuminance image pickup.

[0018]

In order to solve the above problems, the invention according to claim 1 uses a transistor in which a source / drain current is modulated by a charge amount generated and accumulated by light irradiation as a pixel. A pixel array in which the pixels are arranged in a matrix, a read signal for reading a source / drain current corresponding to the accumulated charge of each pixel of the pixel array, and a reset signal for discharging all the accumulated charges of the pixel In a solid-state image pickup device comprising a driving means for selectively applying an overflow signal for discharging a part of the accumulated charge of the pixel to a gate of the pixel, the driving means supplies the overflow signal to the gate of each pixel for an arbitrary period. It is configured so that it can be applied to.

With this configuration, when partial reading is performed in the solid-state image pickup device, the overflow operation can be performed even while the unnecessary line is being selected, and the CMD image pickup device having excellent smear resistance, or It is possible to realize a solid-state imaging device using an imaging element similar to. Further, in the low illuminance imaging for accumulating several frames, it becomes possible to set the gate potential during the accumulation period to the overflow voltage VOF, and the electric field strength of the drain region is relaxed compared to the deep accumulation state, so that the dark current can be reduced. , A CMD image pickup device, or a solid-state image pickup device using an image pickup device similar thereto can be realized.

The invention described in claims 2 and 3 is, in the solid-state image pickup device according to claim 1, configured such that the overflow signal application control of the driving means is performed by the control of a pulse or a power supply line. This allows the overflow operation to be easily performed in a desired period.

[0021]

【Example】

(First Embodiment) Next, an embodiment will be described. Figure 1
FIG. 7 is a diagram showing a configuration of a unit bit of the vertical scanning circuit of the first embodiment of the solid-state imaging device according to the present invention, and the configuration of other portions is shown in FIG.
Since it is the same as the conventional example shown in FIG. The configuration of the unit bit of the vertical scanning circuit of this embodiment is the same as that of the conventional example shown in FIG. 10 in terms of circuit components, and the shift register unit 1 and the six control switches 3-1 to 3-3-
Level mix circuit 2 consisting of 6 and one inverter
However, the difference is that the clock Φcont is used instead of the clock Φ2 as the timing control clock of the level mix circuit 2.

Next, the operation of the unit bit of the vertical scanning circuit having the configuration shown in FIG. 1 will be described with reference to the timing chart of FIG. Clocks .PHI.1 and .PHI.2 are clocks of the vertical scanning circuit, and in the unnecessary line selection period of partial reading, the frequency is increased to perform high-speed scanning. The level mix circuit control clock Φcont has a waveform similar to that of the clock Φ2 during the partial read signal read period, and is always at the L level during the unnecessary line selection period. ΦG is a unit bit output of the vertical scanning circuit and is a vertical selection line signal (gate control pulse).

The operation when these clocks are applied is as follows. That is, in the partial read, the read voltage VRD is output to the vertical select line 5 during the valid signal output period of the selected line during the signal read period, as in the conventional example, and the horizontal blanking period is the clock Φcont, that is, L of the clock Φ2. During level, reset voltage VR
S is output to the vertical selection line 5. Further, the storage voltage VAC is output to the vertical selection line 5 during the effective signal output period of the non-selected line, and the overflow voltage V is output during the horizontal retrace period during the L level of the clock Φcont, that is, the clock Φ2.
OF is output to the vertical selection line 5. On the other hand, during the unnecessary line selection period of partial reading, the control switches 3-1 and 3-6 are constantly turned on and the control switches 3-2 and 3-5 are turned on.
Since it is off, the overflow voltage VOF is always output to the vertical selection line 5 in the non-selected line. Therefore, even when partial reading is performed, the smear resistance does not deteriorate because the overflow operation is performed during the unnecessary line selection period.

In the present embodiment, the clock .PHI.cont is always at the L level during the unnecessary line selection period, but it may be in the pulse form as long as the vertical selection line signal .PHI.G can secure a period in which the overflow voltage VOF rises sufficiently.

(Second Embodiment) FIG. 3 is a diagram showing a configuration of a unit bit of a vertical scanning circuit of a second embodiment of the solid-state image pickup device according to the present invention, and the configuration of other portions is shown in FIG. Since it is similar to the conventional example, its description is omitted. The configuration of the unit bit of the vertical scanning circuit of this embodiment is as shown in FIG.
The same as the conventional example shown in 10, the shift register unit 1
And a level mix circuit 2 including six control switches 3-1 to 3-6 and one inverter. As a timing control clock for the level mix circuit 2, a clock Φ2 and a control signal CONT are used. A
The difference is that ND output is used.

Next, the operation of the unit bit of the vertical scanning circuit having the configuration shown in FIG. 3 will be described with reference to the timing chart of FIG. Clocks Φ1 and Φ2 are clocks of the vertical scanning circuit, and increase the frequency and perform high-speed scanning in the unnecessary line selection period of partial reading. Control signal C
The ONT is a signal that is at the H level during the signal reading period of partial reading and at the L level during the unnecessary line selection period.
ΦG is an output of a unit bit of the vertical scanning circuit and is a vertical selection line signal.

The operation when these clocks are applied is as follows. That is, in the partial read, since the control signal CONT is at the H level during the signal read period, the level mix circuit control clock is the same as the clock Φ2, which is the same as the conventional example and the first example. On the other hand, since the control signal CONT is at the L level during the unnecessary line selection period of the partial read, the level mix circuit control clock is always at the L level, that is, the control switches 3-1 and 3-6 are always on and the control switch 3-2 is 3-5 is turned off, and the overflow voltage VOF is always output to the vertical selection line 5 in the non-selection line. Therefore, even when partial reading is performed, the smear resistance does not deteriorate because the overflow operation is performed during the unnecessary line selection period.

In this embodiment, the AND circuit is used to generate the level mix circuit control clock from the clock Φ2 and the control signal CONT, but other configurations may be used as long as the logic is the same.

(Third Embodiment) FIG. 5 is a diagram showing a configuration of a unit bit of a vertical scanning circuit of a second embodiment of the solid-state image pickup device according to the present invention, and the configuration of other portions is shown in FIG. Since it is similar to the conventional example, its description is omitted. The configuration of the unit bit of the vertical scanning circuit of this embodiment is as shown in FIG.
The same as the conventional example shown in 10, the shift register unit 1
And a level mix circuit 2 including six control switches 3-1 to 3-6 and one inverter. In the conventional example, the power supply of the level mix circuit 2 to which the accumulated voltage VAC is applied. The difference is that the storage voltage VAC and the overflow voltage VOF are selectively applied to the line 6 via a switch 7 which is switched and controlled by a control signal CONT.

In this configuration, if the switch 7 is controlled so that the power supply line 6 is supplied with the accumulated voltage VAC when the control signal CONT is at the H level and the overflow voltage VOF is supplied when the control signal CONT is at the L level, the vertical The selection line signal ΦG becomes the same as that shown in FIG. Therefore, even when partial reading is performed, the smear resistance does not deteriorate because the overflow operation is performed during the unnecessary line selection period. The level of the control signal CONT is not limited to the setting as in this embodiment.

(Fourth Embodiment) FIG. 6 is a diagram showing a low-speed read-out signal for several frames using the unit bit configuration of the vertical scanning circuit of the second embodiment shown in FIG. 3 of the solid-state image pickup device according to the present invention. It is a figure which shows the timing at the time of performing illuminance imaging. In FIG. 6, the signal read frame is a frame in which a signal is read once every several frames. The non-signal reading period is a period during which only accumulation is performed, and the length of this period changes depending on the illuminance of the subject. Φ1 and Φ2 are clocks of the vertical scanning circuit, and the control signal CONT is a signal that becomes H level in the signal read frame and becomes L level in the non-signal read period. ΦG is a unit bit output of the vertical scanning circuit and is a vertical selection line signal.

As for the operation when these clocks are given, the control signal CONT is at H level as in the second embodiment.
At the level, the read voltage VRD / reset voltage VRS is output to the vertical select line on the selected line, and the storage voltage VAC / overflow voltage VOF on the non-selected line.
Is output to the vertical selection line. On the other hand, during the non-signal read period when the control signal CONT is at L level, the overflow voltage VOF is always output to the vertical selection line. Therefore, the electric field strength of the drain region during the non-signal reading period is relaxed as compared with the deep accumulation state, so that the dark current can be reduced.

In the above first to fourth embodiments, the level mix circuit is configured as shown in FIG. 1 as long as the same pulse as in each embodiment can be applied to the vertical selection line.
The configuration is not limited to those shown in FIGS.

[0034]

As described above on the basis of the embodiments,
According to the first aspect of the invention, when partial reading is performed in the solid-state imaging device, the overflow operation can be performed even while the unnecessary line is selected, and it is possible to prevent deterioration of smear resistance. It will be possible. In addition, dark current can be reduced in low-illuminance imaging in which several frames are accumulated. Further, according to the invention described in claims 2 and 3, it becomes possible to easily carry out the overflow operation in an arbitrary period.

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram showing a configuration of a unit bit of a vertical scanning circuit of a first embodiment of a solid-state imaging device according to the present invention.

FIG. 2 is a timing diagram illustrating an operation of a unit bit of the vertical scanning circuit shown in FIG.

FIG. 3 is a circuit configuration diagram showing a configuration of a unit bit of a vertical scanning circuit according to a second embodiment of the present invention.

FIG. 4 is a timing diagram illustrating an operation of a unit bit of the vertical scanning circuit shown in FIG.

FIG. 5 is a circuit configuration diagram showing a configuration of a unit bit of a vertical scanning circuit according to a third embodiment of the present invention.

FIG. 6 is a timing diagram illustrating an operation of a unit bit of the vertical scanning circuit according to the fourth exemplary embodiment of the present invention.

FIG. 7 is a circuit configuration diagram showing a basic configuration of a solid-state image pickup device using a conventional CMD image pickup element.

8 is a diagram showing a pulse waveform applied to a vertical selection line of the solid-state imaging device shown in FIG.

9 is a diagram showing a potential distribution in a state where each pulse voltage is applied to the gate electrode of each pixel of the solid-state imaging device shown in FIG.

10 is a circuit configuration diagram showing a configuration of a unit bit in the vertical scanning circuit of the solid-state imaging device shown in FIG. 7.

11 is a timing chart for explaining an operation of a unit bit of the vertical scanning circuit shown in FIG.

FIG. 12 is a timing chart for explaining a problem when partial reading of the sensor array is performed in the solid-state imaging device shown in FIG. 7.

[Explanation of symbols]

 1 shift register unit 2 level mix circuit 3-1 to 3-6 control switch 4 shift register output 5 vertical selection line 11 pixel 12 sensor array 13 vertical scanning circuit 14 horizontal scanning circuit 15 vertical selection line 16 vertical signal line 17 horizontal selection switch 18 Signal line 19 Drain bias

Claims (3)

[Claims] 1. A pixel array in which a source / drain current is modulated by a charge amount generated and accumulated by light irradiation as a pixel, and the pixel is arranged in a matrix,
A read signal for reading the source / drain current corresponding to the accumulated charge of each pixel of the pixel array, a reset signal for discharging all the accumulated charge of the pixel, and an overflow signal for discharging a part of the accumulated charge of the pixel. In a solid-state imaging device including a drive unit that selectively applies and to the gate of the pixel, the drive unit is configured to be able to apply an overflow signal to the gate of each pixel for an arbitrary period. Solid-state imaging device. 2. The solid-state image pickup device according to claim 1, wherein the overflow signal application control of the drive unit is configured to be performed by controlling a pulse used in the drive unit. 3. The overflow signal application control of the drive means is configured to be performed by control of a power supply line used for the drive means.
The solid-state imaging device described.