JPH09149319A - Method and device for driving electrode of ccd - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for driving electrodes of a CCD by which the dynamic range of the CCD is improved. SOLUTION: A drive pulse is fed to 2nd and 4th phase electrodes of a 4-phase electrode structure CCD for frame transfer periods, and its duty differs from that of a drive pulse fed to 1st and 3rd phase electrodes of the CCD being a frame inter-line charge transfer device for frame transfer periods. According to this method, an unsharpened waveform of the drive pulses is reduced and the dynamic range of the CCD fluctuated timewise is made almost constant.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driving method for a CCD solid-state image pickup device (hereinafter referred to as CCD), and more particularly to a CCD electrode driving method and device for expanding a dynamic range (hereinafter referred to as DR).

[0002]

2. Description of the Related Art FIG. 10 is a block diagram of a conventional frame interline type (hereinafter referred to as FIT type) CCD. Regarding the basic operation of the FIT type CCD, I E E E, Electron Devices Letter 2 (1981 12
Page 319 to page 320 (IEEE, Electron Devices Letter)
2 (Dec., 1981) P. 319-320).

Conventionally, as shown in FIG. 10, photons incident on a photodiode (hereinafter referred to as PD) 90 are converted into electric charges and accumulated in the PD 90. After a certain period of time, the signal charges are read by the vertical CCD (hereinafter referred to as VCCD) 91 and transferred to the storage unit 94 (frame transfer) in a short period of time. The signal charges transferred to the storage unit 94 are supplied to the horizontal CCD for each line.
(Hereinafter referred to as HCCD) 92 is input to the FDA 93 and detected as a voltage.

FIG. 11 is a diagram showing drive pulses supplied to the FIT CCD, which are applied to φV1 to φV4. The drive pulse is divided into a sweep section 95, a reading section 96, a high-speed transfer section 97, and an interline transfer (hereinafter IT) section 98, and the sweep section 95 sweeps smear charges accumulated in the VCCD 91 through the HCCD 92. Read-out unit 9
In 6, the signal charge is transferred from the PD 90 to the VCCD 91, and in the high speed transfer section 97, the signal charge of the VCCD 91 is transferred to the storage section 94. The above operation is performed during the vertical blanking period. In the IT section, the signal charges stored in the storage section 94 are transferred to the HCCD 92 line by line during the horizontal blanking period.

FIG. 12 is a detailed timing chart of the drive pulse, which is applied in the sweep section 95 and the high speed transfer section 97. In Fig. 12 (a), the drive pulse is duty =
In the case of 50%, the same figure (b) is the case of duty = 63%, and each drive pulse is normally a four-phase square wave with a phase difference of π / 2. A frequency higher than that of the high speed transfer unit 97 is applied to the sweeping unit 95.

Further, in the φS1 to φS4, the sweep section 95.
The same pulse as φV1 to φV4 is applied only to the high-speed transfer unit 97. A driver IC is generally used to drive the FIT CCD.
The C signal is applied to φV1 to φV4 and φS1 to φS4. The FIT CCD is used for broadcasting / commercial cameras because of its low smear, and most of the high-definition cameras are also FIT.

FIG. 13 is a sectional view of the VCCD.
3A is a cross section in the Y direction of FIG. 10, and FIG. 13B is a cross section in the X direction. A cross section of only φV4 is shown in FIG. 7B, but the same applies to φV1 to φV3. Generally, φV2 and φV4 gates are formed of the first layer polysilicon, and φV1 and φV3 gates are formed of the second layer polysilicon.
The polysilicon to which the signals of φV1 to φV4 are supplied forms capacitors C1 to C4 with the n layer through the oxide film 84. Further, since the light shielding film 85 is formed of a metal such as aluminum and tungsten and has the interlayer film 86 which is an insulating layer interposed therebetween, the capacitance C5 is similarly generated. Although not shown, drivers 80 to 83 must drive these capacitors because capacitors also occur between the polysilicons. As the size and the number of pixels are further reduced, the polysilicon resistance and capacitance will increase.

[0008]

However, in the conventional FIT type CCD as described above, since the drive pulse is 700 KHz to 1.5 MHz in the sweep section 95 and the high-speed transfer section 97, a rounded square wave is added. However, there was a problem that it became close to a sine wave. As a result, since the pulse is not sufficiently transmitted to the center of the CCD, there is a phenomenon that DR defined by the amplitude of the drive pulse is significantly reduced. Note that the saturation level of VCCD is treated as DR here.

These causes will be described below. The polysilicon gate shown in FIG. 13 has a resistance of several tens Ω / □, and the drivers 80 to 83 also have an output resistance of 20 to 30 Ω.
Have resistance. These resistance and capacitance (C1-C
According to 5), even if a square wave is added as a drive pulse, C
The pulse does not rise sufficiently at the center of the CD. FIG.
As is clear from FIG. 3, the second-layer polysilicon is the first
Since it is formed on the polysilicon layer, the area facing the light shielding film 85 becomes large. Therefore, the light shielding film 8
The capacitance formed between 5 and the second layer polysilicon is larger. Therefore, φV formed of the second layer polysilicon
1. The waveform rounding of φV3 becomes severe.

FIG. 14 shows these relationships. FIG. 14 is an explanatory diagram of a drive pulse in which the rounding of the waveform is taken into consideration, and the broken line indicates C.
The center of the CD, the solid line is the CCD end. FIG. 14 shows drive pulses in the high-speed transfer unit 97, and t = 0 indicates the read unit 96.
Shows the boundary with and the state at t = 0 after signal charge read is about 1
It is assumed that 0 μsec continues. Since the waveform rounding of φV1 and φV3 is large, it does not rise sufficiently as shown in FIG. 4A, and it gradually approaches VX at the first pulse and gradually approaches VY thereafter and stabilizes. The DR shown in FIG. 14E is φV1 to φV
This is the fluctuation of the dynamic range when the potential under the gate changes as indicated by 4 (broken line). Although DR is often considered to be constant, it actually changes over time and is limited by its minimum value.

In FIG. 1 (e), DR has a minimum value VD at the first drive pulse, but gradually increases to a maximum value VMX and a minimum value VR.
Will be repeated. The minimum value VD is only the first few pulses, but when displayed on a CRT, a slight sag occurs in the downward direction. After that, since VR becomes the minimum value, the substantial DR is defined by VR. Since a driving pulse with almost no rounding is applied at the CCD end, DR has a constant value with no time change. When the drive frequency is further increased (for example, at the time of sweeping, at the time of driving at triple speed), the waveform rounding becomes more severe. If the waveform rounding at the center of the CCD becomes severe, the ratio of "VMX / VR" becomes 2 or more, and the absolute value of VR itself also greatly decreases. The triple speed drive is used for slow-motion photography, and conventionally, it was dealt with by simply increasing the drive frequency to triple. The change in DR is made by turning on and off each drive pulse, and conventionally, the range of the minimum value and the maximum value is wide, resulting in a decrease in DR as a whole.

Although the DR drop can be slightly suppressed by increasing the drive voltage (VM), the transfer efficiency may be lowered because the CCD approaches the surface channel type. Moreover, the breakdown voltage of a general driver IC (eg, μPD16502) is (VH-VL) = 2
It is 5V, which is (VH = 16
V, VL = -9V), drive voltage cannot be increased any further.

The present invention has been made in view of the above points, and an object thereof is to provide a CCD electrode driving method and a device therefor having an improved dynamic range.

[0014]

SUMMARY OF THE INVENTION The present invention as set forth in claim 1 for solving the above-mentioned problems, includes a first phase and a third phase of a four-phase electrode structure CCD included in a frame interline type charge transfer device. A drive pulse having a duty different from the duty of the drive pulse applied to each of the electrodes in the frame transfer period is used as the drive pulse applied to each of the second-phase and fourth-phase electrodes of the CCD in the frame transfer period. Is a method of driving a CCD electrode.

The duty of the drive pulse applied to each of the first and third phase electrodes of the CCD in the frame transfer period is 50%, and the electrodes of the second and fourth phases of the CCD are The duty of the drive pulse applied to each frame transfer period may be greater than 50%.

According to a third aspect of the present invention, a four-phase electrode structure CC included in a frame / interline type charge transfer device is provided.
The drive pulse applied to each of the first to fourth phase electrodes of D in the frame transfer period includes at least two pulses having different duty cycles.
This is the electrode driving method.

According to a fourth aspect of the present invention, there is provided a four-phase electrode structure CC included in a frame / interline type charge transfer device.
A first drive pulse is applied to each of the first phase electrodes of D.
And a drive pulse having the same duty as the drive pulse applied by the first drive means.
A third drive means applied to each of the third-phase electrodes, and a drive pulse having a duty different from the drive pulse applied in the frame transfer period by the first drive means and the third drive means. A second drive unit applied to each of the second-phase electrodes of the CCD in the transfer period, and a drive pulse different in duty from the drive pulse applied in the frame transfer period by the first drive unit and the third drive unit. A fourth electrode driving device for applying a driving pulse to each of the fourth-phase electrodes of the CCD in the frame transfer period.

According to a fifth aspect of the present invention, a four-phase electrode structure CC included in a frame / interline type charge transfer device is provided.
In each of the electrodes of the first phase in the frame transfer period of D,
First drive means for applying a drive pulse including at least two pulses of different duty, and application of a drive pulse including at least two pulses of different duty to each of the electrodes of the second phase in the frame transfer period of the CCD. And second drive means for applying a drive pulse including at least two pulses of different duty to each of the electrodes of the third phase in the frame transfer period of the CCD, and the frame transfer of the CCD. A fourth electrode driving device for applying a driving pulse including at least two pulses of different duty to each of the fourth-phase electrodes in the period is an electrode driving device for a CCD.

According to a sixth aspect of the present invention, a selecting means for selecting a voltage setting means for applying a predetermined voltage from a plurality of voltage setting means for applying different voltages, and a voltage selected by the selecting means. At least one of the CCDs is input by inputting the voltage applied by the setting means and outputting the input voltage with a low impedance, and by inputting the voltage output by the buffer means and using the input voltage. It is an electrode driving device for a CCD, which is provided with a driver means for driving each of the electrodes of one phase.

The present invention according to claim 7 drives each of the electrodes of each phase of the electrode structure CCD having a phase of a multiple of 4 larger than 4 in the frame interline type charge transfer device, which is larger than 4 thereof. In the case of a plurality of driver means of 4 and the sweep period, the phase of a multiple of 4 larger than 4 is taken as one unit, and each of the driver means is provided with the CC.
In the case of the first drive control means for driving each of the electrodes of each phase of D and the frame transfer period for performing the high-speed transfer, each of the electrodes of each phase of the CCD is connected to each of the driver means.
An electrode driving device for a CCD, comprising: second drive control means for phase driving.

The present invention according to claim 8 inputs drive means for applying a drive pulse and a drive pulse applied by the drive means, and the input drive pulse is at least one of CCDs with low impedance. It is an electrode driving device for a CCD, comprising: impedance conversion means for outputting to each of the phase electrodes.

By these, the rounding of the waveform of the VCCD drive pulse is reduced, and the D of the VCCD which fluctuates with time is reduced.
R can be made almost constant.

Further, within the withstand voltage of the driving driver, the CCD
It is possible to increase the drive voltage amplitude of.

[0024]

Embodiments of the present invention will be described below with reference to the drawings.

A first embodiment of the present invention will be described with reference to FIG. 1, which is a timing chart showing the timing of the CCD electrode driving method. Traditionally,
The duty of each pulse applied to each electrode of each phase of the CCD was the same. Therefore, the feature of this embodiment is that φV1 and φV3, and φV2 and φV4.
In (1) and (2), each of the electrodes of each phase of the CCD is driven by a pulse having a different duty.

In the present embodiment, the duty of pulses of φV1 and φV3 is set to 50%, and the duty of pulses of φV2 and φV4 is set to 50% or more. Since the conventional DR has a wide range between the maximum value and the minimum value as shown in FIG. 14, the overall DR is lowered. In this embodiment,
By changing the duty, it is possible to shift the on and off timings of the drive pulse. This allows
The minimum value is VR2, and the relation "VR <VR2" is established,
DR is improved as compared with the conventional case.

According to the results of experiments employing this embodiment, it is possible to improve the characteristics by 10 to 30% as compared with the conventional one. The improvement amount has a range because the amount of waveform rounding (R,
This is because the effect varies depending on the size of C). Therefore, the optimum pulse duty depends on the waveform rounding. However, when the pulse duty is 50% or less,
Since the charge accumulation at the CCD end is only one gate, the DR is reduced. Further, since φV1 and φV3 have larger waveform rounding than φV2 and φV4 (large R and C),
The duty was set to 50% in order to secure a sufficient drive amplitude.

A second embodiment of the present invention will be described with reference to FIG. 2, which is a timing chart showing the timing of the method for driving the electrodes of the CCD. The feature of this embodiment is that the initial frequency of the drive pulse is set to a lower frequency than in the conventional case. In the conventional driving method, the frequency during high-speed transfer was always constant. The present embodiment is characterized in that it is operated at a plurality of frequencies.

As shown in the conventional problem, at the start of high-speed transfer, the influence of the initial state (reading section) is large, and D
R was decreasing. In the present embodiment, the driving is performed at a low frequency only in the initial portion where the DR drops, and thereafter, the driving is performed at a higher frequency than the initial portion. Therefore, the drop of DR is small and the relationship of "VD2>VD" is established, so that a slight sag when displayed on a CRT is eliminated.

Needless to say, if the first embodiment and the second embodiment are combined as shown in FIG. 3, the characteristics can be further improved.

Although only the first pulse has a low frequency in FIG. 2, it may be more effective to drive a plurality of pulses at a low frequency depending on how the waveform is blunted.

Further, since the PLD (programmable logic device) generally generates the basic signal of the CCD drive pulse, the duty change for each phase shown in the first embodiment is performed. The frequency change of the second embodiment can be easily implemented.

Furthermore, in the first and second embodiments,
Although only φV1 to φV4 have been described, the above embodiment can be similarly applied to φS1 to φS4.

A third embodiment of the present invention will be described with reference to FIG. 4 which is a block diagram including the CCD electrode driving device. A feature of the present embodiment is an apparatus that avoids the problem of withstand voltage of the driver IC, which has been shown in the conventional problem, by switching the power supply voltage supplied to the driver IC. In FIG. 4, 1 is a CCD, 2 is a driver, and 3
And 4 are select circuits, 9 and 10 are buffer circuits, 5
Reference numerals 6 and 7 are H voltage setting circuits, and reference numerals 7 and 8 are L voltage setting circuits.

The H voltage setting circuit 5 is set to a voltage necessary for reading (for example, 16 V), and the H voltage setting circuit 6 is set to a voltage lower than this. In addition, the L voltage setting circuit 7
Is a driver IC even if the voltage of the H voltage setting circuit 5 is applied.
Is set to a voltage (for example, -9V) that is not destroyed. L
The voltage setting circuit 8 is lower than the L voltage setting circuit 7,
Is set to the maximum value.

Next, the operation of the present embodiment will be described with reference to the timing charts of FIGS. 5 and 4. The select circuits 3 and 4 switch the H voltage and the L voltage set as described above to either one and output them. The buffer circuits 9 and 10 output the H voltage and L voltage input from the select circuits 3 and 4 with low impedance. The H voltage and the L voltage output by the buffer circuits 9 and 10 are supplied to the driver 2 as a power supply. The driver 2 has φV1 to φV depending on the supplied voltage.
V4 is modulated and CCD1 is driven.

The select circuit 3 selects the output of the H voltage setting circuit 5 so as to be narrower than that of the reading section 11 shown in FIG. 5C, and selects the output of the H voltage setting circuit 6 in other cases.
As a result, the output of the buffer circuit 9 becomes as shown in FIG. Similarly, the select circuit 4 selects the output of the L voltage setting circuit 7 for a period narrower than that of the reading unit 11 and wider than the select circuit 4, and selects the output of the L voltage setting circuit 8 for other periods. As a result, the output of the buffer circuit 10 is shown in FIG.
It becomes (b), and the L voltage (for example −
It can be driven by 12V).

The control signals of the select circuits 3 and 4 and the driver 2 (for example, the signals shown in FIG. 12 are output).
The modulation control signal is a microcomputer or PL not shown.
Supplied by D.

Further, since the voltage is sufficiently applied at the CCD end portion to easily approach the surface channel type, the VM voltage is not increased.

FIG. 6 is a timing chart of drive pulses by the electrode drive device of the present CCD. FIG. 6A shows a case where the L voltage of the sweeping section is further lowered. This is a countermeasure because the sweep section has a higher frequency than the high-speed transfer section, and the amplitude of the drive pulse is likely to decrease. That is, by setting the L voltage so that the high-speed transfer section has a sufficient amplitude and then setting the voltage at the sweeping section to a lower value, the pinning voltage (the potential under the gate does not change) is sufficiently changed even if the frequency is different. Voltage) can be reached. This not only improves DR, but also improves smear charge transfer capability. Moreover, the VM voltage is not raised for the reason described above.

FIG. 6 (b) is a timing chart of drive pulses in the case where the electrode drive device of the present CCD carries out triple speed drive. By lowering the L-side voltage of the sweep section and high-speed transfer section, the amplitude of the drive pulse is secured and the DR drop is minimized compared to FIG. There is no particular problem by lowering the L-side voltage, and there is no problem if the pinning voltage is reached. FIG. 6C shows a method in which the L side voltage is lowered only in the initial part of the high speed transfer part, instead of the method of lowering the initial frequency of the high speed transfer part shown in the second embodiment. This makes it possible to prevent a drop in DR at the initial stage of transfer, and to obtain the same effect as that of the second embodiment.

FIG. 6D is a timing chart of drive pulses when a still image is picked up by a video camera or the like by the electrode drive device of the present CCD. By lowering the L-side voltage of the sweep section and lowering the transfer frequency of the high-speed transfer section (the blanking period can be ignored), the DR becomes higher than in the conventional case. FIG. 2E shows that the L-side voltage of the sweep section is lowered and the L-side voltage of the high-speed transfer section of φV1 and φV3 is also lowered. As described in the conventional example, since φV1 and φV3 have more severe waveform distortion than φV2 and φV4, only the L side drive voltage (absolute value) “φV1, φ
The DR improvement effect is larger when V3> φV2, φV4 ”is set. Even when there is no problem of the driver IC breakdown voltage,“ φV1, φV3> φV2, φV4 ”(absolute value)
Needless to say, the one who realizes the relationship is DR size.

The fourth embodiment of the present invention will be described with reference to FIG. 7 which is a block diagram including the electrode driving device of the CCD. The feature of this embodiment is that the conventional φV
1 to φV4 are changed to φV1 to
It has been changed to φV8. That is, φV1 to φV8
The drivers 21 to 28 are provided corresponding to
Drive the CD20.

FIG. 9 is a potential operation diagram of this embodiment. FIG. 9A is a potential operation diagram of the sweeping section in the present embodiment, where φV1 and φV2, φV3 and φV
4, ..., φV7 and φV8 as a set, and φV1 to φV8
It is driven so as to form one cycle. In the high-speed transfer unit, as shown in (b) of the figure, φV1 to φV4 and φV5
The drive is performed so that one cycle is constituted by ~ V8. When the above method is used, if the sweep frequency and the high-speed transfer frequency applied to each gate are the same, the number of gate stages capable of transferring per unit time is larger in FIG.

For example, at t = 1 in FIG. 9A, φV1
And the electric charge stored under φV2 is φ at t = 4.
Transfer to V7 and φV8. However, the figure (b)
At t = 4, only φV4 is transferred. Therefore, the sweep time is half that of the conventional method, and this time can be used for high-speed transfer. Therefore, since the high-speed transfer frequency can be lowered, the waveform rounding is reduced and D
R can be expanded. Further, since the number of drivers is doubled, the load capacity to be driven per driver is halved, and the waveform rounding is further reduced, so that DR is significantly improved. At the time of sweeping, φV1, φV2, and φV3
, And φV4, ..., φV7 and φV8 have been described as being driven simultaneously, but by shifting each phase, CSD (Charge Sweep)
It goes without saying that there is no problem even if the same operation is performed.

In this embodiment, eight drivers are used, the sweep period is set to eight-phase drive, and the four-phase drive is performed during high-speed transfer. However, 4n drivers and 4n sweep periods are used.
Phase driving may be performed and high-speed transfer may be four-phase driving. However, in this case, n is an integer of 2 or more.

A fifth embodiment of the present invention will be described with reference to FIG. 8 which is a block diagram including the electrode drive device of the CCD. In this embodiment, φV1 to φV
4 is supplied to the drivers 31 to 34 and further supplied to the impedance conversion circuit 35, and then the CCD 30 is driven. As shown in the conventional example, the driver has an output resistance (20 to 30Ω), which also contributes to the waveform rounding. Therefore, in this embodiment, the output resistance is set to several Ω by the impedance conversion circuit 35, and C
Drive the CD 30. As a result, waveform rounding is reduced,
DR is improved.

If a push-pull type emitter follower or voltage follower is used, the output resistance 2
3Ω can be realized.

[0049]

As is apparent from the above, according to the present invention, the dynamic range of the VCCD can be improved with a simple structure, which is extremely effective in practice.

[Brief description of the drawings]

FIG. 1 is a CCD according to a first embodiment of the present invention.
Timing chart showing the timing of the electrode driving method of

FIG. 2 is a CCD according to a second embodiment of the present invention.
Timing chart showing the timing of the electrode driving method of

FIG. 3 is a timing chart showing the timing of a CCD electrode driving method in the case where the first embodiment and the second embodiment are combined.

FIG. 4 is a CCD according to a third embodiment of the present invention.
Block diagram including the electrode drive device

FIG. 5 is a timing chart for explaining the principle of drive pulses by the CCD electrode drive device according to the third embodiment.

FIG. 6 is a timing chart showing timings of drive pulses by a CCD electrode drive device according to a third embodiment.

FIG. 7 is a CCD according to a fourth embodiment of the present invention.
Block diagram including the electrode drive device

FIG. 8 is a CCD according to a fifth embodiment of the present invention.
Block diagram including the electrode drive device

FIG. 9 is a potential operation diagram of a drive pulse by the electrode drive device of the CCD according to the fourth embodiment.

FIG. 10 is a block diagram of a conventional FIT CCD.

FIG. 11: Driving pulse supplied to FIT CCD

FIG. 12 is a detailed timing chart of drive pulses.

FIG. 13 is a sectional view of a VCCD.

FIG. 14 is an explanatory diagram of a drive pulse in consideration of waveform rounding.

[Explanation of symbols]

 1, 20, 30 are CCDs, 2, 21-28, 31-34, 80-83 are drivers 9, 10 are buffer circuits, 3 and 4 are select circuits 5-8 are H and L voltage setting circuits 35 are impedance conversion Circuit 84 is an oxide film, 85 is a light-shielding film, and 86 is an interlayer film.

Claims (8)

[Claims] 1. A drive pulse having a duty different from the duty of a drive pulse in a frame transfer period applied to each of first-phase and third-phase electrodes of a four-phase electrode structure CCD included in a frame / interline type charge transfer device. Is a driving pulse applied to each of the second-phase and fourth-phase electrodes of the CCD in the frame transfer period, and the electrode driving method of the CCD. 2. The duty of the drive pulse applied to each of the first-phase and third-phase electrodes of the CCD is 50% in the frame transfer period, and the duty of the second-phase and fourth-phase electrodes of the CCD is The duty of the drive pulse applied to each frame transfer period is 5
CCD according to claim 1, characterized in that it is greater than 0%.
Electrode driving method. 3. The drive pulse in the frame transfer period applied to each of the first to fourth phase electrodes of the four-phase electrode structure CCD of the frame interline type charge transfer device has at least two different duty cycles. A method for driving an electrode of a CCD, comprising a pulse. 4. A first drive means for applying a drive pulse to each of the first-phase electrodes of the four-phase electrode structure CCD included in the frame / interline type charge transfer element, and the application by the first drive means. Drive pulse having the same duty as the drive pulse applied to each of the third-phase electrodes of the CCD, and a frame applied by the first drive means and the third drive means. Second driving means for applying a driving pulse having a duty different from that of the driving pulse in the transfer period to each of the second phase electrodes of the CCD in the frame transfer period, the first driving means and the third driving means. A drive pulse having a duty different from the drive pulse applied in the frame transfer period is applied to each of the fourth phase electrodes of the CCD in the frame transfer period. And a fourth driving means for driving the electrode of the CCD. 5. A first application of a drive pulse including at least two different duty pulses to each of the electrodes of the first phase in the frame transfer period of the four-phase electrode structure CCD included in the frame interline charge transfer device. Drive means for applying a drive pulse including at least two pulses of different duty to each of the electrodes of the second phase in the frame transfer period of the CCD, and the second drive means in the frame transfer period of the CCD. Third driving means for applying a driving pulse including pulses having at least two different duties to each of the three-phase electrodes, and at least two different duties to each of the fourth-phase electrodes in the frame transfer period of the CCD. And a fourth drive means for applying a drive pulse including a pulse of Electrode drive device. 6. A selecting means for selecting a voltage setting means for applying a predetermined voltage from a plurality of voltage setting means for applying different voltages, and a voltage applied by the voltage setting means selected by the selecting means. Buffer means for inputting and outputting the input voltage with low impedance, and inputting the voltage output by the buffer means, and using the input voltage, driving each of the electrodes of at least one phase of the CCD And an electrode driving device for a CCD. 7. A driver means, which is a multiple of 4 larger than 4, for driving each electrode of each phase of an electrode structure CCD having a phase of multiple of 4 larger than 4 in a frame interline type charge transfer device. , In the case of the sweep period, set the phase of multiples of 4 larger than 4 to 1
As a unit, each driver means is provided with a first drive control means for driving each electrode of each phase of the CCD, and in the case of a frame transfer period for performing high-speed transfer, each driver means is provided with each CCD An electrode driving device for a CCD, comprising: second drive control means for driving each phase electrode in four phases. 8. A drive unit for applying a drive pulse and a drive pulse applied by the drive unit are input, and the input drive pulse is output to each of at least one phase electrode of the CCD with low impedance. An electrode driving device for a CCD, comprising: an impedance conversion means.