JP2693426B2 - Sampling hold circuit - Google Patents

Description

The present invention relates to a sampling and holding circuit suitable for use in, for example, an output section of a solid-state imaging device. SUMMARY OF THE INVENTION The present invention is a sampling and holding circuit suitable for use in, for example, an output section of a solid-state imaging device, in which a signal input terminal is connected to one controlled electrode of one conductivity type transistor and Of the conductive type transistor, the capacitor is connected to the other controlled electrode of the other conductive type semiconductor element, and the sampling pulse is supplied to the control electrode of the one conductive type transistor and the other conductive type is connected. By supplying a pulse having a phase opposite to that of the sampling pulse to the control electrode of the semiconductor element and obtaining a sampling hold signal at both ends of the capacitor, a good sampling hold signal without noise components can be obtained. When used in the output section of a solid-state imaging device, a signal obtained by sampling and holding the charge detection signal well Is supplied to a low-pass filter so that a good video signal can be obtained. [Prior Art] Conventionally, as shown in FIG. 5, a sampling and holding circuit used for an output section of a solid-state imaging device has been proposed. The sampling and holding circuit shown in FIG. 5 includes a charge detection signal obtained in the charge detection unit of the solid-state imaging device,
For example, as shown in FIG. 6 A, a charge detection signal input terminal to which a charge detection signals S ₁ having a detected signal voltage level _{E 1, E 2, E 3} ··· voltage E ₀ as the reference voltage is supplied An n-channel MOS field effect transistor (hereinafter referred to as “n”) forming a switching element through (1) via a buffer amplifier (2).
-MOS FET) (3) and the gate electrode of this n-MOS FET (3) is supplied with a sampling pulse φ _S1 synchronized with the charge detection signal S ₁ as shown in FIG. 6B. Connected to the sampling pulse input terminal (4) and grounded via the drain electrode holding capacitor (5) of the n-MOS FET (3).
It is configured by connecting the midpoint of connection between the drain electrode of the MOS FET (3) and one end of the capacitor (5) to the sampling hold signal output terminal (7) via the buffer amplifier (6). However, in this sampling and holding circuit configured in this way, the sampling pulse φ _S1 is n
When supplied to the gate electrode of the -MOS FET (3), the n-MOS
A noise signal S _N1 having a waveform obtained by differentiating the sampling pulse φ _S1 as shown in FIG. 6C is generated due to the gate-drain capacitance of the FET (3), and this noise signal S _N1 is the charge detection signal S Superimpose ₁ on the sampled part, so
The sampling hold signal S ₂ in this case is the sixth
As shown in FIG. D, not only the noise signal S _N1 component is included, but also the signal S ₂ is held at the lower end voltage of the noise signal S _N1 component, and the voltage that should be held originally is
There is a disadvantage that a sampling hold signal holding E ₁ , E ₂ , E ₃ ... Can not be obtained. Therefore, a sampling and holding circuit as shown in FIG. 7 has also been proposed. The sampling and holding circuit shown in FIG.
This P-FET is provided with a P-channel MOS type field effect transistor (hereinafter referred to as P-MOS FET) (8) while having the same configuration as the sampling and holding circuit of the conventional example.
The source electrode and drain electrode of (8) are respectively n-MOS FE
The gate electrode of this P-MOS FET (8) is connected to the source electrode and drain electrode of T (3) and is connected to the n-MOS FET.
The sampling pulse φ _S1 supplied to (3) and a pulse φ _S2 having a phase opposite to that shown in FIG. 8D are supplied to the anti-phase pulse input terminal (9). The sampling and holding circuit of the conventional example shown in FIG.
When a reverse phase pulse φ _S2 is supplied to the gate electrode of the -MOS FET (8), a noise signal S _N2 as shown in Fig. 8E due to the gate-source capacitance of the P-MOS FET (8) is generated. occurs allowed, i.e., caused to generate noise signal S _N1 and the noise signal S _N2 reverse phase shown in FIG. 8 C generated when supplying sampling pulses phi _S1 shown in FIG. 8 B to the n-MOS FET (3) , The noise signal S _N1 is canceled by the noise signal S _N2 , and the signal component of the charge detection signal S ₁ shown in FIG. [Problems to be Solved by the Invention] However, in the sampling and holding circuit of the conventional example shown in FIG. 7, when the DC level of the charge detection signal changes, the gate-source voltage of the n-MOS FET (3) and P
-Since the gate-source voltage of the MOS FET (8) differs, depending on the level of the DC level of the charge detection signal, the n-MOS FET (3) is cut off and the P-MOS FET is cut off.
There is a difference from the cutoff of (8). That is, when the signal voltage level of the charge detection signal S ₁ is high, the n-MOS FET
(3) cuts off before the P-MOS FET (8),
On the contrary, when the signal voltage level is small, the P-MOS FET (8) is n
-Cut off before MOS FET (3). Therefore, the output signal S ₃ is a noise signal when the signal voltage level is high as shown in FIG. 8F, for example, when it is the voltage E _1.
Even if the front _ends of S _N1 and S _N2 cancel each other, the noise signal S
The rear end portion of _N2 is superposed on the charge detection signal S ₁ and the upper end voltage of this noise signal S _N2 component is held, and when the signal voltage level is low, for example, the charge detection signal S 1 _{When 1} is voltage E ₃ , noise signals S _N1 and S _N2
Even if the front ends of the noise signals S _N1 cancel each other, the rear ends of the noise signals S _N1 are superimposed on the sampling parts of the charge detection signal S ₁ , and the lower end voltage of the noise signal S _N1 components is held. As described above, the sampling and holding circuit of the conventional example shown in FIG. 7 has a disadvantage that it cannot obtain the sampling and holding signal holding the voltages E ₁ , E _3, ... The present invention has been made in view of the above circumstances, and an object thereof is to provide a sampling and holding circuit capable of obtaining a good sampling and holding signal in which a voltage to be originally held is held. [Means for Solving Problems] A sampling and holding circuit according to the present invention has a signal input terminal connected to one controlled electrode of a transistor and a capacitor and another semiconductor element provided on the other controlled electrode of the transistor. The other semiconductor element connected is a semiconductor element having an electrode having a diffusion layer of a conductivity type different from the majority carrier of the transistor connected to the other controlled electrode of the transistor and a control electrode adjacent to the electrode. , The electrode having a diffusion layer of a conductivity type different from the majority carrier of the transistor is disconnected from the signal input terminal,
Moreover, no electrical input is made, and a sampling pulse is supplied to the control electrode of the transistor and a pulse having a phase opposite to the sampling pulse is supplied to the control electrode of the another semiconductor element, and both ends of the capacitor are supplied. A sampling hold signal is obtained. [Operation] According to the present invention, the sampling pulse φ _S1 supplied to the control electrode of the one conductivity type transistor (3)
Since the pulse φ _S2 supplied to the control electrode of the semiconductor element (10) of the other conductivity type and the pulse φ _{S2 of} the other conductivity type have opposite phases, the control electrode of the transistor (3) of one conductivity type and the controlled electrode of the other The noise signal S _N1 generated due to the capacitance between the two and the noise signal S _N3 generated due to the capacitance between the control electrode and the controlled electrode of the other conductivity type semiconductor element (10) have an antiphase relationship. Become a signal. Further, in this case, according to the present invention, since the input signal S ₁ passes through only the transistor (3) of the first conductivity type and is supplied to the capacitor (5), the transistor (1) of the first conductivity type ( 3) and the second conductivity type semiconductor element (10) regardless of the cut-off timing, the noise signals S _N1 and S _N3 cancel each other out, and sampling is performed by the first conductivity type transistor (3). The noise signal S _N1 or S _N3 will not be superimposed on the input signal thus generated. [Embodiment] With reference to FIGS. 1 to 4, the present invention will be described with reference to an embodiment of the sampling and holding circuit of the present invention. As in the prior art of FIG. Let's take the case of applying the above as an example. In FIGS. 1 to 4, parts corresponding to FIGS. 5 to 8 are denoted by the same reference numerals, and detailed description thereof will be omitted. In this example, as in the conventional example of FIG. 5, the charge detection signal input terminal (1) is connected to the n-MO via the buffer amplifier (2).
This n-MOS is connected to the source electrode of S FET (3)
The gate electrode of the FET (3) is connected to the sampling pulse input terminal (4) to which the sampling pulse φ _S1 synchronized with the charge detection signal S ₁ is supplied as shown in FIG. 3B. In addition, the drain electrode of the n-MOS FET (3) is grounded via the holding capacitor (5) and the n-MO
The midpoint of connection between the drain electrode of the S FET (3) and one end of the capacitor (5) is connected to the sampling hold signal output terminal (7) via the buffer amplifier (6). Moreover, in this example, as shown in FIG.
T (10) is provided, the drain electrode (10D) of the P-MOS FET (10) is connected to the drain electrode (3D) of the n-MOS FET (3), and the gate electrode (10G) is connected to the reverse phase pulse input terminal. Connect to (9). In this case, regarding the P-MOS FET (10), the source electrode is not provided and the gate
The drain capacitance is made equal to the gate-drain capacitance of the n-MOS FET (3). In FIG. 2, (3S) and (3G) are the source and drain electrodes of the n-MOS FET (3), (11) is a P-type silicon substrate,
(12S) and (12D) are n-MO made of N-type diffusion regions, respectively.
Source region and drain region of the S FET (3), (13) N well, (14S) and (14D) are P-MOS FET (10) source region and drain region respectively composed of P type diffusion regions, (15) ), (16) and (17) are insulating layers, respectively. In the sampling and holding circuit of this example configured as described above, the charge detection signal S ₁ supplied to the charge detection signal input terminal (1) is sampled by the n-MOS FET (3) which is switched by the sampling pulse φ _S1 . The sampled signal voltage is held by the capacitor (5), and the held voltage is obtained at the sampling hold signal output terminal (7) via the buffer amplifier (6). Also in this example, when the sampling pulse φ _S1 shown in FIG. 3B is supplied to the gate electrode of the n-MOS FET (3), it is caused by the gate-drain capacitance of the n-MOS FET (3). Although the noise signal S _N1 as shown in FIG. 3C is generated, the anti-phase pulse φ _S2 shown in FIG. 3 D, which is in the anti-phase relationship of the sampling pulse φ _S1 , becomes the P-MOS FET (1
0) gate electrode of P-MOS FET
Since the noise signal S _N3 as shown in FIG. 2E due to the gate-drain capacitance of (10) is generated, the noise signal S _N1 is canceled by this noise signal S _N3 . In this case, in this example, the charge detection signal S ₁ is P-MO.
Since it does not pass S FET (10) but only n-MOS FET (3), n-MOS FET (3) and P
The noise signal S _N1 will be canceled by the noise signal S _N3 regardless of the cutoff timing of the -MOS FET (10). As described above, in this example, the noise signals S _N1 and S _N3 are made to completely cancel each other, so that the charge detection signal S ₁ shown in FIG. 3A is the sampling pulse S shown in FIG. 3B. ₁
And a good sampling and holding signal S ₄ having no noise component as shown in FIG. 3F can be obtained, and therefore, it can be obtained by a low pass filter (not shown).
When supplying to, a good video signal can be obtained. Although the drain region (14D) and the source region (14S) are provided in the P-MOS FET (10) in the above embodiment, the source region is replaced by the source region as shown in FIG. 4 instead. It is also possible to provide only the drain region (14D) without providing it, and in this case as well, the same operational effect as described above can be obtained. Further, in the above embodiment, the switching element is n
-A MOS FET (3) is provided, and the FET that supplies the reverse phase pulse is P
Although the -MOS FET (10) is used, a P-MOS FET may be provided as a switching element and the FET that supplies a reverse phase pulse may be an n-MOS FET instead. Can be obtained. The present invention is not limited to the above-described embodiments, and it goes without saying that various other configurations can be adopted without departing from the gist of the present invention. EFFECTS OF THE INVENTION According to the present invention, in addition to the first conductivity type transistor (3) for sampling the input signal by the sampling pulse φ _S1, the second conductivity type semiconductor element (that does not pass the input signal) 10) is provided, and the transistor (3) of the first conductivity type is provided in the semiconductor element of the second conductivity type.
To generate a noise signal S _N2 in opposite phase relationship and noise signal S _N1 occur, because it is made so as cancel the noise signal S _N1 in this noise signal S _N2, the first conductivity type of the transistor (3) And the noise signal S _{N1 is changed} to the noise signal S _N1 regardless of the cutoff timing of the second conductivity type semiconductor element (10).
_N3 is the advantage that it is possible to obtain complete sampling hold signal S ₄ no noise component canceled by.
Therefore, when the present invention is used in the output section of a solid-state image pickup device, there is an advantage that a good video signal in which a signal obtained by sampling and holding a charge detection signal is supplied to a low pass filter can be obtained.

BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1 and 2 are block diagrams respectively showing an embodiment of a sampling and holding circuit of the present invention, FIG. 3 is a diagram for explaining the example of FIG. 1, and FIG. FIG. 5 is a block diagram showing another embodiment of the invention, FIG. 5 is a block diagram showing a conventional sampling and holding circuit, FIG. 6 is a diagram for explaining the example of FIG. 5, and FIG. FIG. 8 is a configuration diagram showing another example, and FIG. 8 is a diagram used for explaining the example of FIG. (1) is a charge detection signal input terminal, (3) is an n-MOS FE
T, (4) is a sampling pulse input terminal, (5) is a capacitor, (7) is a sampling hold signal output terminal, and (10) is a P-MOS FET.

   ────────────────────────────────────────────────── ─── Continuation of front page    (72) Inventor Yasuhito Mashiro               6-7-35 Kita Shinagawa, Shinagawa-ku, Tokyo So               Knee Co., Ltd.                (56) References JP-A-61-129964 (JP, A)                 JP 58-121831 (JP, A)

Claims (1)

(57) [Claims] A signal input terminal is connected to one controlled electrode of the transistor, and a capacitor and another semiconductor element are connected to the other controlled electrode of the transistor, and the other semiconductor element is connected to the other controlled electrode of the transistor. A semiconductor element having an electrode having a diffusion layer of a conductivity type different from that of the majority carriers of the connected transistor and a control electrode adjacent to the electrode, and an electrode having a diffusion layer of a conductivity type different from the majority carriers of the transistor is a signal input. The terminal is not connected, and no electrical input is made.A sampling pulse is supplied to the control electrode of the transistor and a pulse having a phase opposite to the sampling pulse is supplied to the control electrode of the other semiconductor element. It is characterized in that a sampling and holding signal is supplied to both ends of the above capacitor. Sampling hold circuit.