JP3858281B2 - Sample / hold circuit, charge transfer device using the same, and drive method of charge transfer device - Google Patents

Description

[0001]
[Industrial application fields]
The present invention relates to a sample / hold circuit, a charge transfer device using the same, and a method for driving the charge transfer device , and more particularly to a sample / hold circuit for performing a signal voltage hold process on an input signal and a charge transfer using the same. The present invention relates to a device and a method for driving a charge transfer device .
[0002]
[Prior art]
FIG. 6 shows an example of a sample / hold circuit used for an output circuit of a CCD delay element, for example. The sample / hold circuit 60 includes an input buffer 61, a transmission gate NchMOS transistor 62 having a drain connected to the output end of the input buffer 61, one end connected to the source of the MOS transistor 62, and the other end The hold capacitor 63 is connected to the ground (ground) line, and the output buffer 64 is connected to the other end of the hold capacitor 63 at the input end.
[0003]
[Problems to be solved by the invention]
This sample / hold circuit is usually fabricated on the same substrate (chip) as other circuits such as a CMOS circuit. Here, for example, in a CMOS circuit, a through current flows between a power supply and a ground in a signal transient portion, and the power supply level or the ground level varies due to this. This is the power supply noise (a) and the ground noise (b) in FIG. Both of these noises (a) and (b) usually fluctuate in opposite directions. This kind of noise component also arises from other circuits in the same chip.
[0004]
In this state, when the input signal (c) in FIG. 7 is sampled by the sample / hold (S / H) pulse (d), the ground line of the hold capacitor 63 is caused by a noise component as shown in FIG. 7 (b). Since it fluctuates, as shown in FIG. 7, the actual output signal (f) is influenced by the noise component with respect to the ideal sample / hold output signal (e). That is, there is a problem that the noise component is superimposed on the signal component, resulting in signal level fluctuations or unnecessary coupling.
[0005]
The present invention has been made in view of the above problems, and an object of the present invention is to provide a sample / sample that can reduce signal level fluctuations due to noise components generated due to operations of other circuits in the same chip. An object of the present invention is to provide a hold circuit, a charge transfer device using the hold circuit, and a driving method of the charge transfer device .
[0006]
[Means for Solving the Problems]
A sample / hold circuit according to the present invention is a sample / hold circuit for processing an output signal of a charge-voltage converter in a charge transfer device, and includes a first capacitor connected between a signal line and a power supply line, A second capacitor connected between the line and the ground line, the ground as a substrate, the power line is patterned, and the power line has a higher resistance component than the ground line. The capacitance value of the first capacitor is set to be larger than the capacitance value of the second capacitor in accordance with the level difference of the noise component of the power supply line that is larger than the noise component of the ground line that is generated in this manner. Yes.
[0007]
In addition, the charge transfer device according to the present invention includes a charge transfer unit that transfers a signal charge, a charge-voltage conversion unit that detects a signal charge transferred by the charge transfer unit and converts the signal charge into a voltage, a signal line and a power supply line, First and second capacitors connected to the ground line, respectively, sample / hold the output signal of the charge-voltage conversion unit, use the ground as a substrate, pattern the power line, According to the level difference of the noise component of the power supply line which is larger than the noise component of the ground line generated due to the resistance component being higher than that of the ground line, the capacitance value of the first capacitor is set to the second value. The sample / hold circuit is set to be larger than the capacitance value of the capacitor.
[0008]
[Action]
In the sample / hold circuit having the above configuration, the capacitance value added to the signal line is a combination of the capacitance values of the first and second capacitors when viewed in an alternating manner. Therefore, by setting the composite capacitance value to a capacitance value necessary for the sample / hold processing, the conventional circuit in which the capacitor having the capacitance value is connected between the signal line and the ground line (or power supply line). The same processing can be performed. In addition, both the power line noise and the ground line noise are superimposed on the signal line via the first and second capacitors, but the power line noise and the ground line noise usually fluctuate in opposite directions. Therefore, both noise components cancel each other on the signal line.
[0009]
In the charge transfer device configured as described above, the signal charge is transferred by the charge transfer unit, converted into a voltage by the charge voltage conversion unit, and then supplied to the sample / hold circuit. In the sample / hold circuit, the capacitance value added to the signal line is a combination of the capacitance values of the first and second capacitors when viewed in an alternating manner. Therefore, desired signal processing can be realized by setting this combined capacitance value to a capacitance value necessary for the sample / hold processing. In addition, both the power line noise and the ground line noise are superimposed on the signal line via the first and second capacitors, but the power line noise and the ground line noise usually fluctuate in opposite directions. Therefore, both noise components cancel each other on the signal line.
[0010]
【Example】
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
FIG. 1 is a circuit diagram showing a first embodiment of the present invention applied to, for example, a sample / hold circuit. 1, a sample / hold circuit 10 includes an input buffer 11, an NchMOS transistor 12 for transmission gate having a drain connected to the output terminal of the input buffer 11, and a source of the MOS transistor 12 via a signal line L1. A first hold capacitor 13 having one end connected and the other end connected to a first power supply (Vdd) line, and a ground (one end connected to the signal line L1 and the other end being a second power supply line) The second hold capacitor 14 is connected to the (ground) line, and the output buffer 15 is connected to the signal line L1 at the input end. A sample / hold (S / H) pulse is applied to the gate of the MOS transistor 12.
[0011]
In the above circuit configuration, when it is assumed that the levels of both noise components on the power supply line and the ground line are substantially equal, the capacitance values of the first and second hold capacitors 13 and 14 are set to substantially equal values. The In addition, when a sample / hold circuit that performs signal processing equivalent to that of the conventional circuit of FIG. 6 is configured, the capacitance values of the first and second hold capacitors 13 and 14 are the values of the hold capacitor 63 of FIG. It is set to approximately ½ of the capacitance value.
[0012]
That is, when the capacitance value of the hold capacitor 63 in the conventional circuit of FIG. 6 is C0 and the capacitance values of the first and second hold capacitors 13 and 14 in the circuit of this embodiment are C1 and C2, each capacitance value is It has the following relationship.
[Expression 1]
C0 = C1 + C2
That is, the capacitance value added to the signal line L1 is the same in the case of the conventional circuit of FIG. 6 and the circuit according to the present embodiment when viewed in an alternating manner.
[0013]
Next, the circuit operation of the sample / hold circuit 10 having the above configuration will be described with reference to the waveform diagram of FIG. By the way, the sample / hold circuit 10 is usually fabricated on the same substrate (chip) as other circuits such as a CMOS circuit. For example, in a CMOS circuit, a through current is generated between the power supply and the ground in a signal transient portion. By flowing, the power supply level or the ground level changes. This is the power supply noise (a) and the ground noise (b) in FIG. Both of these noise components (a) and (b) usually fluctuate in opposite directions, and are also generated due to the operation of other circuits in the same chip.
[0014]
In such a state, when the input signal (c) in FIG. 2 is sampled by the sample / hold (S / H) pulse (d), the noise component (a of both the power line and the ground line is applied to the signal line L1. ) And (b) are superimposed via the first and second capacitors 13 and 14. At this time, as described above, since the noise components (a) and (b) of both the power supply line and the ground line usually fluctuate in opposite directions, the noise components (a) and (b) on the signal line L1. ) Will cancel each other. As a result, in the actual output signal (f) of the sample / hold, the influence of the coupling is small, and the fluctuation of the signal level due to this is reduced, resulting in a waveform close to the ideal output signal (e).
[0015]
In the present embodiment, the capacitance values of the first and second hold capacitors 13 and 14 are set to substantially equal values. However, the present invention is not limited to this, and the noise component of the power supply line and the ground line are not limited thereto. It is also possible to set arbitrarily according to the level difference from the noise component. For example, when the sample / hold circuit 10 is manufactured on the same chip as other circuits, the resistance of the power line is higher than that of the ground line by using the ground as a substrate and the power line as a pattern wiring. For this reason, the level of the noise component tends to be higher in the power supply line than in the ground line.
[0016]
Thus, when the level of the noise component of the power supply line is larger than the level of the noise component of the ground line, the capacitance value C1 of the first hold capacitor 13 is changed to the capacitance value of the second hold capacitor 14 according to the level difference. By setting it to be larger than C2, the levels of both noise components are substantially equal on the signal line L1, and the directions of the noise components are opposite, so they cancel each other. In other words, by appropriately setting the capacitance values of the first and second hold capacitors 13 and 14, it is possible to cope with a case where there is a level difference between the noise components of the power supply line and the ground line.
[0017]
FIG. 3 is a circuit diagram showing a second embodiment of the present invention applied to, for example, an operational amplifier having a phase compensation capacitor. In FIG. 3, a pair of NchMOS transistors Q1 and Q2 have their sources connected in common and their gates connected to input terminals 31 and 32, respectively. The MOS transistors Q1 and Q2 constitute a differential amplifier 33 together with a constant current source NchMOS transistor Q3 connected between each source common connection point N1 and the ground. A predetermined bias voltage Vgg is applied to the gate of the MOS transistor Q3. The drains of the Pch MOS transistors Q4 and Q5 are connected to the drains of the MOS transistors Q1 and Q2, respectively.
[0018]
In the MOS transistors Q4 and Q5, the gates are connected in common, the sources are connected to the power supply (Vdd) line, and the gate and drain of the MOS transistor Q4 are connected in common, whereby the current mirror circuit 34 is connected. Is configured. The gate of the Nch MOS transistor Q6 is connected to the drain common connection point N2 of the MOS transistors Q2 and Q5 via the signal line L2. The MOS transistor Q6 has a drain connected to the power supply line and a source connected to the output terminal 35. The MOS transistor Q6 constitutes an output buffer 36 having a source follower circuit configuration together with a constant current source NchMOS transistor Q7 whose drain is connected to the source and the source is grounded. A bias voltage Vgg is applied to the gate of the MOS transistor Q7.
[0019]
In the operational amplifier 30 configured as described above, the first phase compensation capacitor 37 is connected between the signal line L2 to which the gate of the MOS transistor Q6 of the output buffer 36 is connected and the power supply (Vdd) line, and the signal line L2 is connected to the signal line L2. A second phase compensation capacitor 38 is connected between the ground line. In other words, the first and second phase compensation capacitors 37 and 38 are provided to prevent oscillation caused by the phase turning of the signal on the signal line L2 and perform phase compensation. Normally, only one phase compensation capacitor is connected between the power supply line or ground line and the signal line L2. On the other hand, this embodiment employs a configuration in which the capacitance value of the single phase compensation capacitor is equally divided into two parts and replaced as the first and second phase compensation capacitors 37 and 38, for example.
[0020]
Next, the circuit operation of the operational amplifier 30 configured as described above will be described. By the way, when the operational amplifier 30 is manufactured on the same chip as another circuit, for example, a CMOS circuit or the like, a through current flows between the power source and the ground in the signal transient portion in the CMOS circuit, so that the power level or the ground level Fluctuate, and this becomes power supply noise and ground noise. This kind of noise is generated not only from the CMOS circuit but also from other circuits. As described above, when signal processing is performed in a state where power supply noise and ground noise are generated, the noise components of both the power supply line and the ground line are caused by the first and second phase compensation capacitors 37 and 38 to the signal line L2. It will be superimposed via.
[0021]
At this time, since the noise components of both the power supply line and the ground line usually fluctuate in opposite directions, both noise components cancel each other on the signal line L2. As a result, the output signal of the output buffer 36 is less affected by coupling, and the signal level fluctuation due to this is also reduced. That is, since the capacitance value added to the signal line L2 is a combination of the capacitance values of the first and second phase compensation capacitors 37 and 38 when viewed in an alternating manner, the original phase compensation effect is maintained. However, it is possible to suppress superimposition of noise components of the power supply line and the ground line on the signal line L2.
[0022]
Note that the operational amplifier 30 according to the present embodiment can be used as an operational amplifier constituting the output buffer 15 in the sample / hold circuit 10 of FIG. 1, for example. Also in this embodiment, as in the case of the first embodiment, the capacitance values of the first and second phase compensation capacitors 37 and 38 are determined by the noise component of the power supply line and the noise component of the ground line. It can be arbitrarily set according to the level difference. As a result, it is possible to cope with a case where there is a level difference between the noise components of the power supply line and the ground line.
[0023]
FIG. 4 is a circuit diagram showing a third embodiment of the present invention applied to, for example, a CR low pass filter (LPF). In FIG. 4, one end of a resistor 42 is connected to the input terminal 41, and the other end of the resistor 42 is connected to the output terminal 43 via a signal line L3. A first LPF capacitor 44 is connected between the signal line L3 and the power supply (Vdd) line, and a second LPF capacitor 45 is connected between the signal line L3 and the ground line. The first and second LPF capacitors 44 and 45 constitute a CR low-pass filter 40 together with the resistor 42. Normally, only one capacitor constituting the low-pass filter is connected between the power supply line or ground line and the signal line L3. On the other hand, this embodiment employs a configuration in which the capacitance value of the single LPF capacitor is equally divided into two parts and replaced with the first and second LPF capacitors 44 and 45, for example.
[0024]
Next, the circuit operation of the LPF 40 configured as described above will be described. By the way, when the LPF 40 is manufactured on the same chip as another circuit, for example, a CMOS circuit or the like, a through current flows between the power source and the ground in the signal transient portion in the CMOS circuit, so that the power level or the ground level varies. This becomes power supply noise and ground noise. This kind of noise is generated not only from the CMOS circuit but also from other circuits. As described above, when the filtering process is performed in a state where the power supply noise and the ground noise are generated, the noise components of both the power supply line and the ground line are included in the first and second LPF capacitors 44 and 45 to the signal line L3. It will be superimposed via.
[0025]
At this time, since the noise components of both the power supply line and the ground line usually fluctuate in opposite directions, both noise components cancel each other on the signal line L3. As a result, the output signal of the LPF 40 is less affected by coupling, and the signal level fluctuation due to this is also reduced. That is, since the capacitance value added to the signal line L3 is a combination of the capacitance values of the first and second LPF capacitors 44 and 45 when viewed in an alternating manner, the effect of the original filtering process is maintained. However, it is possible to suppress the noise component of the power supply line and the ground line from being superimposed on the signal line L3.
[0026]
In the third embodiment, as in the first and second embodiments, the capacitance values of the first and second LPF capacitors 44 and 45 are set to the noise component of the power supply line and the ground. It can be arbitrarily set according to the level difference from the noise component of the line. As a result, it is possible to cope with a case where there is a level difference between the noise components of the power supply line and the ground line.
[0027]
FIG. 5 is a schematic configuration diagram showing a charge transfer device according to the present invention, for example, a CCD delay element, using the sample / hold circuit 10 according to the first embodiment as a part of the output circuit. In FIG. 5, a CCD delay element 50 includes a charge input unit 51 that injects a signal charge corresponding to a signal input IN, a CCD charge transfer unit 52 that transfers the injected signal charge, and a CCD charge transfer unit 52. The charge-voltage conversion unit 53 that detects the signal charge transferred in this way and converts it into a voltage, and the output circuit 54 that performs predetermined signal processing on the output signal of the charge-voltage conversion unit 53.
[0028]
In the CCD delay element 50 configured as described above, as the charge input unit 51, a known structure such as a diode cut-off method or a charge preset method can be used. Further, as the charge-voltage converter 53, a well-known structure such as a floating diffusion method or a floating gate method can be used. The output circuit 54 is provided for performing signal processing such as sample / hold on the output signal of the charge-voltage converter 53. As the sample / hold circuit constituting a part of the output circuit 54, the sample / hold circuit 10 according to the first embodiment described above is used.
[0029]
In this way, by using the sample / hold circuit 10 according to the first embodiment for the output circuit 54 of the CCD delay element 50, for example, the output circuit 54 can be connected to other circuits such as the drive circuit of the CCD charge transfer unit 52. In the case of being manufactured on the same chip, even if noise is applied to the power supply line or the ground line due to other circuit operations, the signal line of the noise component is obtained by the operation described in the first embodiment. Since it is possible to suppress the superimposition on, it becomes strong against noise.
[0030]
In this example, the case where the sample / hold circuit 10 according to the first embodiment is used as a circuit constituting a part of the output circuit 54 of the CCD delay element 50 has been described. However, the present invention is not limited to this. Instead, it can be similarly used as a circuit constituting a part of an output circuit of a charge transfer unit such as a CCD area sensor or a CCD linear sensor. The present invention is not limited to the application to the sample / hold circuit 10, the operational amplifier circuit 30 and the CR low-pass filter 40 shown in the first to third embodiments. The present invention can be applied to all signal processing circuits having a capacitor connected to a line.
[0031]
【The invention's effect】
As described above, according to the present invention, the first capacitor connected between the signal line and the power supply line and the second capacitor connected between the signal line and the ground line are provided. The ground line is a substrate, the power line is patterned, and the power line has a higher noise component than the ground line due to a higher resistance component than the ground line . By adopting a configuration in which the capacitance value of the first capacitor is set to be larger than the capacitance value of the second capacitor according to the level difference, noise components generated in the first and second power supply lines are displayed on the signal line. Since they can cancel each other, it is possible to suppress the superimposition of noise components on the signal line.
[Brief description of the drawings]
FIG. 1 is a circuit diagram showing a first embodiment of the present invention applied to a sample / hold circuit.
FIG. 2 is a waveform chart according to the first embodiment.
FIG. 3 is a circuit diagram showing a second embodiment of the present invention applied to an operational amplifier having a phase compensation capacitor;
FIG. 4 is a circuit diagram showing a third embodiment of the present invention applied to a low-pass filter.
FIG. 5 is a schematic configuration diagram showing a CCD delay element according to the present invention.
FIG. 6 is a circuit diagram showing a conventional example.
FIG. 7 is a waveform diagram according to a conventional example.
[Explanation of symbols]
10 sample / hold circuit 13 first hold capacitor 14 second hold capacitor 30 operational amplifier 37 first phase compensation capacitor 38 second phase compensation capacitor 40 CR low pass filter 44 first LPF capacitor 45 second LPF Capacitors L1, L2, L3 signal lines

Claims (3)

A sample / hold circuit for processing an output signal of a charge-voltage converter in a charge transfer device,
A first capacitor connected between the signal line and the power line;
A second capacitor connected between the signal line and the ground line ;
The level of the noise component of the power supply line is larger than the noise component of the ground line generated due to the resistance component being higher than that of the ground line. A sample / hold circuit, wherein the capacitance value of the first capacitor is set to be larger than the capacitance value of the second capacitor according to the difference. A charge transfer section for transferring signal charges;
A charge-voltage converter that detects and converts the signal charge transferred by the charge transfer unit into a voltage;
The first and second capacitors are connected between the signal line, the power supply line, and the ground line, respectively, and process the output signal of the charge-voltage conversion unit. The ground is used as a substrate, and the power supply line is patterned. The power supply line has a resistance component higher than that of the ground line, and the first capacitor has the first capacitor in accordance with the level difference of the noise component of the power supply line that is larger than the noise component of the ground line . A charge transfer device comprising: a sample / hold circuit that sets a capacitance value larger than a capacitance value of the second capacitor. Driving a charge transfer device having first and second hold capacitors connected between a signal line, a power supply line, and a ground line, and having a sample / hold circuit for processing an output signal of the charge-voltage converter A method,
The level of the noise component of the power supply line is larger than the noise component of the ground line generated due to the resistance component being higher than that of the ground line. A method for driving a charge transfer device, wherein the capacitance value of the first hold capacitor is set larger than the capacitance value of the second hold capacitor in accordance with the difference.

Images