JPH01171315A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To allow the fluctuation of an input signal of a 1st input stage gate to follow noise of VCC or ground and to improve the V1H(V), V1L(V) margin of an external input signal in its increasing direction by connecting the input 1st stage gate input terminal, a power supply VCC or ground by a capacitive element. CONSTITUTION:An external input signal is supplied from a pad 11 in a 1st input stage and the 1st input stage gate input signal to a 1st input stage circuit 13 is formed in the inside through an input protection circuit 12. The 1st input stage gate input terminal (node N1) and the power supply VCC are connected by a capacitor C1 in the circuit above so as to allow the waveform fluctuation level of the node N1 to follow the noise generated in the VCC.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to semiconductor integrated circuits, and particularly to noise countermeasures at the first input stage.

[Prior Art] Conventionally, in the first input stage of this type of semiconductor integrated circuit, an external input signal is inputted from a pad 21, and is further internally passed through an input protection circuit 22 to be used as an input first stage gate input signal. This is shown in Figure 2-a. In the figure, the transistor (hereinafter abbreviated as Tr) Ql is a P-channel field effect MO5)
transistor, Q2 is N-channel field effect MO5)
Although the description will be made using a transistor, the basic concept remains the same even if other field effect transistors are used. Although a CMOS inverter type circuit is used as the input first stage circuit 23, the basic concept remains the same even if a NOR type, NAND type, or NMOS type circuit is used.

Here, see Figures 2-a and 2-b regarding the VIH and VIL characteristics when power supply ■CC or ground noise occurs.
Add explanation using diagrams. Figure 2-b shows electric RV CC,
It represents the relative amount of noise at ground and node N1 in Figures 2-8.

Now, suppose that a large load (wire resistance, wiring capacitance, etc.) is attached between the external signal input pad 21 and the gate input in the first input stage 23 due to the mask design. At this time, as shown in FIG. 2-b, if a certain noise is applied to the ground of the power supply VCC1, the load applied to the node N1 is heavy, so that the level fluctuation of the waveform due to the noise becomes dull. This results in a difference in the amount of amplitude due to noise between the power supply CC ground and the node N1.

In Figure 2-b, the power supply VCC at point a.

The difference in amplitude caused by noise △Va (V) between the ground level and the level of node N1 is VCC, and the relative level of node N1 with respect to the ground level has decreased by △Va (V), that is, the external input level is △ It has the same effect as lowering Va (V). Therefore, VIH (V) in the external input signal is VIH (V) min = VIHO (V) - Va (V) (
Here, VIHO is VIH (V) min when there is no noise.
).

Therefore, ΔVa (V), VIH (7) The margin will deteriorate due to noise.

In Figure 2-b, the amplitude difference △Vb (V) caused by noise between the levels of the voltage gvcc and the ground and the node N1 at point) b is VCC, the relative level of the node N1 with respect to the ground level is △ It has the same effect as if the external input level were increased by Va (V), that is, the external input level was increased by Δvb (V). For this reason, VIL (V) in the external input signal is VIL
(V)rnax=VILo(V)+ΔVb(V) (here, VILO is the value of VIL(V)max when there is no noise). Therefore, the margins of ΔVb (V) and VIL will deteriorate due to noise.

In Figure 2-b, the amplitude distortion difference △VC at point c is similar to the amplitude difference △vb at point b mentioned above, the margin of VIL (L) in the external input signal is reduced by noise to △VC (V). (V I L (V
) ma, x = VI LO (V) + VC (V)).

In Figure 2-b, the amplitude difference △Vd at point) d is similar to the amplitude difference △Va at point a mentioned above, the margin of VIH (V) in the external input signal is reduced by △Vd (V) due to noise. to aggravate (VIH(V)mi
n=VIHo(V)−ΔVd(V)).

Here, the difference between ΔVa (V) and ~'d(V), and between Δvb(v) and ΔVC(V) is due to the difference in the direction of initial noise generation.

Also, the fluctuation due to noise at node N level becomes smaller as the load related to it becomes heavier, so conversely, △Va (V)
, △Vb(V), △VC(V).

△Vd(V) becomes larger, therefore VIH(V).

This results in a worse VIL(V) margin.

[Problems to be Solved by the Invention] The first input stage of the conventional semiconductor integrated circuit described above employs a method in which an external signal is input from the pad 21, and is further passed through an input protection circuit internally to become the first input stage gate input signal. Therefore, if a heavy load is attached to the wiring between the pad 21 and the input first stage gate due to the mask design, the fluctuation of the input first stage gate input signal will not be able to follow the noise of VCC and ground, and as a result, the VIH of the external input signal will increase. (V), VIL
(, V>This method has the disadvantage of deteriorating the margin.

[Differences between the invention and the prior art] With respect to the gate input signal at the first input stage of the conventional semiconductor integrated circuit described above, the present invention provides
By connecting the capacitor to CC or ground, the input first stage gate input signal follows the fluctuation of VCC or ground, and VIH (.

V), VIL (V) has the difference of improving the margin.

[Means for Solving the Problems] The present invention provides a semiconductor integrated circuit comprising an input section to which an external input signal is supplied, and an input first stage circuit having a gate connected to the input section. The gist is that a capacitor is interposed between the note connected to the input first-stage circuit and the power supply voltage and/or ground.

[Example: Supranasal Fart] Next, an example of the present invention will be described with reference to the drawings.

FIG. 1a is a circuit diagram showing a first embodiment of the present invention. FIG. 1-b shows the relative noise amount (with and without capacitance) of the power supply VCC9 grounded in this embodiment and the node N1 in FIG. 1-a.

In this embodiment, as shown in Fig. 1-a, by connecting the input first-stage gate input signal (node Nl in Fig. 1-a) and the power supply VCC with a capacitor C1, this capacitor generates a voltage at VCC. The waveform fluctuation level of the node N1 is made to follow the noise generated. In the figure, 11 is a pad, 12 is an input protection circuit, and 13 is an input first stage circuit.

Now, when a certain noise is added to VCC as shown in Figure 1-b, if the capacitor according to this embodiment is not attached, as explained in the conventional example, the VIH (V) due to the noise is
H(V)min=VIHO(V)−△Va(V),
Or VIH(V)min=VIHO(V)-
ΔVd (V). Also, VIL (V) is VIL (
V) max=VIL.

(V)+△Vb(V) or VIL(V)ma
x=VILO(V)+ΔvC(v).

Here, by connecting the capacitor according to this embodiment between vCC and node N1, the noise generated at vCC is
It is transmitted to the node N1 via the capacitor ff1c1 in the figure, and therefore the capacitor ff1c1 has the effect of forcing the level of the node N1 to follow the VCC noise. As a result, node N1
The waveform is shown by the dotted line in FIG. 1-b.

Figure 1-b, point) power supply VCC at point a.

The difference in amplitude amount ΔVa' (V) caused by noise between the ground level and the level of node N1 is smaller than the difference in amplitude amount ΔVA (V) when there is no capacitor C1.

Therefore, by adding a capacitor C1, the VI of the external input signal
H(V) is VIH(V)min=VIH0(V)-△V
a' (V) (here△Va' (V)ku△Va
(V)), △VIH(V) = △Va - △Va'
The margin of VIH (V) is improved by (V). However, the value of ΔVIH (V) depends on the magnitude of the capacitance tc1.

Difference in amplitude caused by noise between the levels of power supply V CC, ground and node N1 at point) b in Figure ib) △
Vb' (V) is smaller than the amplitude difference ΔVb (V) in the case where the capacitor ff1c1 does not exist.

Therefore, by adding a capacitor C1, the external input signal V
IL (V) is V I L (V) max=V I L
O (V) + △Vb' (V) (here △Vb' (
V) △Va(V)), △VIL(V)=△Vb
The margin of vIL(V) is improved by -ΔVb'(V). However, the value of △VIL (V) also depends on the capacitance C
It depends on the size of 1.

VIL of the external input signal at point C in Figure 1-b (
Is V) at point b? [Same as VIL(V)v I L
(V)max=VI LO(V)+△■cl (Here, △Vc'(V)<△Vc(V)), △VI
L (V) = △Vc - △Vc' VIL (
V) margin will be improved.

VIH (of the external input signal at point) d in Figure 1-b
V) is similar to VIH(V) at point a.
H(V)min=VIHO(V)−△Vd'
(V) (Here, Δvd(V)<Vd(V)), and the margin of VIH(V) is improved by ΔVIH(V)”ΔV d−ΔVd′ (V).

As explained above, by connecting node N1 and VCC with a capacitor, VCC and ground noise can follow the level fluctuation of node N1, and external input signal (7) VIH (V)
, VIL (V) The margin can be improved. Further, the degree of margin improvement can be easily set by changing the size of the capacitor C1.

Further, the embodiment is particularly effective against noise in the power supply VCC when the amounts of power supply VCC and ground noise are different.

y)0 Poor Example A second embodiment of the present invention is shown in FIG. 1-C. In this embodiment, the capacitor ff1c1 that was provided between the node N1 and VCC in the first embodiment is provided between the node N1 and the ground. As a result, the level fluctuation of the node N1 follows the power supply V CC and ground noise, and the external input signal V I H (V),
V I L (V) Merge'/a improve. This operating principle is exactly the same as the first embodiment.

This embodiment is effective when there is no margin for creating a capacitance between the node N1 and VCC due to mask design.

Further, this embodiment is particularly effective against ground noise when the power supply V CC and ground noise are different.

Figures 1-d show a third embodiment of the present invention. In this embodiment, capacitances are provided between the node N1, the power supply V CC and the ground, respectively, and this is effective against noise from both V CC and the ground. External input signal VIH (V), VIL (
V) The principle of margin improvement is exactly the same as in the first and second embodiments.

[Effects of the Invention] As explained above, the present invention connects the input first stage gate input signal and VCC or ground with a capacitive element, thereby making the noise of VCC and ground follow the fluctuation of the input first stage gate input signal. , external input signal (7) VI
This has the effect of widening the H(V) and VIL(V) margins.

[Brief explanation of the drawing]

Fig. 1-a is a circuit diagram showing a first embodiment of the present invention;
Figure b is a waveform diagram showing the relative noise amount of the power supply VCC, grounding, and input first stage gate input signal according to the present invention, and Figures 1-a and 1-d represent the second and third embodiments of the present invention, respectively. Figure 2-a is a circuit diagram showing a conventional example;
Figure 1-b is a waveform diagram showing the relative noise amounts of VCC, ground, and input first stage gate input signals in the conventional example. 11...Input bad, 12...Input protection circuit, 13...Input first stage, 01-C2...Capacitance. Agent Patent Attorney Kiyoshi Kuwai - 8 Figure 1-b Figure 2-Pen

Claims (1)

[Scope of Claims] A semiconductor integrated circuit comprising an input section to which an external input signal is supplied, and an input first stage circuit having a gate connected to the input section, wherein: A semiconductor integrated circuit characterized in that a capacitor is interposed between a node and a power supply voltage and/or ground.