JP3148061B2 - Comparator circuit with built-in dynamic hiss - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a comparator circuit, and more particularly to a comparator circuit formed by an integrated circuit.

[0002]

2. Description of the Related Art In a comparator circuit, in order to prevent chattering from occurring at the time of output switching,
Dynamic hissing is performed. Conventionally, in a comparator circuit formed by an integrated circuit, a capacitor for creating dynamic hiss is externally provided to the integrated circuit.

FIG. 15 shows an example of the circuit. In the figure,
Comparator circuit 1 is formed in an integrated circuit IC, that - on the side input with the input terminal terminal IN _1, + side input terminal to the input terminal IN _2, connects the output to the output terminal OUT.
The input terminal I
A series circuit of a capacitor C and a resistor R between the N ₂ and the output terminal OUT is connected. In the comparator circuit 11, the input voltage V _IN to the input terminal IN ₁ is an input terminal IN
_The threshold level V _TH is input to 2 and the output terminal OU
The output is taken from T.

FIG. 16 shows an outline of dynamic hiss.
This will be described with reference to FIG. Figure 16 shows the relationship between the input voltage V _IN and the output voltage V _OUT in the absence of dynamic hysteresis, Figure 16 shows the relationship between the input voltage V _IN and the output voltage V _OUT in the circuit of FIG. 15 with a dynamic hysteresis. First, a case where the comparator circuit 1 has no dynamic hysteresis will be described. As shown in FIG. 16, when the input voltage _VIN is equal to the threshold level V _{TH at the} points A and B.
When the voltage becomes larger or smaller, the output voltage V _OUT switches. However, the noise included in the input waveform causes the input voltage V _{IN to change.}
Crosses the threshold level V _TH many times, the output switches each time, and chattering occurs in the output voltage V _OUT , which may cause a malfunction.

On the other hand, in the circuit of FIG. 15 with dynamic hysteresis, as shown in FIG. 17, when the input voltage V _IN becomes larger or smaller than the threshold level V _{TH at the} points A and B, the output voltage V _OUT There was inverted, the output voltage V _{OU T} which changed the cut is superimposed on the input terminal iN ₂ through the capacitor C, to reduce or increase the threshold level V _TH. Thereafter, the threshold level V _TH returns to its original value at a certain time constant τ due to the charging or discharging of the capacitor C. However, the input voltage V _IN including noise does not cross the threshold level V _TH due to dynamic hiss, so that chattering occurs. Does not occur.

[0006]

In the above-described conventional comparator circuit with dynamic hysteresis,
A capacitor C for creating dynamic hiss must be connected outside the integrated circuit IC. Also, when the threshold level V _TH is created inside the integrated circuit IC, the input terminal IN is used to connect a capacitor.
₂ has to be provided. Furthermore, the time constant τ of the dynamic hiss fluctuates due to the resistance existing in the external circuit to which the comparator circuit is connected,
There is a problem that a constant time constant τ cannot be obtained.

According to the present invention, in a comparator circuit formed by an integrated circuit, occurrence of chattering due to high-frequency noise is prevented by adding dynamic hysteresis.
It is another object of the present invention to eliminate the need to connect a capacitor for creating dynamic hiss outside the integrated circuit.

[0008]

In order to achieve the above object, the present invention relates to a comparator circuit formed by an integrated circuit, comprising: a base (at least one transistor of a differential pair); For example, a capacitor formed in an integrated circuit for providing dynamic hysteresis is connected between the bases of the output transistors.

[0009]

According to the above means, when the input voltage becomes larger or smaller than the threshold level and the output voltage is switched, the base voltage of the output transistor (or the preceding transistor) is connected to the transistor of the differential pair via the capacitor. , And instantaneously fluctuates the base voltage. As a result, the dynamic hiss is attached and chattering can be prevented. In addition, since the capacitor can be formed in the integrated circuit by the above means, it is not necessary to externally connect the capacitor.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below with reference to the drawings. In the drawings below, components having the same function are denoted by the same reference numerals, and redundant description will be omitted. ( Base Technology ) FIGS. 1 to 4 show circuit diagrams of the base technology of the present invention. 1 shows a PNP input comparator circuit, FIG. 2 shows a comparator circuit having an improved input voltage range, FIG. 3 shows an NPN input comparator circuit, and FIG. 4 shows a comparator circuit having an improved input voltage range. In the present embodiment, between the bases of the output transistors Q ₉ of one of the differential transistors Q ₄ of the transistors Q _2, Q ₄ of the differential pair,
It is characterized by connecting a capacitor C ₁ for applying a dynamic hysteresis. Since the other parts of the circuits of FIGS. 1 to 4 are well known as comparator circuits,
The description here is omitted.

Hereinafter, the comparator circuit shown in FIG.
This will be described with reference to the waveform diagram of FIG. FIG.
Circuit input voltage V_IN, Threshold level V_TH, Output power
Pressure V _OUTShows the relationship. In the circuit of FIG.
V_INIs applied to the input terminal + IN, and the threshold level
V_THIs described below as being applied to the input terminal -IN.
I will tell. Input voltage V applied to input terminal + IN_INIs
Resistance R₁Through one of the transistors Q of the differential pair_TwoNo
Applied to the source. The threshold applied to the input terminal -IN
Old level V_THIs the resistance R_TwoThrough the other of the differential pair
Transistor Q_FourApplied to the base. Output terminal OU
T is the power supply V_CCAnd an output transformer connected via a resistor R.
Jista Q₉Drawn from the collector. And thread
Shoulder level V_THIs applied to the differential transistor Q_Four
Base and output transistor Q₉Between the base of the die
Capacitor C for adding natural hiss₁Is connected
You.

At the point A in FIG._INBut
Threshold level V_THWhen larger, the differential
Star Q_TwoBase voltage V_B2Is the differential transistor Q_FourNo
Source voltage V_B4Larger, the transistor Q₇Is on
Output transistor Q ₉Is the power supply voltage
V_BEIt decreases from (V) to 0 (V). This will output
Transistor Q₉Turns off and the output voltage V_OUTIs 0
Ra V_CCChanges to

[0013] Simultaneously, the output transistor with decreasing V _BE component of the base voltage of Q _9, the base voltage V _B4 differential transistor Q ₄ which is connected via a capacitor C ₁ is V _TH -V from the threshold level V _TH It decreases instantaneously to _BE . Thereafter, the capacitor C ₁ is charged with a time constant τ = R ₂ C ₁ (where R ₂ is a resistor connected between the input terminal −IN and the capacitor C ₁ ), and the base voltage V of the differential transistor Q _{4. B4} is returned to the original threshold level V _TH.

During this time, even if there is noise in the input voltage,
Dynamic transistor Q_FourBase voltage V _B4Greatly fluctuates
Therefore, the differential transistor Q_TwoBase voltage V_B2But
Crossing will no longer occur and chattering may occur.
And not. Therefore, the dynamic hiss width V_BEAt time
A dynamic hiss with a time width determined by the constant τ is obtained.
You.

Next, at the point B in FIG._INBut
Threshold level V_THWhen smaller, Transis
TA Q₇Is turned off, so that the output transistor Q₉
Base voltage is from 0 to V_BETo increase. With this
Force transistor Q₉Turns on and the output voltage V_OUTIs V
_CCFrom 0 to 0. At the same time, the output transistor Q ₉
V of base voltage of_BEThe capacitor C₁To
Differential transistor Q connected through_FourBase voltage V
_B4Also threshold level V_THTo V_TH+ V_BEMomentary until
To increase. Then, the capacitor C₁Is the time constant τ = R_Two
By discharging at C, the differential transistor Q_FourBee
Voltage V_B4Is the original threshold level V _THReturn to.
As a result, the same dynamic noise as at the point A is obtained.
Is obtained.

As described above, according to this embodiment,
Chattering does not occur because dynamic hysteresis is applied to the comparator circuit. Moreover, because this capacitor C ₁ for applying a dynamic hysteresis can be formed in an integrated circuit, it is not necessary to connect a capacitor for applying a dynamic hysteresis external to the integrated circuit. Furthermore, it is not necessary to provide an external terminal for connecting to the capacitor in the integrated circuit.

(Embodiment 1 ) Next, a description will be given of a comparator circuit which can obtain a time constant of dynamic hysteresis larger than that of the comparator circuit of the base technology and can further prevent chattering by increasing the duration of the dynamic hysteresis. . FIG. 6 shows the PN
FIG. 7 shows a P-input comparator circuit, and FIG. 7 shows an NPN-input comparator circuit. Of these circuits, the comparator circuit of FIG. 6 will be described with reference to the waveform diagram of FIG.

In this embodiment, the transistor of the differential pair
The transistor Q connected to Darlington₁, Q_Two
And Q_Three, Q_FourIt consists of. Input terminal -IN is a resistor
R₁Darlington connection transi
First stage transistor Q ₁Connected to the base.
The input terminal + IN is connected to the resistor R_TwoOne side of the differential pair through
First stage transistor of Darlington connection transistor
Q_ThreeConnected to the base. The output terminal OUT is connected to the power supply V
_CCOutput transistor Q connected to the₉of
Drawn from the collector.

[0019] Oite to this embodiment, a capacitor attaching a dynamic hysteresis is provided in the following two places. First,
Capacitor C ₁ is connected between the base of the preceding transistor Q ₈ of the base and the output transistor Q ₉ of the transistor Q ₄ of the second-stage differential transistor input terminal + IN side. Further, the output and the second stage base of the transistor Q ₂ of the differential transistor input terminal -IN-side transistor Q
Capacitor C ₂ is connected between the base _9.

Hereinafter, a threshold level is applied to the input terminal + IN.
Le V_THIs applied, and the input voltage V is applied to the input terminal -IN._INMark
It will be described as being added. Now, at point A in FIG.
And the input voltage V_INIs the threshold level V_THBigger
Then, the differential transistor Q _TwoBase voltage V_B2Is differential
Transistor Q_FourBase voltage V_B4Larger,
Transistor Q₇Is turned on and the transistor Q₈No
Source voltage is V_BEFrom 0 to 0. This allows the tiger
Transistor Q₈Is off, transistor Q₉Is turned on,
Output voltage is from 0 to V_CCChanges to

[0021] At the same time, the transistor with decreasing base voltage of Q _8, the base voltage V _B4 also the threshold level of the differential transistors Q ₄ of the second stage which is connected via a capacitor C ₁ V _TH from V _TH -V _BE To decrease instantaneously. Thereafter, the capacitor C ₁ is charged and the differential transistor Q
₄ of the base voltage V _B is returned to the original threshold level V _TH. At this time, the capacitor C _1, because that would be charged by the base currents of the differential transistors Q _4, is the time constant τ becomes as follows in equation (1).

[Equation 1] τ = V_BE・ C₁/ (I₁/ Β) (where I₁Is the differential transistor Q_FourEmitter current
And β is the current amplification factor) Next, as shown at point B in FIG._INIs thread
Shoulder level V_THWhen smaller, differential transistors
TA Q_TwoBase voltage V_B2Is the differential transistor Q _FourBee
Voltage V_B4Transistor Q₇Is off,
Transistor Q ₈Is turned on and the output transistor Q
₉Base voltage is V_BEFrom 0 to 0. This
Output transistor Q₉Is turned off and the output voltage becomes 0
To V_CCChanges to

At the same time, as the base voltage of the transistor Q ₉ decreases, the base voltage V _{B2 of} the second-stage differential transistor Q ₂ connected via the capacitor C ₂ also increases.
It decreases momentarily from _IN to V _IN -V _BE . Thereafter, the capacitor C ₂ is discharged, the base voltage V _B2 of the differential transistor Q ₂ is returned to the original input voltage V _IN. At this time, the capacitor C _1, because that would be charged by the base currents of the differential transistors Q _4, is the time constant τ becomes as follows in expression (2).

[Equation 2] τ = V _BE · C ₂ / (I ₁ / β) (where I ₁ is the emitter current of the differential transistor Q ₂ and β is its current amplification factor) In the embodiment, the capacitors C ₁ and C ₂ connected between the differential transistor and the output transistor are charged by the base currents of the differential transistors Q ₄ and Q ₂ . It can be larger than that of the base technology . Therefore, the time width of the dynamic hysteresis can be increased, and the occurrence of chattering during the operation of the comparator circuit can be more reliably prevented.

(Embodiment 2 ) In the base technology and the embodiment 1 described above, the dynamic hysteresis width is as large as V _BE (V). Therefore, the input terminal -I
If the voltage level at the N or + IN is low, when the switching of the output transistor Q ₅ or Q ₇ is without operation sometimes comparator circuit to malfunction. On the other hand, the input voltage range can be improved by setting the width of the dynamic hiss to an arbitrary value smaller than V _BE . This example will be described below.

FIGS. 9 and 10 show a comparator circuit according to this embodiment. These comparator circuits are based on the prerequisite techniques described above.
Operator configured substantially similar to the comparator circuit shown in FIG. 1 and FIG. 3 is that the capacitor C ₁ in series to a resistor R ₃ to give a dynamic hysteresis is connected to the comparator circuit of FIG. 1 and FIG. 3 Different. The resistance R ₃
Becomes to be connected to the connected resistor R ₂ in series with the input terminal -IN.

The operation of these comparator circuits is also a prerequisite technique.
It performs the same operation in surgery. However, when the switching of the output, the base voltage of the output transistor Q ₉ is decreased or increased by V _BE, the V _BE is the resistance R ₂ and the resistor R ₃
Divided by the base voltage V of the differential transistor Q ₄ by
Superimposed on _B4 . As a result, variation namely dynamic hysteresis width of the base voltage V _B4 differential transistor Q ₄ are look like the following Formula 3, the time constant τ is as [Equation 4].

[Equation 3] Dynamic Hiss width = V _BE · R ₂ / (R ₂ + R ₃ ) [Equation 4] Time constant τ = (R ₂ + R ₃ ) · C ₁ Therefore, according to this embodiment, the resistance By setting the resistance value of R ₃ to an appropriate value, the dynamic hiss width is
It can be adjusted to any value smaller than _BE (V), and the time constant τ can be increased.

The present embodiment is not limited to the comparator circuits shown in FIGS. 1 and 3, and can be applied to other comparator circuits. Embodiment 3 In the PNP input comparator circuit shown in FIG. 6 in Embodiment 1 described above, the voltage level of the input terminal −IN to which the input voltage V _IN is applied cannot be set to 0 (V) and used. This is because the instantaneous base voltage of the differential transistors Q ₄ and the voltage level of the input terminal -IN is 0 (V) is the V _BE, and the transistor Q ₇ is turned on, the base voltage of the differential transistor Q ₄ is 0 The emitter voltage of the differential transistor Q ₄ becomes V _BE (V),
This is because the transistor Q ₇ may not be able to operate.

On the other hand, the PNP shown in FIG.
In the input comparator circuit, 0 is input to the input terminal -IN.
Third Embodiment A third embodiment in which an input voltage that changes with reference to (V) can be applied will be described below. FIG. 11 shows a circuit diagram, and FIG. 12 shows a waveform diagram thereof. Transistors Q ₁₁ , Q ₁₂ and Q ₁₃ , Q ₁₂ connected in two stages to the bases of transistors Q ₂ , Q ₄ of the differential pair, respectively.
₁₄ is connected. These transistors Q ₁₁ and Q ₁₂ and Q ₁₃ and Q ₁₄ each constitute a level shift circuit.
Then, the first stage of the first level shift circuit the base of the transistor Q ₁₁ is connected to the input terminal + IN, based of the preceding transistor Q ₈ of the base and the output transistor Q ₉ of the transistor Q ₁₂ of the second stage capacitor C ₁ for applying a dynamic hysteresis is connected between.

The first level shift circuit of the second level shift circuit
Transistor Q₁₃Is connected to the input terminal -IN.
And the second-stage transistor Q₁₄Base and output transition
Star Q ₉Transistor Q provided two stages before_TenNo
Condensed to make dynamic hiss between
Sa C_TwoIs connected. Comparators configured as above
In the data circuit, the input terminal + IN
Input voltage V_INIs applied and the input terminal -IN is grounded.
When connected to GND, each transistor Q of the differential pair_Twoof
Base voltage V_B2And transistor Q_FourBase voltage V_B4
Are as shown in FIG. 12, respectively. That is,
Force terminal + IN side differential transistor Q_TwoThe base voltage of
V_IN+ 2V_BEAnd the input terminal-IN side differential transistor
Star Q_FourBase voltage is 0 + 2V_BE(= V_TH).

Next, the operation of this comparator circuit will be described.
Will be explained. Input voltage V_INDecreases and crosses the zero potential
Then, as shown at point A in FIG.
_TwoBase voltage V_B2Is the differential transistor Q_FourBase of
Voltage_B4Lower, the transistor Q₇Is off
And the output transistor Q₉Turns on, and the output voltage becomes V
_CCFrom 0 to 0.

At the same time, the transistor Q₈Of the base voltage
The capacitor C₁Connected via
Jista Q₁₂Of the differential transistor Q
_TwoBase voltage V_B2Is V_IN+ 2V_BETo V_IN+ V_BEUntil
It decreases instantaneously. Then, the capacitor C₁Is charged
And the differential transistor Q_TwoBase voltage V_B2Is the original V _IN
+ 2V_BEReturn to.

On the other hand, when the input voltage V _IN is zero potential cross increasing, as shown in point B in FIG. 12, the base voltage of the differential transistors Q ₄ V _B4 differential transistor Q ₂ of the base voltage V _B2 be higher, transistor Q ₇ is turned on. Accordingly, the output transistor Q ₉ is turned off, the output voltage changes from 0 to V _CC. At the same time, with a decrease in the base voltage of the transistor Q _10, the capacitor C
Connected base voltage of the transistor Q ₁₄ to ₂ decreases, the base voltage V _B4 differential transistor Q ₄ is instantaneously decreased from 0 + 2V _BE threshold level V _TH to 0 + V _BE. Thereafter, the capacitor C ₂ is charged, the base voltage V _B4 differential transistor Q ₄ are returned to 0 + 2V _BE in the original threshold level V _TH.

As described above, according to this embodiment,
Even in the case of processing a small signal from a sensor or the like based on the zero potential, dynamic hysteresis can be applied to prevent output chattering. Further, in the above comparator circuit described, so as to switch the base voltage V _B4 differential transistor Q ₄ in two stages, an example which is adapted chattering can more reliably prevented.

FIG. 13 is a circuit diagram thereof, and FIG. 14 is a waveform diagram thereof. Figure 13 is differs from the FIG. 11 described above, the differential resistor R ₄ between the transistor Q ₁₄ of the base and the level shift circuit of the transistor Q ₄ is connected, further base and the ground GND of the differential transistors Q ₄ The point where the switch SW and the current source 2I ₁ are connected between them is shown in FIG.
Same as 1. Then, the switch SW is configured to be switched on at the switch off, off Q ₇ ON of the transistor Q _7. Although a detailed description of the switch SW is omitted, the switch SW is formed by a well-known transistor circuit.

[0037] Thus, as shown in FIG. 14, the base voltage V _B4 differential transistor Q ₄ are, the transistor Q ₇
On and the switch SW off, but the usual 0 + 2V _BE, transistor Q ₇ off, when the switch SW turned on, reduced by hysteresis width R ₄ · I _1. Therefore, the relationship between the input voltage V _IN and the threshold level is as shown in FIG. 14, and the change in the threshold level is added to the dynamic hysteresis when the output is switched, so that chattering can be more reliably prevented.

[0038]

According to the present invention, in a comparator circuit formed by an integrated circuit, the occurrence of chattering due to high frequency noise is prevented by providing dynamic hysteresis, and a capacitor for creating dynamic hysteresis is provided outside the integrated circuit. This eliminates the need to connect to In addition to this, dynamic hiss is optimal
In this way, chattering can be reliably prevented.

[Brief description of the drawings]

FIG. 1 is a first circuit diagram of a base technology of the present invention.

FIG. 2 is a second circuit diagram of the base technology of the present invention.

FIG. 3 is a third circuit diagram of the base technology of the present invention.

FIG. 4 is a fourth circuit diagram of the base technology of the present invention.

FIG. 5 is a waveform chart of the circuit of FIG. 1;

[6] a first circuit diagram of the first embodiment of the present invention.

FIG. 7 is a second circuit diagram according to the first embodiment of the present invention.

FIG. 8 is a waveform chart of the circuit of FIG. 6;

FIG. 9 is a first circuit diagram according to a second embodiment of the present invention.

[10] The second circuit diagram of a second embodiment of the present invention.

FIG. 11 is a first circuit diagram according to a third embodiment of the present invention.

FIG. 12 is a waveform chart of the circuit of FIG. 11;

FIG. 13 is a second circuit diagram according to the third embodiment of the present invention.

FIG. 14 is a waveform chart of the circuit in FIG. 13;

FIG. 15 is a circuit diagram of a conventional comparator circuit.

FIG. 16 is a waveform chart for explaining dynamic hiss.

FIG. 17 is a waveform chart of the circuit of FIG. 15;

[Explanation of symbols]

1: Comparator circuit Q: Transistor C: Capacitor R: Resistance -IN, + IN: Input terminal OUT: Output terminal _VIN : Input voltage _VOUT : Output voltage _VTH : Threshold level

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-3-90868 (JP, A) JP-A-63-20912 (JP, A) JP-A-5-102800 (JP, A) JP-A-50- 80750 (JP, A) JP-A-57-111116 (JP, A) JP-A-55-93133 (JP, U) (58) Fields investigated (Int. Cl. ⁷ , DB name) G01R 19/00-19 / 32 H03K 5/00-5/02 H03K 5/08-5/12

Claims (3)

(57) [Claims] In a comparator circuit formed by an integrated circuit, a transistor of a differential pair is formed by a Darlington connection transistor, and is connected to a base of each second stage transistor of the Darlington connection transistor and a line whose potential changes according to the logic of the comparator. A dynamic hysteresis comparator circuit, wherein a capacitor formed in the integrated circuit for applying dynamic hysteresis is connected. 2. A comparator circuit formed by an integrated circuit, wherein a level shift circuit is provided between the differential pair and each input terminal, and the potential is determined by the logic of the comparator and the base of each second stage transistor of each level shift circuit. A dynamic hysteresis comparator circuit characterized by connecting a capacitor to a changing line. 3. A dynamic hysteresis built comparator circuit according to claim 1 or 2, characterized in that by connecting a resistor for time constant adjusting to the capacitor in series.