JPH0486119A - Buffer circuit - Google Patents

Abstract

PURPOSE:To prevent a reverse voltage in excess of base-emitter reverse breakdown voltage from being applied to a transistor(TR) by connecting a capacitor between a base of a 2nd NPN TR and a signal input terminal. CONSTITUTION:In the transient state where an input signal changes from a high level to a low level, since a capacitor 7 acts like quickening a base drawing speed for an NPN TR 2, the speed when the NPN TR 2 is turned off is quickened. On the other hand, in the transient state where the input signal changes from a low level to a high level, the bias of the NPN TR 2 depends on an N-channel MOS TR 5 and a resistor 6, but since the capacitor 7 is connected between the input terminal and a base of the NPN TR 2, the capacitor 7 acts like quickening the speed of bias voltage setting, then the speed when the NPN TR 2 is turned on is quickened.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a buffer circuit configured with a BiCMO5 semiconductor integrated circuit.

[Prior Art] Conventionally, a circuit shown in FIG. 5 has been known as a buffer circuit configured with a BiCMO8 semiconductor integrated circuit.

Power supply V. A first NPN transistor 1 is connected between 0 and the output terminal, and a first NPN transistor 1 is connected between the output terminal and the ground terminal.
A second NPN transistor 2 is connected. A P-channel transistor 3 is connected between the power supply terminal and the base of the NPN transistor 1, and an N-channel MOS transistor 4 is connected between the base of the NPN transistor 1 and the ground terminal. These MOS transistors 3 and 4 have their gates connected to each other, and invert and amplify the input signal input to their common gate to generate an NPN signal.
It constitutes a CMOS inverter that drives transistor 1. Further, an N-channel MOS transistor 5 is connected between the output terminal and the base of the NPN transistor 2, and a resistor 6 is connected between the base of the NPN transistor 2 and the ground terminal. The N-channel MOS transistor 5 performs switching according to an input signal input to its gate, and drives the NPN transistor 2.

Next, the operation of the buffer circuit configured as described above will be explained.

When the input signal is at low level, P channel MOS transistor 3 is turned on and N channel MOS transistor 4 is turned on.
．． Since transistor 5 is turned off, NPN transistor 1 is turned on. Furthermore, since the base of the NPN transistor 2 is pulled down by the resistor 6, it is turned off. As a result, the output signal becomes high level.

On the other hand, when the input signal is high level, P channel M
Since OS transistor 3 is turned off and N channel MOS transistors 4 and 5 are turned on, NPN transistor 1 is turned off. Further, at this time, a current flows through the N-channel MOS transistor 5 to the resistor 6 and the base of the NPN transistor 2, so that the NPN transistor 2 is turned on.

As a result, the output signal becomes low level.

Problems to be Solved by the Invention In the conventional buffer circuit described above, in order to turn on the NPN transistor 2, a current is applied to the base of the NPN transistor 2 and the resistor 6 through the N-channel MOS transistor 5 to create a bias. There must be. Therefore, when the input signal switches from low level to high level, there is a delay in the ON operation of the NPN transistor 2, and there is also a delay in switching the output signal to low level.

On the other hand, as for NPN transistor 1, there is no delay and its base is quickly pulled to low level by N-channel MOS transistor 4, so a reverse voltage is applied between the base and emitter of NPN transistor 1, and the base - There was a problem that the emitter reverse breakdown voltage was exceeded.

The present invention has been made in view of such problems, and it prevents the application of a reverse voltage exceeding the base-emitter reverse breakdown voltage during the switching operation of the NPN transistor in the output stage, thereby achieving excellent reliability. The purpose of this invention is to provide a buffer circuit with improved performance.

[Means for Solving the Problems] A buffer circuit according to the present invention includes a first NP whose collector is connected to a high potential side power supply and whose emitter is connected to an output terminal.
a second NPN transistor whose collector is connected to the output terminal and whose emitter is connected to a low potential power supply; and a second NPN transistor which is connected between the high potential power supply and the base of the first NPN transistor. at least one P-channel MO run shifter whose gate is supplied with an input signal; and at least one run shifter connected between the base of the first NPN transistor and the low potential side power supply and whose gate is supplied with the input signal. a first N-channel MOS transistor, the output terminal and the second NP
at least one second N-channel MOS transistor connected between the base of the NPN transistor and having its gate supplied with the input signal; and between the base of the second NPN transistor and the low potential side power supply. The buffer circuit is characterized in that the buffer circuit includes a capacitor having one end to which the input signal is input and the other end connected to the base of the second NPN transistor.

[Operations] According to the present invention, between the base of the second NPN transistor of the two NPN transistors in the output stage, which has conventionally had a problem of delay in operation, and the signal input terminal,
capacity is connected. Note: When the input signal changes from a high level to a low level, the capacitance can speed up the extraction of charge from the base of the second NPN transistor and speed up the second NPN transistor being turned off. . Also, when the input signal changes from low level to high level, the second N-channel MO
The speed of the bias voltage setting performed by the S transistor and the resistor can be increased by the capacitor, and the speed at which the second NPN transistor is turned on can be increased.

As a result, according to the present invention, during the switching operation of the NPN transistor in the output stage, the operating speeds of the two NPN transistors can be made equal, and a reverse voltage exceeding the base-emitter reverse breakdown voltage is prevented from being applied. can do.

[Embodiments] Hereinafter, embodiments of the present invention will be described based on the attached drawings.

FIG. 1 is a circuit diagram of a buffer circuit according to a first embodiment of the present invention.

The circuit of FIG. 1 differs from the conventional circuit shown in FIG. 5 in that a speed-up capacitor 7 is connected between the input terminal and the base of the second NPN transistor 2. Note that the other configurations are the same as the circuit shown in FIG. 5, so detailed explanation will be omitted.

Next, the operation of this circuit will be explained.

In a steady state where the input signal is at low level or high level, the circuit operates in the same way as a conventional circuit.

In a transient state where the input signal changes from a high level to a low level, the capacitor 7 speeds up the base extraction of the NPN transistor 2, so that the speed at which the NPN transistor 2 turns off can be increased.

On the other hand, in a transient state where the input signal changes from a low level to a high level, the bias of the NPN transistor 2 is
It is determined by the N-channel MOS transistor 5 and the resistor 6, but since a capacitor 7 is connected between the input terminal and the base of the NPN transistor 2, the speed of bias voltage setting can be increased by this capacitor 7. ,NP
The speed at which the N transistor 2 turns on can be increased.

FIG. 2 is a graph diagram for comparing the operation of the circuit of this embodiment and the conventional circuit shown in FIG.

As is clear from this figure, conventionally, when the input signal changes from low level to high level, the rise of the base voltage of the NPN transistor 2 is delayed;
The change in the output signal cannot keep up with the change in the base of the NPN transistor 1, and a large reverse voltage is applied between the base ψ emitter of the NPN transistor 1. On the other hand, in the circuit of the present embodiment, as a result of the speed at which the base voltage of the NPN transistor 2 rises, the change in the output signal can sufficiently follow the fall of the base voltage of the NPN transistor 2. Therefore, it is possible to prevent a reverse voltage exceeding the reverse breakdown voltage from being applied to the base/emitter of the NPN transistor 1.

FIG. 3 is a diagram showing a buffer circuit according to a second embodiment of the invention.

In this embodiment, the input stage of the first embodiment shown in FIG.
A CMOS inverter 10 consisting of an OS transistor 9 is provided. The other configurations are the same as the circuit shown in FIG.

According to this embodiment, a CMOS inverter 10 is used in the input stage.
, it becomes a non-inverting buffer circuit. Further, in this embodiment, by providing the CMOS inverter 10 at the input stage, there is an advantage that the speed-up capacitor 7 does not affect the driving ability of the circuit input to the buffer circuit.

FIG. 4 is a diagram showing a buffer circuit according to a third embodiment of the present invention.

In this embodiment, a NOR gate is used as the input stage gate for driving NPN transistors 1 and 2.

That is, P channel MOS transistors 3a and 3b are connected in series between the power supply terminal and the base of the NPN transistor 1. Furthermore, an N-channel MO3 transistor 4a+4b is connected in parallel between the base of the NPN transistor 1 and the ground terminal. Furthermore, N channel MOS transistors 5a and 5b are connected in parallel between the output terminal and the base of the NPN transistor 2. Furthermore, among these MOS transistors, the gates of transistors 3a+4b and 5b are commonly connected to input a first input signal, and the gates of transistors 3b+4a and 5a are commonly connected to input a second input signal. It looks like this. Capacitors 7a and 7b are connected between the base of the NPN transistor 2 and each input terminal, respectively.

Even in a buffer circuit having such a NOR gate function, the same effects as in the previous embodiment can be obtained.

[Effects of the Invention] As described above, according to the present invention, a capacitor is connected between the base of the second NPN transistor and the signal input terminal, so that the second NPN The rise speed of the base of the transistor can be increased, and the fall speed of the output level can also be increased. As a result, it is possible to prevent a reverse voltage exceeding the reverse breakdown voltage from being applied between the base and emitter of the first NPN transistor, and it is possible to provide a highly reliable buffer circuit.

[Brief Description of the Drawings] Fig. 1 is a circuit diagram of a buffer circuit according to a first embodiment of the present invention, Fig. 2 is a graph showing the operation of the same buffer circuit in comparison with a conventional example, and Fig. 3 4 is a circuit diagram of a buffer circuit according to a second embodiment of the present invention, FIG. 4 is a circuit diagram of a buffer circuit according to a third embodiment of the present invention, and FIG. 5 is a circuit diagram of a conventional buffer circuit. . L 2; NPN transistor, 3+ 3a, 3b. 8: P channel MOS transistor, 4 + 4 a
+4b, 5+ 5a+ 5b, 9; N channel M
OS transistor, 6; resistor, 7, 7 at 7 b
:Capacity, 10;CMOS inverter

Claims (1)

[Claims] (1) A first NPN transistor whose collector is connected to a high-potential power supply and an emitter connected to an output terminal; and a second NPN transistor whose collector is connected to the output terminal and whose emitter is connected to a low-potential power supply. at least one P-channel MOS transistor connected between the high potential power supply and the base of the first NPN transistor and having its gate supplied with an input signal; at least one first N-channel MOS transistor connected between a low potential side power supply and having its gate supplied with the input signal;
at least one second N-channel MOS transistor connected between the output terminal and the base of the second NPN transistor and having its gate supplied with the input signal; A buffer circuit having a resistor connected between a low potential side power supply and a capacitor having one end inputting the input signal and the other end connected to the base of the second NPN transistor. buffer circuit.