KR100489587B1 - Time delay circuit - Google Patents

Abstract

1. TECHNICAL FIELD OF THE INVENTION

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a time delay circuit, and to a time delay circuit that can easily control a delay time without increasing the size of a semiconductor device.

2. Technical problem to be solved by the invention

The purpose of the present invention is to prevent an increase in the size of the device generated when the delay time is changed by using the resistance value.

3. Summary of the Solution of the Invention

The delay time is controlled by adjusting the capacitance of a capacitor composed of MOS transistors.

4. Significant Uses of the Invention

Applicable to the time delay circuit design of semiconductor devices.

Description

Time delay circuit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a time delay circuit, and more particularly, to a time delay circuit that can easily adjust a delay time without increasing the size of a semiconductor device.

In general, a time delay circuit used in a semiconductor device is configured such that a delay time is determined by a resistance value and a capacitance. A conventional time delay circuit will be described with reference to FIG. 1 as follows.

First and second inverters I1 and I2 are connected in series between the input terminal IN and the first node K1, and third and fourth inverters between the first node K1 and the output terminal OUT. I3 and I4) are connected in series. A capacitor C composed of a MOS transistor is connected between the first node K1 and ground. In addition, first and second resistors R1 and R2 are connected in series between a power supply voltage Vcc and a power supply terminal of the second inverter I2, and a gate is provided between both terminals of the first resistor R1. The first transistor P1 connected to the first control signal S1 input terminal is connected in parallel, and the second transistor whose gate is connected to the second control signal S2 input terminal between both terminals of the second resistor R2. P2 is connected in parallel.

The time delay circuit configured as described above is configured such that a signal input through the input terminal IN is output after a predetermined time delay through the first to fourth inverters I1 to I4 and the output terminal OUT. In this case, the delay time is determined according to the states of the first and second control signals S1 and S2. For example, when the first and second control signals S1 and S2 are input to a high potential state, the first and second transistors P1 and P2 are turned off. Accordingly, the time delay is determined only by the resistance values of the first and second resistors R1 and R2. On the other hand, when the first and second control signals S1 and S2 are input in a low potential state, resistance components exist due to the turn-on of the first and second transistors P1 and P2. You will not.

However, in the conventional time delay circuit using the time delay according to the resistance value, the power supply voltage Vcc and the second inverter I2 even when the first and second transistors P1 and P2 are turned on. The channel resistance values of the first and second transistors P1 and P2 exist between the power supply terminals. Therefore, in order to further reduce the resistance between the power supply voltage Vcc and the power supply terminal of the second inverter I2, the channel widths of the first and second transistors P1 and P2 must be increased. Increasing the size of the device makes it difficult to integrate the device.

Accordingly, an object of the present invention is to provide a time delay circuit that can solve the above disadvantages by adjusting the capacitance of a capacitor composed of a MOS transistor.

The present invention for achieving the above object is the first and second inverters connected in series between the input terminal and the first node, the third and fourth inverters connected in series between the first node and the output terminal, the power supply voltage and A resistor connected between a power supply terminal of the second inverter, a capacitor connected between the first node and ground, first and second transistors configured to operate as a capacitor between the first node and the second node, and the first An output terminal is connected to two nodes and a fifth inverter receives a control signal through an input terminal. The first transistor is an NMOS transistor, and the second transistor is a PMOS transistor.

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

2 is a circuit diagram illustrating a time delay circuit according to the present invention;

First and second inverters I11 and I12 are connected in series between the input terminal IN and the first node K11, and third and fourth inverters between the first node K11 and the output terminal OUT. I13 and I14) are connected in series. A resistor R is connected between the power supply voltage Vcc and the power supply terminal of the second inverter I12, and a capacitor C composed of a MOS transistor is connected between the first node K11 and ground. In addition, the first and second transistors N and P configured to operate as a capacitor are connected in parallel between the first node K11 and the second node K12, and a control signal (C) to the second node K12. The fifth inverter I15, which receives S), is connected.

The time delay circuit configured as described above is configured such that a signal input through the input terminal IN is output after a predetermined time delay through the first to fourth inverters I11 to I14 and the output terminal OUT. The delay time is determined by the resistor R and the first and second transistors N and P. At this time, the capacitor C has a fixed capacitance, but when the control signal S is input at a low potential state, the second node K12 to which the gate of the first transistor N is connected is high. The first transistor N is turned on because of the potential. Therefore, the capacitance viewed from the first node K11 becomes the capacitance Cox by the gate oxide film of the first transistor N. FIG.

As a result, the second transistor P is operated when the potential of the first node K11 transitions from low to high, and the first transistor N is operated when the potential of the first node K11 transitions from high to low. .

On the other hand, when the control signal S is input to the high potential state, the potential of the second node K12 becomes low, so that the first and second transistors N and P are both cut-off. ) State. Therefore, at this time, the capacitance viewed from the first node K11 is a value obtained by synthesizing the capacitance Cox by the gate oxide film and the capacitance by the transistor process in series. Smaller than Cox). As a result, the capacitance of the first node K11 is reduced and the time delay caused by the first node K11 is reduced.

As described above, in the present invention, unlike the conventional time delay circuit which allows the delay time to be controlled by the resistance value, the delay time is controlled by adjusting the capacitance of the capacitor composed of the MOS transistor. Therefore, unlike the conventional method of adjusting the resistance value to obtain the desired delay time, only the capacitance of the capacitor needs to be controlled, thereby increasing the size of the device. In addition, by using the present invention, the delay time can be easily adjusted, and when the delay time set by the process or the like during the device manufacturing cannot be obtained, the delay time can be easily corrected.

1 is a circuit diagram for explaining a general time delay circuit.

2 is a circuit diagram for explaining a time delay circuit according to the present invention.

<Explanation of symbols for main parts of drawing>

I1 to I4: first to fourth inverters P1 and P2: first and second transistors

R1 and R2: first and second resistors C: capacitor

I11 to I15: first to fifth inverters R: resistance

N and P: first and second transistors

Claims (2)

In the time delay circuit, First and second inverters I11 and I12 connected in series between the input terminal and the first node, Third and fourth inverters I13 and I14 connected in series between the first node and the output terminal, A resistor (R) connected between a power supply voltage and a power supply terminal of the second inverter, A capacitor C connected between the first node and ground, First and second transistors (N, P) configured to operate as capacitors between the first and second nodes; And a fifth inverter (I15) having an output terminal connected to the second node and receiving a control signal through an input terminal. The method of claim 1, The first transistor is an NMOS transistor, and the second transistor is a PMOS transistor.

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