JPH02154461A - Output buffer of semiconductor integrated circuit - Google Patents
Output buffer of semiconductor integrated circuitInfo
- Publication number
- JPH02154461A JPH02154461A JP63308653A JP30865388A JPH02154461A JP H02154461 A JPH02154461 A JP H02154461A JP 63308653 A JP63308653 A JP 63308653A JP 30865388 A JP30865388 A JP 30865388A JP H02154461 A JPH02154461 A JP H02154461A
- Authority
- JP
- Japan
- Prior art keywords
- driver
- output
- pull
- well
- output buffer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 8
- 230000000694 effects Effects 0.000 abstract description 11
- 230000007704 transition Effects 0.000 abstract description 7
- 230000007423 decrease Effects 0.000 abstract description 6
- 238000010586 diagram Methods 0.000 description 7
- 239000000758 substrate Substances 0.000 description 5
- 238000004904 shortening Methods 0.000 description 2
- 230000007257 malfunction Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Electronic Switches (AREA)
- Logic Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は半導体集積回路に関し、特にその出力バッフ
ァに関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit, and particularly to its output buffer.
第７図は従来の出力バッファの回路図である。 FIG. 7 is a circuit diagram of a conventional output buffer.
図において、ＱｌはＮＭＯＳ型トランジスタのプルアッ
プドライバ、Ｑ２はＮＭＯＳ型トランジスタのプルダウ
ンドライバである。また１は出力端子、２ａ及び２ｂは
各々Ｑ１及びＱ２のゲート制御端子である。Ｑｌのドレ
イン３及びソース４は各々電源及び出力端子１に接続さ
れ、バックゲート５は接地されている。Ｑ２のドレイン
６は出力端子１に接続され、ソース７及びバックゲート
８は共に接地されている。In the figure, Ql is an NMOS transistor pull-up driver, and Q2 is an NMOS transistor pull-down driver. Further, 1 is an output terminal, and 2a and 2b are gate control terminals of Q1 and Q2, respectively. The drain 3 and source 4 of Ql are connected to the power supply and output terminal 1, respectively, and the back gate 5 is grounded. The drain 6 of Q2 is connected to the output terminal 1, and the source 7 and back gate 8 are both grounded.
第８図は第７図の従来の出力バッファの断面図を示し、
Ｑｌ、Ｑ２及び１〜８は第７図と同じ部分を示す。９は
Ｑｌ、Ｑ２が形成されるＰウェルであり、１０はＮ型基
板である。なお、この図ではＱｌ及びＱ２は同−Ｐウェ
ル９内に形成されているが、各々別個のＰウェルに形成
されていても差し支えない。FIG. 8 shows a cross-sectional view of the conventional output buffer of FIG.
Ql, Q2 and 1 to 8 indicate the same parts as in FIG. 9 is a P-well where Ql and Q2 are formed, and 10 is an N-type substrate. In this figure, Ql and Q2 are formed in the same P well 9, but they may be formed in separate P wells.
次に動作について説明する。出力ドライバＱ１及びＱ２
は各々ゲート制御端子２ａ及び２ｂの電位によってＯＮ
またはＯＦＦし、出力端子１の電位を変化させる。高電
位を出力する時は、２ａを高電位、２ｂを低電位にする
。逆に低電位を出力する時は、２ｂを高電位、２ａを低
電位にする。Next, the operation will be explained. Output drivers Q1 and Q2
are turned ON by the potentials of the gate control terminals 2a and 2b, respectively.
Alternatively, it is turned OFF and the potential of output terminal 1 is changed. When outputting a high potential, 2a is set to high potential and 2b is set to low potential. Conversely, when outputting a low potential, 2b is set to a high potential and 2a is set to a low potential.
また２ａ＊２ｂ共に低電位にすると、Ｑｌ、Ｑ２ともに
ＯＦＦし、出力は高インピーダンス状態となる。Further, when both 2a*2b are set to a low potential, both Ql and Q2 are turned off, and the output becomes a high impedance state.
出力電位ｌであるが、プルアップドライバ、プルダウン
ドライバ共にＮＭＯＳ型トランジスタを用いているため
、低電位側は接地電位まで下がるが、高電位側は電源電
位からＱｌのしきい値電圧（以下ＶＴＨＱＩと呼ぶ）だ
け低い電位までしか上昇しない。As for the output potential l, since both the pull-up driver and pull-down driver use NMOS type transistors, the low potential side drops to the ground potential, but the high potential side drops from the power supply potential to the threshold voltage of Ql (hereinafter referred to as VTHQI). The potential rises only to a lower potential than
このタイプの出力バッファは、従来ＮＭＯＳ型半導体集
積回路に用いられていたが、最近ではＣＭＯ８型半導体
集積回路装置にも用いられるようになってきた。すなわ
ち、０ＭＯ８型出カバ、ソファに比べ出力振幅が小さい
ため、出力変化時のノイズ発生量が小さくなり、ノイズ
に起因する誤動作を防止するのに効果がある。This type of output buffer has conventionally been used in NMOS type semiconductor integrated circuits, but recently it has also come to be used in CMO8 type semiconductor integrated circuit devices. That is, since the output amplitude is smaller than that of the 0MO8 type output cover and sofa, the amount of noise generated when the output changes is reduced, and it is effective in preventing malfunctions caused by noise.
しかし出力高電位が下がると、電源電圧が低くなった場
合に逆に充分な出力振幅を確保できなくなる可能性があ
る。先に示した従来例では、プルアップドライバＱ１の
バックゲート５が接地されているため、出力電位が上昇
していくとＱｌにバックゲート効果が生じて以下ＶＴＨ
ＱＩが増大する。However, if the output high potential decreases, there is a possibility that a sufficient output amplitude cannot be secured when the power supply voltage decreases. In the conventional example shown above, the back gate 5 of the pull-up driver Q1 is grounded, so as the output potential increases, a back gate effect occurs on Ql, and below VTH
QI increases.
ＶＴＨＱＩの値は、バックゲート効果が生じると、約０
．７ｖから約１．５ｖへ増大するので１．電源電圧が４
．５ｖのとき、出力高電位は３．Ｏｖまでしか上昇しな
い。かつ、その時Ｑ１のインピーダンスは非常に大きく
なるので、数ｍＡの電流が流れるバイポーラトランジス
タのベースを駆動する場合は、さらに出力高電位は低下
する。The value of VTHQI becomes approximately 0 when the backgate effect occurs.
．． 1. Since it increases from 7v to about 1.5v. Power supply voltage is 4
．． At 5V, the output high potential is 3. It only rises to Ov. In addition, since the impedance of Q1 becomes very large at that time, when driving the base of a bipolar transistor through which a current of several milliamperes flows, the output high potential further decreases.
さらには、バックゲート効果により出力電位が上昇する
際、Ｑｌのドライブ能力は急激に減少し出力遷移時間が
長くなってしまう。Furthermore, when the output potential rises due to the back gate effect, the drive ability of Ql decreases rapidly, resulting in a longer output transition time.
従来の半導体集積回路の出力バッファは以上のように構
成されているので、出力高電位が下がり過ぎて充分な出
力振幅が得られない、また出力遷移時間が長くなると言
った問題点があった。Since the output buffer of a conventional semiconductor integrated circuit is constructed as described above, there are problems in that the output high potential drops too much, making it impossible to obtain a sufficient output amplitude, and that the output transition time becomes long.
この発明は上記のような問題点を解消するためになされ
たもので、充分な出力振幅を確保できる、ＮＭＯＳ型ト
ランジスタのプルアップドライバを用いた出力バッファ
で、しかも出力遷移時間を短縮で〆きる出力バッファを
得ることを目的とする。This invention was made to solve the above-mentioned problems, and it is an output buffer using an NMOS transistor pull-up driver that can ensure sufficient output amplitude, and can shorten the output transition time. The purpose is to obtain an output buffer.
また、さらにこの発明は、充分な出力振幅を確保でき、
しかも出力端子の容阜増大を抑制アきる出カッ１くソフ
ァを得ることを目的とする。Furthermore, this invention can ensure sufficient output amplitude,
Moreover, it is an object of the present invention to obtain a sofa with a high output that can suppress the increase in the size of the output terminal.
本発明に係る出力バッファは、プルアップドライバ用Ｎ
ＭＯＳ型トランジスタが形成されるＰウェルを他のＰウ
ェルと分離し、そのバックゲートすなわちＰウェルをそ
のソースすなわち出力端子に接続したものである。The output buffer according to the present invention has N
A P-well in which a MOS type transistor is formed is separated from other P-wells, and its back gate, that is, the P-well, is connected to its source, that is, its output terminal.
また本発明に係る出力バッファは、他のＰウェルから分
離されたＰウェルよに形成され、ドレインが電源に、ソ
ースとバックゲート（Ｐウェル）が出力端子に各々接続
されたＮＭＯＳ型トランジスタを補助用プルアップドラ
イバとして挿入し、その寸法及びＰウェル面積を本来の
プルアップドライバのそれ社より小さく、たとえば必要
最小限に抑えたものである。Further, the output buffer according to the present invention is formed in a P well separated from other P wells, and supports an NMOS transistor whose drain is connected to a power supply and whose source and back gate (P well) are connected to an output terminal. The pull-up driver is inserted as a pull-up driver, and its dimensions and P-well area are smaller than those of the original pull-up driver, for example, to the necessary minimum.
本発明における出力バッファでは、プルアップドライバ
用ＮＭＯＳ型トランジスタにバックゲート効果が生じな
いため、出力電位が上昇する際にもＶＴＨＱＩは増大し
ないので、充分な出力高電位を発生でき、かつドライブ
能力の低下も小さくなる。In the output buffer of the present invention, since no back gate effect occurs in the NMOS type transistor for the pull-up driver, VTHQI does not increase even when the output potential increases, so a sufficiently high output potential can be generated and the drive capability can be improved. The drop will also be smaller.
また本発明における出力バッファでは、上記と同じ理由
によって充分な出力高電位を発生でき、かつ補助用プル
アップドライバのＰウェル−Ｎ基板間の容量による出力
端子の容量増大を抑えることができる。Further, the output buffer of the present invention can generate a sufficiently high output potential for the same reason as described above, and can suppress an increase in the capacitance of the output terminal due to the capacitance between the P well and the N substrate of the auxiliary pull-up driver.
以下この発明の第１の実施例を図について説明する。 A first embodiment of the present invention will be described below with reference to the drawings.
第１図において、Ｑｌ、Ｑ２．１〜４及び６〜８は第７
図に示す従来例と同じである。５ａはＱｌのバックゲー
トであり、Ｑｌのソース４すなわち出力端子１に接続さ
れている。第２図において９ａはＱｌが形成されるＰウ
ェルであり、他の回路のＰウェル９から分離されている
。In Figure 1, Ql, Q2.1-4 and 6-8 are the 7th
This is the same as the conventional example shown in the figure. 5a is a back gate of Ql, which is connected to the source 4 of Ql, that is, the output terminal 1. In FIG. 2, 9a is a P well in which Ql is formed, and is separated from P wells 9 of other circuits.
このようにＱｌのバックゲー）５ａは、出力端子１に接
続され、かつ電気的に他のＰウェル９と絶縁されている
ため、その電位は出力電位に追従する。したがって、バ
ックゲート５ａとソース４との間に電位差が生じず、Ｑ
ｌにはバックゲート効果によるＶＴＨＱＩの増大が生じ
ない。In this way, the Ql backgate 5a is connected to the output terminal 1 and electrically insulated from the other P well 9, so its potential follows the output potential. Therefore, no potential difference occurs between the back gate 5a and the source 4, and Q
VTHQI does not increase due to the back gate effect.
第３図は、第１図の実施例によるプルアップドライバと
第７図の従来のプルアップドライバのドレイン電流特性
を示す。比較のために、同一プロセスで形成しトランジ
スタサイズも同じとする。FIG. 3 shows drain current characteristics of the pull-up driver according to the embodiment shown in FIG. 1 and the conventional pull-up driver shown in FIG. For comparison, assume that they are formed using the same process and have the same transistor size.
従来は出力電位はＢ点までしか上昇しないが、本発明に
よるとＡ点まで上昇するので、その差は約０．８■あり
、充分な出力振幅を得ることができる。また、出力電位
が」１弄するとバックゲート効果の有無の違いによって
ドレイン電流も従来より増大している。すなわち駆動能
力が増大し出力が低電位から高電位に変化する時の遷移
時間も短縮できる。出力遷移時間の短縮は、高速動作を
必要とする半導体集積回路、たとえばスタティックＲＡ
Ｍ等にを効である。Conventionally, the output potential rises only to point B, but according to the present invention, it rises to point A, so the difference is about 0.8 square meters, and a sufficient output amplitude can be obtained. Furthermore, when the output potential is increased by 1, the drain current also increases compared to the conventional case due to the presence or absence of the back gate effect. That is, the driving capability is increased and the transition time when the output changes from a low potential to a high potential can also be shortened. Shortening the output transition time is useful for semiconductor integrated circuits that require high-speed operation, such as static RA.
It is effective for M etc.
以下この発明の第２の実施例を図について説明する。A second embodiment of the invention will be described below with reference to the drawings.
第４図において、Ｑｌ、Ｑ２及び１〜８は第７図に示す
従来例と同じである。Ｑ３は付加されるＮＭＯＳ型Ｏ８
型補助アップドライバである。Ｑ３のドレイン１１は電
源に、ソース１２及びバックゲート１３は出力端子１に
各々接続される。２ＣはＱ３のゲート制御端子である。In FIG. 4, Ql, Q2, and 1 to 8 are the same as in the conventional example shown in FIG. Q3 is added NMOS type O8
It is a type assisted up driver. The drain 11 of Q3 is connected to the power supply, and the source 12 and back gate 13 are connected to the output terminal 1. 2C is a gate control terminal of Q3.
２ｃはＱｌのゲート制御端子２ａへの信号と同信号であ
っても別信号であってもよい。第５図において９ｂはＱ
３が形成されるＰウェルであり、他の回路のＰウェルか
ら分離されている。2c may be the same signal as the signal to the gate control terminal 2a of Ql, or may be a different signal. In Figure 5, 9b is Q
3 is a P-well formed and is separated from the P-wells of other circuits.
補助用プルアップドライバＱ３はこのように形成されて
いるので、本発明の第１の実施例を示す第１図における
プルアップドライバＱ１と同様の特性を示す。さて、第
１図のように本来のプルアップドライバＱ１のバックゲ
ー）５ａを出力端子１に接続すると第２図から明らかな
ようにＰウェル９ａとＮ基板１０との間のジャンクショ
ン容ｆｉが出力容量に追加される。したがって出力容量
に厳しい制限があるときは、この追加される容量が問題
となり、Ｐウェル９ａの面積を小さくする必要性がでて
くるが、このようにするとドライブ能力が低下する。Since the auxiliary pull-up driver Q3 is formed in this manner, it exhibits the same characteristics as the pull-up driver Q1 in FIG. 1 showing the first embodiment of the present invention. Now, as shown in Fig. 1, when the back gate 5a of the original pull-up driver Q1 is connected to the output terminal 1, as is clear from Fig. 2, the junction capacitance fi between the P well 9a and the N substrate 10 becomes the output capacitance. will be added to. Therefore, when there is a severe limit on the output capacitance, this added capacitance becomes a problem, and it becomes necessary to reduce the area of the P-well 9a, but this reduces the drive capability.
そこで第４図に示すように、主たるプルアップドライバ
は、従来タイプのプルアップドライバＱ１を用い、バッ
クゲート１３が出力端子１に接続されるＮＭＯＳ）ラン
ジスタＱ３を補助用プルアップドライバとして用いるこ
とが考えられる。このドライバＱ３のトランジスタサイ
ズは、出力高電位を確保できる必要最小限に抑える。こ
れに伴イ該ドライバＱ３が形成されるＰウェル９ｂの面
積も必要最小限に抑えて出力容量の増大を抑える。Therefore, as shown in FIG. 4, it is possible to use a conventional type pull-up driver Q1 as the main pull-up driver, and use an NMOS transistor Q3 whose back gate 13 is connected to the output terminal 1 as an auxiliary pull-up driver. Conceivable. The transistor size of this driver Q3 is kept to the minimum necessary to ensure a high output potential. Accordingly, the area of the P well 9b in which the driver Q3 is formed is also minimized to suppress an increase in output capacitance.
第６図に第４図の実施例による補助用プルアップドライ
バＱ３と、第７図の従来のプルアップドライバＱ１のド
レイン電流特性を示す。本第２実施例の補助用プルアッ
プドライバＱ３はトランジスタサイズが小さいため、ド
レイン電流は小さく駆動能力は小さいが、出力高電位は
Ａ点まで上昇するので、たとえ数ｍＡの引き抜き電流が
あっても、従来タイプより高電位を確保することは容易
である。たとえば、引き抜き電流が４ｍＡとすると、補
助用プルアップドライバＱ３のトランジスタ幅は５０μ
ｍもあれば出力電位の低下を峡ｏ。FIG. 6 shows the drain current characteristics of the auxiliary pull-up driver Q3 according to the embodiment shown in FIG. 4 and the conventional pull-up driver Q1 shown in FIG. Since the auxiliary pull-up driver Q3 of the second embodiment has a small transistor size, the drain current is small and the drive capability is small, but the output high potential rises to point A, so even if there is a pull-out current of several mA. , it is easier to secure a higher potential than the conventional type. For example, if the pull-out current is 4mA, the transistor width of the auxiliary pull-up driver Q3 is 50μ.
If there is m, the output potential will decrease.
５■以内に抑えることができ、従来の出力高電位Ｂ点よ
りも高くできる。この時Ｐウェル９ｂの面積は約１００
０μｍ２であり、Ｐウェル９ｂとＮ基板１０とのジャン
クション容量は約０． １ｐＦとなり、全く問題ない。It can be suppressed to within 5■, and can be higher than the conventional output high potential point B. At this time, the area of P well 9b is approximately 100
0 μm2, and the junction capacitance between the P well 9b and the N substrate 10 is approximately 0.0 μm2. It becomes 1 pF, which is no problem at all.
以上のように、この発明によれば、ＮＭＯＳ型トランジ
スタからなるプルアップドライバのＰウェルを他のＰウ
ェルから分離してバックゲートをソースに接続するよう
にしたので、充分な出力高電位を発生でき、かつ出力遷
移時間を短縮できる効果がある。As described above, according to the present invention, the P-well of the pull-up driver made of NMOS transistors is separated from other P-wells and the back gate is connected to the source, so that a sufficiently high output potential is generated. This has the effect of shortening the output transition time.
またこの発明によれば、独立したＰウェル上に形成され
、バックゲートがソースに接続されたＮＭＯＳ型トラン
ジスタからなる補助用プルアップドライバを付加するよ
うにしたので、充分な出力高電位を発生でき、かつ出力
容量の増加を抑えられる効果がある。Furthermore, according to the present invention, an auxiliary pull-up driver formed on an independent P-well and consisting of an NMOS transistor whose back gate is connected to the source is added, making it possible to generate a sufficiently high output potential. , and has the effect of suppressing an increase in output capacitance.
第１図はこの発明の第１の実施側番こよる出力バッファ
を示す回路図、第２図はこの発明の第１の実施例による
出力バッファを示す断面図、第３図はこの発明の第１の
実施例による出力バッファを示すドレイン電流特性図、
第４図はこの発明の第２の実施例による出力バッファを
示す回路図、第５図はこの発明の第２の実施例による出
力バッファを示す断面図、第６図はこの発明の第２の実
施例による出力バッファを示すドレイン電流特性図、第
７図は従来の出力バッファを示す回路図、第８図は従来
の出力バッファを示す断面図である。
図において、ＱｌはＮＭＯＳ型トランジスタからなるプ
ルアップドライバ、Ｑ２はＮＭＯＳ型トランジスタから
なるプルダウンドライバ、Ｑ３はＮＭＯＳ型トランジス
タからなる補助用プルアップドライバ、１は出力端子、
２ａはプルアップドライバＱ１のゲート制御信号、２ｂ
はプルダウンドライバＱ２のゲート制御信号、２ｃは補
助用プルアップドライバＱ３のゲート制御信号、３はＱ
ｌのドレイン、４はＱｌのソース、５，５ａはＱｌのバ
ックゲート、６はＱ２のドレイン、７はＱ２のソース、
８はＱ２のバックゲート、９はＰウェル、９ａはＱｌが
形成されるＰウェル、９ｂはＱ３が形成されるＰウェル
、１０はＮ基板、１１はＱ３のドレイン、１２はＱ３の
ソース、１３はＱ３のバックゲートである。
＝１２−
なお図中同一符号は同−又は相当部分を示す。FIG. 1 is a circuit diagram showing an output buffer according to a first embodiment of the invention, FIG. 2 is a sectional view showing an output buffer according to a first embodiment of the invention, and FIG. A drain current characteristic diagram showing the output buffer according to the first embodiment,
FIG. 4 is a circuit diagram showing an output buffer according to a second embodiment of the invention, FIG. 5 is a sectional view showing an output buffer according to a second embodiment of the invention, and FIG. 6 is a circuit diagram showing an output buffer according to a second embodiment of the invention. A drain current characteristic diagram showing the output buffer according to the embodiment, FIG. 7 is a circuit diagram showing a conventional output buffer, and FIG. 8 is a sectional view showing the conventional output buffer. In the figure, Ql is a pull-up driver made of an NMOS transistor, Q2 is a pull-down driver made of an NMOS transistor, Q3 is an auxiliary pull-up driver made of an NMOS transistor, 1 is an output terminal,
2a is the gate control signal of the pull-up driver Q1, 2b
is the gate control signal of pull-down driver Q2, 2c is the gate control signal of auxiliary pull-up driver Q3, and 3 is Q
1 is the drain of 1, 4 is the source of Q1, 5, 5a is the back gate of Q1, 6 is the drain of Q2, 7 is the source of Q2,
8 is the back gate of Q2, 9 is the P well, 9a is the P well where Ql is formed, 9b is the P well where Q3 is formed, 10 is the N substrate, 11 is the drain of Q3, 12 is the source of Q3, 13 is the back gate of Q3. =12- Note that the same reference numerals in the figures indicate the same or corresponding parts.
Claims (2)
ドレインが電源にソースが出力端子に各々接続されるプ
ルアップドライバを有する出力バッファにおいて、 上記プルアップドライバのＰウェルが他の回路のＰウェ
ルから分離され、上記ソースに接続されてなることを特
徴とする半導体集積回路の出力バッファ。(1) Consisting of an NMOS type transistor on a P well,
An output buffer having a pull-up driver whose drain is connected to a power supply and whose source is connected to an output terminal, characterized in that the P-well of the pull-up driver is separated from the P-wells of other circuits and connected to the source. Output buffer for semiconductor integrated circuits.
ライバを有する出力バッファにおいて、Ｐウェル上のＮ
ＭＯＳ型トランジスタからなり、ドレインが電源にソー
スが出力端子に各々接続され、かつ上記Ｐウェルが他の
回路のＰウェルから分離され上記ソースに接続された補
助用プルアップドライバが付加されてなり、 該補助用プルアップドライバのサイズ及び 該補助用プルアップドライバが形成されるＰウェルの面
積は、上記プルアップドライバに比べ小さいことを特徴
とする半導体集積回路の出力バッファ。(2) In an output buffer with a pull-up driver consisting of an NMOS transistor, the N
It consists of a MOS type transistor, the drain is connected to the power supply, and the source is connected to the output terminal, and an auxiliary pull-up driver is added in which the P-well is separated from the P-well of other circuits and connected to the source, An output buffer for a semiconductor integrated circuit, wherein the size of the auxiliary pull-up driver and the area of the P-well in which the auxiliary pull-up driver is formed are smaller than those of the pull-up driver.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63308653A JPH02154461A (en) | 1988-12-06 | 1988-12-06 | Output buffer of semiconductor integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63308653A JPH02154461A (en) | 1988-12-06 | 1988-12-06 | Output buffer of semiconductor integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02154461A true JPH02154461A (en) | 1990-06-13 |
Family
ID=17983665
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63308653A Pending JPH02154461A (en) | 1988-12-06 | 1988-12-06 | Output buffer of semiconductor integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02154461A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04113670A (en) * | 1990-09-03 | 1992-04-15 | Nec Ic Microcomput Syst Ltd | Semiconductor integrated circuit |
| JPH04345317A (en) * | 1991-04-08 | 1992-12-01 | Internatl Business Mach Corp <Ibm> | Driver circuit, low noise driver circuit and low noise low vibration driver-receiver circuit |
| EP0533339A2 (en) * | 1991-09-16 | 1993-03-24 | Advanced Micro Devices, Inc. | CMOS output buffer circuits |
| JP2010003925A (en) * | 2008-06-20 | 2010-01-07 | Toppan Printing Co Ltd | Semiconductor device |
| JP2015177579A (en) * | 2014-03-13 | 2015-10-05 | 富士電機株式会社 | Drive circuit for insulated gate type device |
| JP2017162539A (en) * | 2011-08-24 | 2017-09-14 | 株式会社半導体エネルギー研究所 | Semiconductor device and manufacture method therefor |
-
1988
- 1988-12-06 JP JP63308653A patent/JPH02154461A/en active Pending
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04113670A (en) * | 1990-09-03 | 1992-04-15 | Nec Ic Microcomput Syst Ltd | Semiconductor integrated circuit |
| JPH04345317A (en) * | 1991-04-08 | 1992-12-01 | Internatl Business Mach Corp <Ibm> | Driver circuit, low noise driver circuit and low noise low vibration driver-receiver circuit |
| EP0533339A2 (en) * | 1991-09-16 | 1993-03-24 | Advanced Micro Devices, Inc. | CMOS output buffer circuits |
| EP0533339A3 (en) * | 1991-09-16 | 1995-02-08 | Advanced Micro Devices Inc | |
| JP2010003925A (en) * | 2008-06-20 | 2010-01-07 | Toppan Printing Co Ltd | Semiconductor device |
| JP2017162539A (en) * | 2011-08-24 | 2017-09-14 | 株式会社半導体エネルギー研究所 | Semiconductor device and manufacture method therefor |
| JP2015177579A (en) * | 2014-03-13 | 2015-10-05 | 富士電機株式会社 | Drive circuit for insulated gate type device |
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