JPH06268457A - Operational amplifier circuit - Google Patents

Abstract

PURPOSE:To improve the PSRR characteristics of a bootstrap type erational amplifier circuit basically constituted of MOSFET. CONSTITUTION:This bootstrat type operational amplifier circuit is provided with an FETP1 for connecting a power supply voltage VDD and the source of differential MOSFETP2 and P3, an FETN4 provided between an output terminal Vout and a grounded potential VSS, the FETP4 for connecting the power supply voltage VDD and the output terminal Vout, a resistor R2 for connecting a bias voltage supply point VB1 and the gate of the FETP4 and a capacitance C2 for connecting the gate of the FETP4 and the gate of the FETN4. The gate of the FETP1 is connected to a bias voltage VB1 and ground VSS respectively by the resistor R1 and the capacitance C1. Thus, the values of the resistor R1 and the capacitance C1 are designed so as to mutually offset the fluctuation of output signals Vout due to that potential fluctuation between the power supply voltage VDD and the bias voltage VB1 is transmitted through them to the MOSFETP1 and the fluctuation due to that the potential fluctuation is transmitted through the resistor R2 and the capacitance C2 to the gate of the MOSFETP4.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an operational amplifier circuit, for example, a MOSFET (metal oxide semiconductor field effect transistor. In this specification, MOSFET is a generic term for an insulated gate field effect transistor). The present invention relates to a technique which is particularly effective when used in a bootstrap type operational amplifier circuit as a basic configuration.

[0002]

2. Description of the Related Art As illustrated in FIG. 6, a differential amplifier circuit centered on P-channel type differential MOSFETs P2 and P3 which receive a non-inverted input signal VinP and an inverted input signal VinN at their gates, respectively, and a circuit. Output terminal V
out and the ground potential VSS, the gate of which is the non-inverted output signal of the differential amplifier circuit, that is, the MOSFET.
N-channel type output MO that receives the drain potential of P3
SFET N4 and power supply voltage VDD and the above output MOS
A predetermined bias voltage VB1 is provided to the gate of the drain of the FET N4, that is, the output terminal Vout of the circuit.
P-channel M that acts as a constant current source by receiving
Output circuit composed of OSFETP4 and output terminal V of the circuit
out and the gate of the output MOSFET N4, the capacitor C3 and the N-channel MOSF are provided in series.
There is an operational amplifier circuit including a phase compensation circuit made of ETN3. Further, there is a so-called bootstrap type operational amplifier circuit in which a feedback capacitance C2 is provided between the gate of the MOSFET P4 which is a constant current source of such an operational amplifier circuit and the gate of the output MOSFET N4.

Regarding an operational amplifier circuit having a MOSFET as a basic structure and including a phase compensation circuit, for example, in 1982,
Published in February, "I-E-E-Journal of Solid State Circuits (IEEE Jou
rnal of Solid-State Circu
its) Vol. SC17 No. 6 ”, pages 969 to 982, and the like.

[0004]

However, as the performance of the operational amplifier circuit and the communication system including the same has been improved, the conventional bootstrap type operational amplifier circuit as described above has the following problems. It has been clarified by the inventors of the present application that points are generated. That is, in the bootstrap-type operational amplifier circuit, the feedback capacitance C2 for the MOSFET P1 which is the constant current source of the differential amplifier circuit.
A resistor R2 is provided to suppress the influence of the above, and a so-called smoothing capacitor C4 is provided to absorb the high frequency noise superimposed on the bias voltage VB1. However, when viewed from the bias voltage supply point VB1, the resistance R2 and the capacitance C2
Acts as a low-pass filter, so to speak, the power supply voltage VD
Only the relatively gradual potential change generated between D and the bias voltage VB1 is transmitted to the gate of the MOSFET P4.
Therefore, a potential difference occurs between the gate voltages of the two MOSFETs P1 and P4, which are constant current sources, and the power supply voltage VDD and the bias voltage VB1 are added to the output signal Vout of the operational amplifier circuit.
A level change occurs due to a potential change between the two. As a result, PSRR (Power Su) as an operational amplifier circuit
The characteristics of "ply rejection ratio (voltage fluctuation elimination ratio)" are deteriorated, and performance improvement of a communication system including an operational amplifier circuit is restricted.

An object of the present invention is to improve the PSRR characteristics of a bootstrap type operational amplifier circuit and promote high performance of a communication system including the operational amplifier circuit.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0007]

The outline of the representative one of the inventions disclosed in the present application will be briefly described as follows. That is, the P-channel type first and second P-channel type MOSFETs in the differential form, and the P-channel type MOSFET provided between the first power supply voltage and the commonly connected sources of the first and second MOSFETs. Third MOS of
An FET, an N-channel type fourth MOSFET provided between the output terminal of the circuit and the second power supply voltage, and having its gate receiving the drain potential of the second MOSFET;
P provided between the first power supply voltage and the output terminal of the circuit
The fifth channel-type MOSFET, a bias voltage supply point to which a predetermined bias voltage is supplied, and the fifth MO described above.
A second resistor provided between the gate of the SFET, the gate of the fifth MOSFET and the fourth MOSFET.
A bootstrap type operational amplifier circuit including a second capacitor provided between the gate of T and a first resistor provided between the bias voltage supply point and the gate of the third MOSFET, A first capacitance provided between the gate of the third MOSFET and the second power supply voltage is added, and the resistance value of the first resistor and the capacitance value of the first capacitance are set to the first capacitance. The potential fluctuation between the power supply voltage and the bias voltage is changed to the third M via the first resistance and the first capacitance.
Level fluctuation of the output signal of the circuit that is transmitted to the gate of the OSFET and level fluctuation of the output signal that is transmitted to the gate of the fifth MOSFET through the second resistor and the second capacitor Design so that and are offset.

[0008]

According to the above means, the level fluctuation of the output signal of the circuit due to the potential fluctuation between the first power supply voltage and the bias voltage can be canceled and its absolute value can be reduced. As a result, the PSRR characteristic of the operational amplifier circuit is improved,
It is possible to promote high performance of a communication system including an operational amplifier circuit.

[0009]

1 is a circuit diagram of a first embodiment of an operational amplifier circuit to which the present invention is applied. The configuration and operation of the operational amplifier circuit according to this embodiment and its features will be described with reference to FIG. The operational amplifier circuit of this embodiment is included in the communication integrated circuit that constitutes the terminal device of the mobile communication system. Each circuit element of FIG. 1 is formed on one semiconductor substrate such as single crystal silicon together with other circuit elements (not shown) of a communication integrated circuit. In the following circuit diagrams, the MOSFET with an arrow attached to its channel (back gate) portion is a P-channel type MOSFET, and is shown separately from the N-channel MOSFET without an arrow.

In FIG. 1, the operational amplifier circuit of this embodiment is a pair of P channel type (first conductivity type) differential MOS transistors.
FETs P2 (first MOSFET) and P3 (second M)
OSFET). The drains of these MOSFETs are a pair of N-channel (second conductivity type) load MOSs.
It is coupled to the ground potential VSS (second power supply voltage) through the FETs N1 and N2, and its commonly coupled source is P
It is coupled to the power supply voltage VDD (first power supply voltage) through the channel MOSFET P1 (third MOSFET). The gate of the MOSFET P2 is supplied with the non-inverted input signal VinP from a pre-stage circuit (not shown) of the communication integrated circuit, and the gate of the MOSFET P3 is supplied with the inverted input signal Vn.
inN is supplied. The gate of the MOSFET P1 is coupled to the bias voltage supply point VB1 (first bias voltage supply point) via the resistor R1 (first resistance), and M
The gate of OSFET N1 is commonly coupled to its drain and then to the gate of MOSFET N2. The power supply voltage VDD is a positive power supply voltage such as + 3V, and the bias voltage V at the bias voltage supply point VB1
B1 is a positive constant voltage whose absolute value is smaller than the power supply voltage VDD.

As a result, the MOSFETs N1 and N2 are in the current mirror form, and the differential MOSFETs P1 and P2 are formed.
Acts as an active load for. Also, MOS
The FET P1 acts as a constant current source that gives a predetermined operating current according to the bias voltage VB1 to the differential MOSFETs P2 and P3, and the differential MOSFETs P2 and P3.
Operates as one differential amplifier circuit which receives a differential input signal, that is, a non-inverted input signal VinP and an inverted input signal VinN together with these MOSFETs P1 and N1 and N2. As a result, the potential at the non-inverting output node of the differential amplifier circuit, that is, the drain of the MOSFET P3 is
It is made higher when the non-inverting input signal VinP has a higher potential than the inverting input signal VinN, and conversely, the non-inverting input signal Vi.
It is lowered when nP is set to a potential lower than the inverted input signal VinN.

Non-inverted output signal of the differential amplifier circuit centered on the differential MOSFETs P2 and P3, that is, MOSFETP.
The drain potential of 3 is N-channel MOSFET N4
It is supplied to the gate of the (fourth MOSFET). This M
The source of OSFET N4 is coupled to ground potential VSS,
Its drain is coupled to the output terminal Vout of the circuit.
Between the output terminal Vout of the circuit and the power supply voltage VDD,
P-channel MOSFET P4 (fifth MOSFET)
Is provided, and its gate is coupled to the bias voltage supply point VB1 via a resistor R2 (second resistor).

As a result, the MOSFET P4 is
The MOSFET acts as a constant current source that gives a predetermined operating current to the FET N4 according to the bias voltage VB1.
N4 acts as an output MOSFET that inverts and transmits the non-inverted output signal of the differential amplifier circuit centered on the MOSFETs P2 and P3 to the output terminal Vout of the circuit. That is, when the potential of the non-inverted output signal of the differential amplifier circuit is increased, the conductance of the output MOSFET N4 is increased, which lowers the potential of the output signal Vout at the output terminal Vout of the circuit. On the other hand, when the potential of the non-inverted output signal of the differential amplifier circuit is lowered, the output MO
The conductance of the SFET N4 is reduced, which increases the potential of the output signal Vout.

Output terminal Vout of the circuit and output MOSFE
N-channel MOSFET is connected between the gate of TN4
N3 (sixth MOSFET) and capacitor C3 (third capacitor) are provided in series. Of these, MOSFET
The gate of N3 is coupled to the bias voltage supply point VB2 (second bias voltage supply point) and receives a bias voltage VB2 of a positive potential whose absolute value is smaller than that of the bias voltage VB1. As a result, the MOSFET N3 acts as a substantial resistance element and constitutes a phase compensation circuit in the high frequency region together with the capacitance C3.

The operational amplifier circuit of this embodiment further includes a capacitance C4 provided between the power supply voltage VDD and the bias voltage supply point VB1, a gate of the MOSFET P4 and an output MO.
The capacitor C2 (second capacitor) provided between the gate of the SFET N4 is included. Among them, the capacitor C4 is a so-called smoothing capacitor, and acts to absorb the high frequency noise superimposed on the bias voltage VB1. The capacitance C2 is
The gate potential of the output MOSFET N4 is set to MOSFETP4
Of the so-called bootstrap type, which acts as a feedback capacitance, and the resistor R2 acts to suppress the influence of the feedback capacitance C2 on the MOSFET P1 which is a constant current source.

By the way, the resistor R2 and the capacitor C2 also act as a low-pass filter when viewed from the bias voltage supply point VB1, and determine only a relatively gradual potential fluctuation generated between the bias voltage VB1 and the power supply voltage VDD. It is transmitted to the gate of the MOSFET P4 serving as a current source. For this reason,
In the operational amplifier circuit of this embodiment, a capacitance C1 (first capacitance) is provided between the MOSFET P1 and the ground potential VSS, and the capacitance C2 and the resistor R2 are formed by a low pass filter including the capacitance C1 and the resistor R1. A method of canceling the influence of the low-pass filter is adopted.

That is, only the gradual potential fluctuation generated between the bias voltage VB1 and the power supply voltage VDD is caused by the resistance R2.
And MOSFET P4 serving as a constant current source via the capacitor C2
Is transmitted to the output MOSF from the MOSFET P4.
Although the value of the operating current supplied to ETN4 varies, the value of this operating current becomes smaller when the potential of the bias voltage VB1 is increased and the potential difference from the power supply voltage VDD is reduced, which causes the output of the operational amplifier circuit. The potential of the signal Vout is lowered. Further, when the potential of the bias voltage VB1 is lowered and the potential difference from the power supply voltage VDD is increased, the voltage is increased, which causes the output signal Vou of the operational amplifier circuit.
The potential of t is increased.

On the other hand, the capacitor C1 and the resistor R1 form another low-pass filter when viewed from the bias voltage supply point VB1, and only a relatively gentle potential fluctuation generated between the bias voltage VB1 and the power supply voltage VDD. It is transmitted to the gate of the MOSFET P1 serving as a constant current source. At this time, MO
The value of the operating current supplied from the SFET P1 to the differential MOSFETs P2 and P3 becomes smaller when the potential of the bias voltage VB1 is lowered and the potential difference from the power supply voltage VDD is made smaller, and the differential current centered on the differential MOSFETs P2 and P3. Non-inverting output node of amplifier circuit, that is, MOSFETP
3 acts to lower the potential at the drain. As a result, the conductance of the output MOSFET N4 is reduced and the potential of the output signal Vout of the operational amplifier circuit is increased. In addition, from the MOSFET P1 to the differential MOSFET P
The value of the operating current supplied to 2 and P3 increases when the potential of the bias voltage VB1 is lowered and the potential difference from the power supply voltage VDD is increased, and the value of the operating current of the differential amplifier circuit centered on the differential MOSFETs P2 and P3 increases. It acts to increase the potential at the inverting output node, ie, the drain of MOSFET P3. As a result, the conductance of the output MOSFET N4 conversely increases, and the output signal V of the operational amplifier circuit is increased.
The potential of out is lowered.

That is, the bias voltage VB1 and the power supply voltage V
The level fluctuation of the output signal Vout of the operational amplifier circuit accompanying the gentle potential fluctuation generated between the MOSFET and the DD is transmitted to the MOSFET P4 via the resistor R2 and the capacitor C2, and to the MOSFET P1 via the resistor R1 and the capacitor C1. The output signal Vo of the operational amplifier circuit accompanying the transmission
The level fluctuation of ut has a relationship in which the phases thereof are opposite to each other and cancel each other out. In this embodiment, the resistance R
1 and the capacitor C1 and the resistor R2 and the capacitor C2 are such that only a relatively gradual potential change generated between the bias voltage VB1 and the power supply voltage VDD is transmitted through these resistors and capacitors, in other words, the bias voltage VB1. And a relatively steep potential change that occurs between the power supply voltage VDD and the level change of the output signal Vout of the operational amplifier circuit that is absorbed by the low-pass filter including these resistors and capacitors cancel each other out. Are designed to have a resistance value and a capacitance value of. As a result, the level fluctuation of the output signal Vout of the operational amplifier circuit due to the potential fluctuation of the bias voltage VB1 can be suppressed, so that the PSRR characteristic of the operational amplifier circuit is improved and the performance of the communication system including the operational amplifier circuit is improved. Is something that can be promoted.

FIG. 2 is a circuit diagram of a second embodiment of the operational amplifier circuit to which the present invention is applied. It should be noted that this embodiment basically follows the embodiment of FIG. 1 described above, and therefore description will be added only to portions different from this.

In FIG. 2, the operational amplifier circuit of this embodiment includes a P-channel MOSFET P5 (seventh MOSFET) which receives the bias voltage VB1 at its gate.
The source of this MOSFET P5 is coupled to the power supply voltage VDD, and its drain is composed of two N-channel MOSFETs N5 (eighth MOSFET) and N formed in series.
6 (9th MOSFET), and is coupled to the ground potential VSS. The MOSFET P5 acts as a constant current source by receiving the bias voltage VB1 at its gate,
The drains and gates of the SFETs N5 and N6 are commonly coupled to form a diode. This causes MOSFETs P5 and N5 and N6 to
A bias voltage generating circuit is configured, and the gate of the MOSFET N5 is connected to the N-channel MOSF from the ground potential VSS.
A predetermined bias voltage VB2, which is twice as high as the threshold voltage of ET, that is, 2 Vth, is formed and supplied to the gate of the N-channel MOSFET N3 forming the phase compensation circuit.

In this embodiment, the capacitor C1 which constitutes a low pass filter together with the resistor R1 is provided between the gate of the MOSFET P1 which serves as a constant current source and the gate of the MOSFET N5 which constitutes the bias voltage generating circuit, that is, the bias voltage supply point VB2. To be Therefore, the capacitance C1
The potential of the lower electrode of the MOSFET is higher than the potential of the lower electrode of the capacitor C2 forming another low-pass filter together with the resistor R2 by the threshold voltage of the MOSFET N3. As a result, the transfer characteristics of the two low-pass filters are further approximated, and the level fluctuation of the output signal Vout of the operational amplifier circuit due to the potential fluctuation between the power supply voltage VDD and the bias voltage VB1 being transmitted through these low-pass filters. By further compressing the difference, the PSRR characteristic of the operational amplifier circuit can be further improved.

The resistor R in the operational amplifier circuit of FIG.
1 indicates the bias voltage supply point VB as shown in FIG.
1 and the common-coupled gates of the MOSFETs P1 and P5 that are constant current sources, and the capacitance C1 is M
It can be provided between the commonly coupled gates of the OSFETs P1 and P5 and the ground potential VSS. In this case, the change in the gate potential of the MOSFET P5 due to the change in the potential between the power supply voltage VDD and the bias voltage VB1 is changed by the MOSF.
The PSRR characteristic of the differential amplifier circuit can be further improved by approaching the fluctuation of the gate potential of ETP1.

Further, as shown in FIG. 4, the operational amplifier circuit of FIG. 3 has a capacitance C provided between the power supply voltage VDD and the commonly coupled gates of the MOSFETs P1 and P2.
5 (fourth capacitance), power supply voltage VDD and MOSFETP
And a capacitor C6 (fifth capacitor) provided between the capacitor C4 and the capacitor C4. In this case, the capacitors C5 and C6 serve as smoothing capacitors and act to absorb the high frequency noise of the bias voltage VB1 at the gates of the MOSFETs P1 and P2 and P4, and thereby the PSRR of the operational amplifier circuit.
The characteristics will be further improved.

As shown in the above-described embodiments, by applying the present invention to a bootstrap type operational amplifier circuit having a MOSFET as a basic structure, the following operational effects can be obtained. (1) First and second P-channel type differential type
MOSFET, the first power supply voltage, and the first and second
P-channel type third MOSFET provided between the MOSFET and a commonly connected source of the MOSFET, and the gate of the second MOSFET provided between the output terminal of the circuit and the second power supply voltage. A fourth N-channel MOSFET that receives a potential and a fifth P-channel type provided between the first power supply voltage and the output terminal of the circuit.
Second MOSFET, a second resistance provided between the bias voltage supply point to which a predetermined bias voltage is supplied and the gate of the fifth MOSFET, and the fifth MOSFE.
In a bootstrap type operational amplifier circuit including a second capacitor provided between the gate of T and the gate of the fourth MOSFET, between the bias voltage supply point and the gate of the third MOSFET. A first resistance provided and a first capacitance provided between the gate of the third MOSFET and the second power supply voltage are added, and the resistance value of the first resistance and the static capacitance of the first capacitance are added. The capacitance value of the output signal of the circuit due to the potential variation between the first power supply voltage and the bias voltage being transmitted to the gate of the third MOSFET through the first resistance and the first capacitance. The level change and the fifth resistance through the second resistance and the second capacitance
By designing to cancel the level fluctuation of the output signal due to being transmitted to the gate of the MOSFET, the level fluctuation of the output signal of the circuit due to the potential fluctuation between the first power supply voltage and the bias voltage is eliminated. This has the effect of offsetting and reducing the absolute value.

(2) According to the above item (1), the PSRR characteristic of the bootstrap type operational amplifier circuit can be improved. (3) In the above items (1) and (2), a third circuit is provided between the output terminal of the circuit and the gate of the fourth MOSFET.
And a gate of the N-channel type sixth MOSFET for receiving the second bias voltage, a phase compensation circuit is provided, and the first bias voltage is applied to the gate between the first and second power supply voltages. 7th M of P channel type to receive
A bias voltage generating circuit is provided in which an OSFET and an N-channel type eighth and ninth MOSFETs whose drains and gates are commonly coupled are connected in series.
The gate potential of the MOSFET is supplied to the gate of the sixth MOSFET as the second bias voltage, and the first capacitance is provided between the gate of the third MOSFET and the second bias voltage supply point. By providing, the characteristics of the low-pass filter composed of the first resistor and the capacitor and the characteristic of the low-pass filter composed of the second resistor and the capacitor are brought close to each other,
The PSRR characteristic of the operational amplifier circuit can be further improved.

(4) In the above item (3), the first resistor is connected to the first bias voltage supply point and the third and seventh MOSs.
The first power supply is provided between the common-coupled gates of the FETs and the first capacitance is provided between the common-coupled gates of the third and seventh MOSFETs and the second power supply voltage. Voltage variation of the gate voltage of the seventh MOSFET due to the potential variation between the voltage and the first bias voltage.
It is possible to bring the effect that the potential variation of the gate voltage of the OSFET can be approximated and the PSRR characteristic of the differential amplifier circuit can be further improved. (5) In the above items (1) to (4), a fourth capacitor is provided between the first power supply voltage and the gate of the third MOSFET so that the first power supply voltage and the fifth MOSFET are connected to each other. By providing a fifth capacitor between the third and fifth MOSFETs
It is possible to absorb the high frequency noise of the first bias voltage at the gate of, and to further improve the PSRR characteristic of the operational amplifier circuit. (6) According to the above items (1) to (5), it is possible to obtain the effect of promoting higher performance of a communication system including a bootstrap type operational amplifier circuit.

The invention made by the present inventor has been specifically described above based on the embodiments, but the invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say. For example, in the embodiment of FIGS. 1 to 4, resistors R1 and R
2 can be replaced with a MOSFET having the same on-resistance value, and the capacitors C1 to C6 can be replaced by MOSF.
The gate capacitance of ET can also be used. Capacity C in FIG.
5 and C6 are the power supply voltage VDD and MOSFETP of FIG.
1 and the gates of P4 and the power supply voltage VDD and the MOSFETs P1 and P of FIG.
It can also be provided between each of the four gates. Further, the specific configuration of the operational amplifier circuit, the polarity and absolute value of the power supply voltage, the conductivity type of the MOSFET, and the like can take various embodiments.

In the above description, a case where the invention made by the present inventor is mainly applied to a bootstrap type operational amplifier circuit mounted in a communication integrated circuit of a communication system which is a field of application of the invention is described. However, the present invention is not limited thereto, and can be widely applied to at least a bootstrap type operational amplifier circuit and various integrated circuit devices including the same.

[0030]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, the P-channel type first and second P-channel type MOSFETs in the differential form, and the P-channel type MOSFET provided between the first power supply voltage and the commonly connected sources of the first and second MOSFETs. Third MO
An N-channel fourth MOSFET provided between the SFET and the output terminal of the circuit and the second power supply voltage and receiving the drain potential of the second MOSFET at its gate.
A P-channel type fifth MOSFET provided between the first power supply voltage and the output terminal of the circuit, a bias voltage supply point to which a predetermined bias voltage is supplied, and a gate of the fifth MOSFET. A second resistor provided between the gate of the fifth MOSFET and the fourth MO;
A bootstrap type operational amplifier circuit including a second capacitor provided between the gate of the SFET and a first resistor provided between the bias voltage supply point and the gate of the third MOSFET. The third MOSFE
A first capacitance provided between the gate of T and the second power supply voltage is added, and the resistance value of the first resistor and the capacitance value of the first capacitance are set to the first power supply voltage and the above. Level fluctuation of the output signal of the circuit due to the potential fluctuation between the bias voltages being transmitted to the gate of the third MOSFET through the first resistor and the first capacitor, and the second resistor and the second capacitor. By designing so as to cancel out the level fluctuation of the output signal of the circuit that is transmitted to the gate of the fifth MOSFET via the above, the potential fluctuation between the first power supply voltage and the bias voltage It is possible to cancel the level fluctuation of the output signal of the accompanying circuit and reduce its absolute value. As a result, it is possible to improve the PSRR characteristic of the operational amplifier circuit and promote high performance of a communication system including the operational amplifier circuit.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a first embodiment of a bootstrap type operational amplifier circuit to which the present invention is applied.

FIG. 2 is a circuit diagram showing a second embodiment of a bootstrap type operational amplifier circuit to which the present invention is applied.

FIG. 3 is a circuit diagram showing a third embodiment of a bootstrap type operational amplifier circuit to which the present invention is applied.

FIG. 4 is a circuit diagram showing a fourth embodiment of a bootstrap type operational amplifier circuit to which the present invention is applied.

FIG. 5 is a circuit diagram showing an example of a conventional bootstrap type operational amplifier circuit.

[Explanation of symbols]

P1 to P5 ... P channel MOSFET, N1 to N
6 ... N-channel MOSFET, R1 to R2 ...
Resistance, C1-C6 ... Capacity.

Claims (5)

[Claims] 1. A common combination of first and second MOSFETs (P2 and P3) of a first conductivity type in a differential form, a first power supply voltage (VDD) and the first and second MOSFETs. The third of the first conductivity type provided between the third source and the source
MOSFET (P1) and the output terminal of the circuit (Vou
t) and a second power supply voltage (VSS), and a second conductivity type fourth MOSFET (N4) which receives the drain potential of the second MOSFET at its gate and a first power supply voltage. A fifth MOSFET (P4) of the first conductivity type provided between the output terminal of the circuit and a first MOSFET provided between the first bias voltage supply point (VB1) and the gate of the third MOSFET. (R1), the first capacitance (C1) provided between the gate of the third MOSFET and the second power supply voltage, the first bias voltage supply point, and the fifth MOSFET. A second resistor (R2) provided between the gate of the fifth MOSFET and a gate of the fourth MOSFET (C2) provided between the gate of the fifth MOSFET and the gate of the fourth MOSFET. Characteristic operational amplifier circuit. 2. The first resistance and the first capacitance are the first
Level fluctuation of the output signal of the circuit due to the potential fluctuation between the power supply voltage and the first bias voltage being transmitted to the gate of the third MOSFET through these resistors and capacitors, and the first power supply voltage. And the level fluctuation of the output signal due to the potential fluctuation between the first bias voltage and the second resistance and the second capacitance being transmitted to the gate of the fifth MOSFET, should be offset. The operational amplifier circuit according to claim 1, wherein the operational amplifier circuit has a predetermined resistance value and a predetermined capacitance value, respectively. 3. The sixth MOSFET of the second conductivity type whose source is coupled to the gate of the fourth MOSFET and whose gate is coupled to the second bias voltage supply point (VB2) in the operational amplifier circuit. (N3) and the sixth MO
A phase compensation circuit including a third capacitance (C3) provided between the drain of the SFET and the output terminal of the circuit, the source of which is coupled to a first power supply voltage, and the gate of which is the first power source voltage.
A seventh MOSFET (P5) of the first conductivity type coupled to the bias voltage supply point of the second MOSFET, the gate and drain of which are coupled to the drain of the seventh MOSFET and serving as the second bias voltage supply point. 6 MOSFET
Conductivity type eighth MOSFET coupled to the gate of the
(N5) and the ninth MOSFET (N6) of the second conductivity type, which is provided between the source of the eighth MOSFET and the second power supply voltage and whose gate and drain are commonly coupled.
And a bias voltage generation circuit including: and the first capacitance is provided between the gate of the third MOSFET and the second bias voltage supply point. The operational amplifier circuit according to claim 1 or 2, which is characterized by the above. 4. The gates of the third and seventh MOSFETs are commonly coupled, and the first resistor is
The first bias voltage supply point and the third and seventh M
Provided between the commonly connected gates of the OSFETs,
3. The first capacitor is provided between the common-coupled gates of the third and seventh MOSFETs and a second power supply voltage, claim 1, claim 2 or claim 3. Item 3 operational amplifier circuit. 5. The operational amplifier circuit includes a fourth capacitor (C5) and a fifth capacitor (C5) which are provided between the first power supply voltage and the gates of the third and fifth MOSFETs, respectively.
6. The method according to claim 1, further comprising 6).
The operational amplifier circuit according to claim 2, claim 3, or claim 4.