JP2505390B2 - Differential amplifier circuit - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a differential amplifier circuit composed of MOSFETs (insulated gate field effect transistors), and for example, converts a high-frequency image signal into a binary pattern signal. The present invention relates to a technique effectively used for a differential amplifier circuit used to do so.

[Background technology]

In a differential amplifier circuit, the characteristics of pair elements included in the differential amplifier circuit do not match each other due to variations in manufacturing conditions, etc., and therefore an offset voltage that forms an output voltage of a certain value even if an input signal of the same value is supplied. have.
As a circuit for adjusting the offset in such a differential amplifier circuit, trimming a resistance means as its load may be considered. However, in addition to complicating the circuit, a change in element characteristics over time may occur. On the other hand, it has a problem that it cannot deal with it.

The differential amplifier circuit composed of MOSFETs is
It is described on pages 259 to 261 of "MOS / LSI Design and Application" issued by Electronics Digest, Inc. on November 20, 1977.

[Object of the Invention]

An object of the present invention is to provide a differential amplifier circuit that realizes a low offset with a simple circuit configuration.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Outline of Invention]

The outline of a typical one of the inventions disclosed in the present application will be briefly described as follows. That is,
A part of the load circuit of the differential amplification MOSFET is configured, and the same input voltage is supplied to the differential amplification MOSFET by using the MOSFET as the variable impedance means whose control voltage is supplied to the gate. The impedance of the MOSFET as a means is unbalanced, and an offset is forcibly generated in one direction, and the control voltage supplied to the gate of one of the MOSFETs is changed in the direction in which the offset is reduced, and the differential amplifier circuit The offset is canceled by stopping the change of the control voltage supplied to the gate of the one MOSFET at the time when the polarity of the offset voltage in (1) is reversed.

〔Example〕

FIG. 1 is a block diagram showing one embodiment of the present invention. Although not particularly limited, each circuit block shown in the figure is formed on a semiconductor substrate such as single crystal silicon by a known semiconductor integrated circuit manufacturing technique, though not particularly limited thereto.

Although not particularly limited, the differential amplifier circuit Amp of this embodiment
Form a voltage follower circuit in which the inverting input (-) and the output terminal OUT are connected. The differential amplifier circuit
In order to cancel the offset of Amp, the non-inverting input (+) of the differential amplifier circuit Amp is switched between the input terminal IN and the reference voltage Vref by the switch SW. The reference voltage Vref and the signal at the output terminal OUT of the differential amplifier circuit Amp are compared by the voltage comparison circuit VC. The output signal of the voltage comparison circuit VC is used as a control signal of the pulse control circuit PC that controls the timing signals CK1 to CK3 for offset cancellation supplied to the differential amplifier circuit Amp.

FIG. 2 shows a circuit diagram of an embodiment of the differential amplifier circuit Amp. Although not particularly limited, the differential amplifier circuit Amp of this embodiment is composed of a CMOS circuit including a P-channel MOSFET and an N-channel MOSFET.

That is, the differential amplification MOSFETs Q2 and Q3 are P-channel
Composed of MOSFET, its common source and positive supply voltage
A P-channel MOSFET Q1 which performs a constant current operation is provided between Vcc and Vcc by supplying a constant bias voltage VB1 to its gate.

N-channel MOSFETs Q4 and Q6 forming a load circuit are provided at the drains of the differential amplification MOSFETs Q2 and Q3.
These MOSFETs Q4 and Q6 form an active load circuit by forming a current mirror form. Also,
The MOSFETs Q4 and Q6 are N-channel MOSFET Q5 as a variable impedance means for performing offset cancellation.
And Q7 are provided in parallel respectively. These MOSFETs
The gates of Q5 and Q7 are provided with capacitors C1 and C2 for holding a control voltage described later. The gates of the above MOSFETs Q5 and Q7 receive control signals VB2 and V2 via transmission gate MOSFETs Q9 and Q10 which operate by receiving timing signals CK1 and CK2, respectively.
B3 is supplied. When the conductance characteristics of the MOSFETs Q5 and Q6 are made equal, one control voltage VB
3 is set to be larger in absolute value than VB2. further,
The capacitor C2 is provided with a resetting MOSFET Q8 which operates by receiving the timing signal CK3.

The offset cancel operation in the differential amplifier circuit of this embodiment will be described with reference to the timing chart shown in FIG.

Before the differential amplifier circuit performs the amplifying operation, the following offset canceling operation is performed. That is,
In FIG. 1, the reference voltage Vref is supplied to the non-inverting input (+) of the differential amplifier circuit Amp. Then, in FIG. 2, the high level MOSFTQ9 of the timing signal CK1 is turned on to supply the control voltage VB2 to the capacitor C1. Further, the high level of the timing signal CK2 turns on the MOSFET Q10 to supply the control voltage VB3, and the high level of the timing signal CK3 turns on the MOSFET Q8 to reset the capacitor C2.

Next, when the timing signal CK2 remains at the high level and the other timing signals CK1 and CK3 are brought to the low level, the MOSFETs Q9 and Q8 are turned off. As a result, the control voltage VB2 is held in the one capacitor C1,
On the other hand, the control voltage VB3
Will start charging. Therefore, at this time MOSF
Since the impedance characteristic of the ETQ5 is smaller than that of the MOSFET Q7, for example, the output voltage Vout is made to have a negative offset voltage with respect to the reference voltage Vref, and gradually becomes smaller as the capacitor C2 is charged. It is detected by the inversion operation of the voltage comparison circuit VC that the two substantially match, and the timing signal CK2 is changed from the high level to the low level. As a result, the MOSFET Q10 is turned off, and the control voltage at that time, in other words, the control voltage that does not cause an offset, is applied to the capacitor.
Held in C2.

After such an offset cancel operation, the non-inverting input (+) of the differential amplifier circuit Amp is connected to the input terminal IN side and the input signal to be amplified is supplied.

Since the control voltage held by the capacitors C1 and C2 varies depending on the leak current, the offset cancel operation similar to the above is performed at a constant cycle. Although not particularly limited, when the differential amplifier circuit of this embodiment is used in a circuit for binarizing an image signal in a high speed facsimile, the offset canceling operation is performed by utilizing a time domain in which a signal after line feed is not transmitted. Is done.

〔effect〕

(1) The load of the differential amplifier circuit is brought into an unbalanced state by the variable impedance means, one variable impedance means is controlled in a direction to correct it, and when the offset is canceled, the variable impedance means By holding the control voltage capacitor,
The effect that the offset of the differential amplifier circuit can be reduced can be obtained.

(2) By using the variable impedance means for every fixed period,
By performing the offset cancel operation, it is possible to obtain an effect that it is possible to cancel the offset caused by the variation in the characteristics over time in the differential amplifier circuit.

(3) MOSFET as variable impedance means, a capacitor for holding its control voltage, and a voltage comparison circuit,
The effect that a low offset can be realized by a simple circuit such as a timing generation circuit is obtained.

Although the invention made by the present inventor has been specifically described based on the embodiments, the invention is not limited to the above-mentioned embodiments and can be variously modified without departing from the scope of the invention. Nor. For example, in the embodiment circuit of FIG. 1, the differential amplifier circuit Amp has its inverting input (-) and output terminal only during the offset cancel operation.
The OUT may be connected to form a voltage follower. When the voltage follower state is set in this way, the presence or absence of an offset can be easily identified by comparing the input reference voltage Vref and the output voltage Vout. Further, the conductivity types of the MOSFETs in FIG. 2 may be all reversed. Further, it may be configured by only the N-channel MOSFET or the P-channel MOSFET. Further, the differential amplifier element may use a bipolar transistor other than the above MOSFET. And
The load circuit in the differential amplifier circuit may use a fixed resistor or a MOSFET as a resistance means in addition to the active load using the current mirror circuit. Then, the MOSFETs Q5 and Q7 as the variable impedance means.
May have different conductance characteristics in advance to supply the same control voltage. Further, the load circuit having a fixed impedance may be provided with an offset in advance, and the variable impedance means may be provided on one side.

[Field of application]

INDUSTRIAL APPLICABILITY The present invention can be widely used as a differential amplifier circuit, and is particularly effective when applied to an A / D, D / A conversion circuit that requires a low offset, or an image signal binarization circuit in a facsimile machine. It plays.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a circuit diagram showing an embodiment of the differential amplifier circuit in FIG. 1, and FIG. 3 is an example of its offset canceling operation. FIG. 6 is a timing chart for explaining the above. Amp: Differential amplifier circuit, VC: Voltage comparison circuit, PC: Timing control circuit

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Yoshiharu Tatari 4026 Kujimachi, Hitachi City Hitachi Ltd. Hitachi Research Laboratory (72) Inventor Masayuki Tateoka 1479 Kamimizumoto Town, Kodaira Hitachi Micro Computer Engineering Incorporated (56) References JP-A-54-64955 (JP, A) JP-A-57-38064 (JP, A) JP-A-57-65907 (JP, A)

Claims (1)

(57) [Claims] 1. A differential amplification MOSFET for amplifying a facsimile image input signal, a drain of each of these differential amplification MOSFETs, and a parallel arrangement with a resistance means. First and second switch MOSFETs are provided at their gates. First and second loads that are supplied with first and second voltages via the terminals and operate as variable impedance means
Between a load circuit including a MOSFET, first and second capacitors provided in the gates of the first and second load MOSFETs and performing a voltage holding operation, and between the gate and the source of the second load MOSFET. And an amplifying section including a third switch MOSFET provided at the time of operation and in the time region where the input signal other than the line feed in the facsimile is not supplied, the amplifying section is made into a voltage follower form, and a reference voltage is applied to its input terminal. Is supplied, and the first and third switch MOSFETs are turned on to supply the first and second loads.
A first operation for making the combined impedance of the MOSFET and the corresponding resistance means unbalanced, and the first and third switch MOSFETs that have been turned on.
Is turned off, the second switch MOSFET is turned on, and the voltage supplied to the gate of the second load MOSFET is changed so that the difference in the output voltage from the reference voltage decreases. And the reference voltage and the output voltage of the amplifier are compared, and when the comparison output signal is inverted from one level to the other level, the second switch MOSFET is turned off, and A differential amplifier circuit comprising an offset adjusting circuit that performs a third operation of holding a gate voltage in a capacitor.