JPS6152012A - Differential amplifier circuit - Google Patents

Abstract

PURPOSE:To attain low offset by applying offset cancellation while a negative feedback loop for setting the gain of a differential amplifier circuit is opened. CONSTITUTION:A switch SW1 gives an input IN and a reference voltage Vref slectively to a non-inverting input IN(+) of a differential amplifier Amp. A switch SW2 switches an inverting input IN(-) to an output OUT or the non-inverting input (+). When the switch SW2 is thrown to the position of a contact (a), the offset voltage of the differential amplifier Amp. is amplified largely by the open loop gain and then outputted. The offset voltage output and the reference voltage are compared by a voltage comparator circuit VC to apply offset concellation. Since the offset voltage is amplified very largely, the offset voltage of the circuit VC itself is neglected.

Description

Detailed Description of the Invention [Technical Field] The present invention relates to a differential amplifier circuit configured with MOSFETs (!fa edge-gated field effect transistors). This technology is effective for use in differential amplifier circuits used to convert signals into digital signals.

[Background technology]

Differential amplifier circuits have an offset in which the characteristics of the paired elements included in the circuit do not match each other due to variations in manufacturing conditions, resulting in an output voltage of a certain value even when input signals of the same value are supplied. have. As a circuit for indirecting the offset in such a differential amplifier circuit, it is possible to trim the resistor means as the load, but in addition to complicating the circuit, it also causes problems due to changes in element characteristics over time. However, there are problems such as not being able to deal with the situation.

The differential amplifier circuit configured with MOSFETs is described in "rMoS/LSI Design and Application" published by 6m Electronics Digest on November 20, 1977.
P, 259-P, 261.

[Purpose of the invention]

An object of the present invention is to provide a differential amplifier circuit that achieves low offset with a simple circuit configuration.

The above and other objects and novel features of this invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Summary of the invention]

A brief overview of typical inventions disclosed in this application is as follows.

In other words, the invention of 1 is a MOS FET as a variable impedance means which constitutes a part as a load circuit of a differential increase @MO5FET and whose gate is supplied with a control voltage.
ET as the variable impedance means by supplying the same input voltage to the differential amplification MOSFET.
The impedance of the SFET is unbalanced to forcibly generate an offset in one direction, and the control voltage supplied to the gate of one MOSFET is changed in a direction that reduces the offset, thereby generating an offset in the differential amplifier circuit. When the polarity of the voltage is reversed, one of the above MO
During the offset canceling operation of stopping the change in the control voltage supplied to the gate of the 3F, ET, the negative feedback loop for setting the gain of the differential amplifier circuit is opened. In another aspect of the present invention, a binary output signal is obtained from an output terminal of a voltage comparison circuit that detects that the polarity of the offset voltage in the differential amplifier circuit is reversed.

[Embodiment 1] FIG. 1 shows a block diagram of an embodiment of the present invention. Each circuit block in the figure is not particularly limited by known semiconductor integrated circuit manufacturing technology, but It is formed on a semiconductor substrate such as single crystal silicon.

Although not particularly limited, the differential amplifier circuit of this embodiment, A
mp constitutes a voltage follower circuit whose inverting input (-) and output terminal OUT are connected. In order to cancel the offset of the differential amplifier circuit A Ill p, the inverting input (-) is set to a non-inverting state by the switching switch circuit SW2 so as to short-circuit the output terminal OUT or the re-input to form a negative feedback loop. Selectively connected to input (+). The non-inverting input (+) of the differential amplifier circuit Amp is selectively supplied with the input terminal IN and the reference voltage V ref by the switch SW1. This base is $1!
The voltage V ref and the signal at the output terminal OUT of the differential amplifier circuit A m p are compared in voltage by a voltage comparison circuit VC. This voltage comparison circuit VC includes the differential amplifier circuit A
A pulse control circuit PC that controls timing signals CKI to CK3 for offset cancellation supplied to mp.
form a control signal.

FIG. 2 shows a circuit diagram of an embodiment of the switch circuit SW2. Each circuit element in the figure is a known 0MO
3<complementary MO3) is formed on a single semiconductor substrate, such as single crystal silicon, using integrated circuit manufacturing techniques. In the following description, unless otherwise specified, MO
S FET is an N-channel MOSFET. In the following drawings, a MOSFET with a straight line added between the source and drain is a P-channel type.

Although not particularly limited, the integrated circuit is formed on a semiconductor substrate made of single-crystal P-type silicon. N channel MOS
The FET is made of polysilicon, which has a source region, a drain region formed on the surface of the semiconductor substrate, and a thin gate insulating film formed on the surface of the semiconductor substrate between the source region and the drain region. Consists of a gate electrode. The P-channel MOSFET is formed in an N-type well region formed on the surface of the semiconductor substrate.

Thereby, the semiconductor substrate constitutes a common substrate gate for a plurality of N-channel MOS FETs formed thereon. The N-type well region constitutes the base cage of the P-channel MOSFET formed thereon. The substrate gate of the P-channel MOS FET, ie, the N-type well region, is coupled to the power supply terminal Vcc of FIG.

The switch circuit SW2 includes an N-channel MOSFET Q11, a P-channel MOSFET QI2, and a differential N-channel MOS FET Q13 and P channel 7 are connected in parallel between the inverting input (-) of the amplifier circuit and the output terminal OUT.
MO5FETQ14. Above 2
! ll MO5FETQI 1°Ql2 and Ql3. Ql
4 is selectively turned off by the switching signal GO, the switching signal GC is set to N+Y'/channel MO
It is supplied to the gates of SFETQ11 and P-channel M'05FETQ14. The switching signal GC is supplied to the inverter circuit IV. The switching signal GC inverted by this inverter circuit IV is applied to the N-channel MOSFET QI3 and the P-channel MOSFET QI3.
Supplied to the gate of TQ12. As a result, if the switching signal GC is at a high level, "N-channel MOS
FETQI 1 is in on state, P channel MOSFE
TQ14 is turned off. Due to the low level of the inverted signal of the signal GC, the P-channel MO5FETQI 2
is turned on and N-channel MOSFET QI3 is turned off. Therefore, the MO turned on is
SFETQI 1. The inverting input (-) and the non-inverting input (+) are coupled by Ql 2, and the same voltage is supplied to the re-inputs (-, +). Moreover, if the switching signal GC is at low level, contrary to the above case, MOSFETQI
1. Ql 2 in off state, MO'5FETQI 3.
Ql 4 is turned on. Therefore, the inverted input (
-) and the output terminal OUT, the differential amplifier circuit Amp is configured as a voltage follower.

Note that the other switch circuit SWI is also a MOSFE similar to the above.
It is composed of T.

FIG. 3 shows a specific circuit diagram of an embodiment of the differential amplifier circuit Amp. Although not particularly limited, the differential amplifier circuit A m p of this embodiment includes the above-mentioned P channel MOSFET and N channel MOSFET.
It is composed of three CMO circuits consisting of 'I'.

Differential amplification MOS FET Q2 and Q3 are composed of P-channel MOSFETs, and a constant bias voltage VBI is supplied to the gate between their common source and the positive power supply voltage Vcc. P-channel MOSFE 'I' Q 1 which performs constant current operation by
is provided. The drains of the differential amplification MOSFETs Q2 and Q3 are connected to N-channel MOS transistors constituting a 9-load circuit.
FETs Q4 and Q6 are provided. These MOS
FET Q4, Q6 constitute an active load circuit by being placed in a current mirror configuration. Also, the above MOS FET Q.

4. Q6 is an N-channel MOSFET as variable impedance means for offset cancellation.
Q5 and Q7 are each provided in parallel form. These MOSFETQ5. The gate of Q7 is provided with capacitors CI and C2 for holding a control voltage, which will be described later. The above MOSFETQ,5. The gates of Q7 each receive a timing signal CK1. Transmission gate MOSFET Q9 that operates in response to GK2. Control voltage ■B via QIO
2 and VB3 are supplied. In addition, the above MO5FETQ5
When the conductance characteristics of Q6 and Q6 are made equal, the one control voltage VB3 is set to be larger in absolute value than VB2. Furthermore, the capacitor C2 is connected to a reset MO which operates in response to the timing signal CK3.
SFETQ8 is provided.

The off-cent canceling operation in the differential amplifier circuit of this embodiment will be explained with reference to the timing chart shown in FIG.

Before the differential amplifier circuit performs an amplification operation, the following offset cancellation operation is performed.

That is, in FIG. 1, the switch circuit SW1 is closed to the a side, so that the base t$ voltage V ref is supplied to the non-inverting input (+) of the differential amplifier circuit A m p.

Further, by closing the switch circuit S'wv2 to the a side, the same reference voltage Vrr=f is supplied to the re-inputs (+, -), and the jr:'tM loop is opened. Therefore, the input OFF voltage Vof is amplified by the above-mentioned WF>open loop gain in the amplifier circuit (for example, 80 dB=10 ooo times) and outputted to the output OUT of the differential amplifier circuit Amp.

In this state, the timing signal CKI.

MOS FETQ 9 is turned on by level
7 and supplies the control voltage VB2 to the capacitor C1.8 Also, due to the high level of the timing signal CK2, the MOS
F E T Q i Turn off the control voltage ■B
3, and at the same time, the timing (high level of the word CK3) turns off the MOS FET Q8 and resets the keypad C2.

Next, when the timing signals CK1-CKa are set to low level, MOS FET Q 9 and 0.8 are turned off, and MOS FET Q 10 is turned on. As a result, the control voltage VB2 is held in one capacitor C1, and the other capacitor C1 is held at the control voltage VB2.
2, the control voltage VB3 is applied through MOSFET QIO.
Charging starts. Therefore, at this time MO
The impedance characteristics of SFETQ5 are those of MOSFETQ7
For example, the output OUT has a negative offset voltage Vof with respect to the reference voltage Vref.
This offset voltage Vof gradually decreases as the capacitor C2 is charged, as shown by the dotted line in the figure. In this case, the output voltage Vout of the output terminal OUT is the offset voltage +-m voltage Vof amplified by the open loop gain, so
As shown by the solid line, it remains at a low level like the ground potential of the circuit. If the two match, and even a slight reversal occurs, the output voltage Vout amplified by the open loop gain is inverted to the power supply voltage level. The voltage comparator circuit VC detects this level reversal and
The timing signal CK2 is changed from low level to high level.

As a result, the FAOS FETQ 10 is turned off, so the control voltage at that time, in other words, the control voltage that is
2. In such an off-cent cancellation operation, the off-cent voltage of the differential amplifier circuit A m p inputted to the voltage comparator circuit VC is multiplied by its open loop gain, so that the off-cent voltage existing in the voltage comparator circuit VC is Can be ignored. Thereby, for example, a logic gate circuit such as a CMOS impark circuit can be used as the voltage comparison circuit VC.

Because, as mentioned above, the open loop gain is 80d.
In the case of B, the CMOS operates at the power supply voltage Vcc of SV.
The logic threshold voltage of the impark circuit is set to 2,5
2, it can be regarded as a voltage ratio t21 [71 path with an offset voltage of 2°5V above. but,
Since the off-cent voltage of the differential amplifier circuit A m p supplied to the input of this CMOS inverter circuit is multiplied by 10,000, in L% filli terms, the off-cent voltage of the above CMO3 inverter circuit is ±0.25 m
It can be considered as V. Therefore, when the voltage comparator circuit VC is constituted by a differential amplifier circuit as in the embodiment shown in FIG. 1, the offset voltage can be substantially ignored as described above.

Incidentally, when the voltage comparison circuit VC is constituted by such a logic circuit, the switch circuit SW1 and the reference voltage V ref in the circuit shown in FIG. 1 become unnecessary.

Note that after the offset canceling operation as described above, the differential amplifier circuit A m is switched by switching the switch circuit SWI.
The non-inverting input (+) of p is connected to the input terminal IN side. Furthermore, by switching the switch circuit SW2, the differential amplifier circuit Amp is put into a voltage follower configuration, and performs an amplification operation (in this example, an impedance conversion operation) of the input signal to be amplified.

Since the control voltages held by the capacitors CI and C2 vary depending on their leakage currents, offset/to cancel operations similar to those described above are performed at regular intervals. Although not particularly limited, when the differential amplifier circuit of this embodiment is used in a circuit that binarizes an image signal in a high-speed facsimile, the above-mentioned offset canceling operation can be performed using the time domain in which no signal is transmitted after the line feed. is performed for each time domain.

[Embodiment 2] FIG. 5 shows a block diagram of another embodiment in which the present invention is applied to the binarization circuit described above.

The differential amplifier circuit A m p of this embodiment has its inverting input (-) and output terminal O as in the embodiment shown in FIG.
Configures a voltage follower circuit connected to the UT. In this embodiment, in order to cancel the offset of the differential amplifier circuit A m p, its non-inverting input (+) is connected to the input terminal IN and the reference voltage V r by a switch SW.
ef is selectively supplied. This reference voltage Vref and the output signal of the differential amplifier circuit Amp are the voltage comparator circuit V
The voltages are compared by C. This voltage comparison circuit VC is
On the other hand, timing signals CKI to CK for offset cancellation supplied to the differential amplifier circuit A m p
A control signal for the pulse control circuit pc that controls the pulse control circuit 3 is formed. On the other hand, the voltage comparison circuit VC forms and outputs a binary signal indicating whether the input signal supplied from the input terminal IN with respect to the reference voltage V ref is at the H/f level or the low level. The specific circuit of the differential amplifier circuit Amp is the same as the embodiment shown in FIG. 3 above.

The offset canceling operation in this embodiment will be explained with reference to the timing chart shown in FIG.

Prior to performing the binarization operation of the input analog signal supplied from the input terminal IN, the following offset canceling operation is performed. That is, in FIG. 5, the switch circuit SW connects the non-inverting input (+
) is switch-controlled to supply the reference voltage Vref. In this state, similar to the offset cancel operation, the high level of the timing signal CKI causes the MO
The 5FET Q9 is turned on and the control voltage VB2 is supplied to the capacitor C1. Further, the high level of the timing signal CK2 turns off the MOSFET QIO to cut off the control voltage VB3, and the high level of the timing signal CK3 turns on the MOSFET Q8, thereby putting the capacitor c2 in the reset state.

Next, when the timing signals CKI to CK3 are set to low level, MO5FETQ9 and Q8 are turned off, and M
OSFETQIO turns on. As a result, the control voltage VB2 is held in one capacitor c1, and charging of the other capacitor C2 is started with the control voltage B3 through the MOSFET QIO. Therefore, at this time, the impedance characteristic of MO5FETQ5 becomes smaller than that of MOSFETQ7, so for example, the output voltage VouL of the differential amplifier circuit Amp is made to have a negative offset voltage with respect to the reference voltage Vref, and this The offset voltage gradually decreases as the capacitor c2 is charged, as shown by the dashed line in the figure. When the level relationship between them is reversed, the voltage comparison circuit VC detects this level reversal and changes the timing signal CK2 from low level to high level. As a result, the MOSFET QIO is turned off, so that the control voltage at that time, in other words, the control voltage that does not cause offset is held in the capacitor C2.

In this case, although an offset voltage exists in the voltage comparator circuit VC, at the timing when its output is inverted, the difference between the reference voltage Vref and the differential amplifier circuit A, including its own offset voltage, is m p
This is to detect that the output voltage Vout and N' match. Therefore, after the offset canceling operation as described above, the switch circuit SW is switched to supply the signal from the input terminal IN.

The supplied analog signal is supplied to the non-inverting input (+) of the differential amplifier circuit Amp, and an output voltage Vout is formed accordingly, and the voltage comparator circuit VC determines whether it is a high level or a low level with respect to the reference voltage Vref. In the voltage comparison operation that performs value determination, it can be assumed that the offset voltages of both the differential amplifier circuit A m p and the voltage comparison circuit VC do not exist.

〔effect〕

(1) The load of the differential amplifier circuit is brought into an unbalanced state by the variable impedance means, one of the variable impedance means is controlled in a direction to correct the imbalance, and when the offset is canceled, the load of the differential amplifier circuit is unbalanced. In an offset canceling operation in which a control voltage is held in a capacitor, the differential amplifier circuit is operated in an oven loop state to amplify and output the offset voltage. This makes it possible to ignore the offset voltage of the voltage comparator circuit for determining whether or not the offset has been canceled, thereby achieving the effect that the differential amplifier circuit can have a low offset.

(2) By amplifying the offset voltage of the above-mentioned differential amplifier circuit by its oven loop gain and outputting it, a voltage comparison circuit that identifies the polarity reversal can be used as a voltage comparison circuit that has a substantially large offset voltage, such as a logic gate circuit. You can use the circuit. This provides the effect that the circuit can be simplified.

(3) A voltage comparator circuit that puts the load of the differential amplifier circuit in an unbalanced state using variable impedance means, controls one variable impedance means in a direction to correct the imbalance, and detects that the offset has been canceled. By obtaining a binarized output signal of the analog input voltage from , it is possible to obtain a binarized output signal in which both the offset voltages of the differential amplifier circuit and the voltage comparator circuit are canceled.

(4) By obtaining a binary output signal from the voltage comparator circuit, the voltage comparator circuit can perform offset canceling operation and
Since it can be used for both value conversion operations, it is possible to achieve the effect of simplifying the circuit.

(5) Using variable impedance means at regular intervals,
By performing the offset canceling operation, it is possible to cancel offsets caused by variations in characteristics over time in the differential amplifier circuit (or the differential amplifier circuit and the voltage comparison circuit).

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that this invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. For example, in the embodiment circuit of FIG. 1, the differential amplifier circuit Amp may be provided with a negative feedback circuit for gain setting. All of the conductivity types of the MOSFETs constituting the differential amplifier circuit shown in FIG. 3 may be reversed. Also, N channel/
The load circuit in the differential amplifier circuit may be configured only with an I/MO5FET or a P-channel MOsFET.Furthermore, the differential amplifier element may be a bipolar transistor based on the MOSFET described above. In addition to active loads using the above-mentioned current mirror circuit, MOS F E as a fixed resistance or resistance means
The above MOSFETQ5.T may be used as the variable impedance means. Q7 is
The same control voltage may be supplied with different conductance characteristics in advance. Also,
The load circuit having a fixed impedance may be provided with an offset in advance, and the variable impedance means may be provided on one side.

[Application field]

The present invention can be widely used as a differential amplifier circuit, and is particularly applicable to A/D and D/A conversion circuits that require a low offset voltage.
Alternatively, the present invention can be effectively used in a binarization circuit for image signals in a facsimile machine.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention. FIG. 2 is a circuit diagram showing an embodiment of the switch circuit. FIG. 3 is an implementation of the differential amplifier circuit shown in FIG. FIG. 4 is a timing diagram showing an example of the off-cent cancel operation + operation; FIG. 5 is a block diagram showing another embodiment of the present invention; FIG. FIG. 3 is a timing chart showing an example of a cent cancel operation.

Claims (1)

[Claims] 1. A differential amplification element and an MO as a variable impedance means that constitutes a part of a load circuit provided to each of these differential amplification elements and whose gate is supplied with a control voltage.
SFET, a differential amplifier circuit to which a negative feedback circuit for gain setting is connected by a first switch circuit, and a second switch circuit that selectively supplies the same input voltage to the differential amplifier element. , a comparison circuit receiving the output voltage of the differential amplifier circuit and the input voltage, a control signal for the switch circuit, and a MOSFE as the variable impedance means.
a control circuit that forms a control voltage that is supplied to the gate of one MOSFET in a direction that reduces the difference in output voltage from a state where the impedance of T is unbalanced;
Prior to the differential amplification operation of the differential amplifier circuit, the control circuit turns the first switch circuit off and the second switch circuit on to change the control voltage, and outputs the voltage comparison circuit. When the MO of one of the above is reversed,
A differential amplifier circuit characterized in that a change in a control voltage supplied to a gate of an SFET is stopped. 2. A pair of MOS as the variable impedance means
A patent characterized in that the gates of the FETs are each provided with a capacitor that holds the control signal, and the means for unbalancing the impedance is performed by a MOSFET that discharges the charge of one of the capacitors. A differential amplifier circuit according to claim 1. 3. The differential differential according to claim 1 or 2, wherein the switch circuit is a CMOS switch circuit constituted by a pair of N-channel MOSFET and P-channel MOSFET arranged in parallel. Amplification circuit. 4. A differential amplification element and an MO as a variable impedance means that constitutes a part of a load circuit provided for each of these differential amplification elements and whose gate is supplied with a control voltage.
a differential amplifier circuit including an SFET, a switch circuit that supplies a reference voltage to an input terminal of the differential amplifier circuit, a voltage comparison circuit that receives the output voltage of the differential amplifier circuit and the reference voltage, and the switch. a control circuit that forms a control voltage that is supplied to the gate of one MOSFET in a direction that reduces the difference in output voltage from a state in which the control signal of the circuit and the impedance of the MOSFET as the variable impedance means are unbalanced; Prior to the differential amplification operation of the differential amplifier circuit, the control circuit turns on the switch circuit to change the control voltage, and when the output of the voltage comparison circuit is inverted, one of the MOSFEs
A differential amplifier circuit characterized in that a change in a control voltage supplied to a gate of a voltage comparator circuit is stopped, the switch circuit is turned off, and a binary signal is sent from an output terminal of a voltage comparator circuit. 5. A pair of MOS as the variable impedance means
A patent characterized in that the gates of the FETs are each provided with a capacitor that holds the control signal, and the means for unbalancing the impedance is performed by a MOSFET that discharges the charge of one of the capacitors. A differential amplifier circuit according to claim 4.