JPS62269512A - Voltage comparator - Google Patents

Abstract

PURPOSE:To attain high accuracy and high speed by using a differential amplifier setting in itself the bias voltage of a load transistor (TR) so as to reduce the offset of a comparator even when a capacitance element having no voltage dependancy is not used. CONSTITUTION:Switches SW3, SW4 are closed in the preset mode with a clock theta1 at a high level and the gate and drain of load TRs MP1, MP2 are short- circuited to automatically set a bias voltage. In case, a switch SW2 is also closed and a reference voltage VREF is applied to the gate of a drive TR MN2. If unbalanced threshold voltage exists between differential TRs MN2, MN3 and MP1, MP2, the bias voltage of the TRs MP1, MP2 are set accordingly. In the amplifier mode, switches SW3,SW4 are opened and the said bias voltage is kept respectively in capacitors CGSI, CGS2. Further, the switch SW2 is opened and the switch SW1 is closed to apply an input voltage VIN to the gate of the TR MN2. In the latch mode, the input voltage difference is amplified rapidly up to the logical amplitude level. Thus, the input converted offset voltage is reduced without using a capacitance element.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a voltage comparator (hereinafter referred to as a controller) that determines the magnitude of the voltage of 2al with high precision and high speed.

(Problems to be solved by the invention based on the prior art) MO
In order to improve the precision of a t comparator using an S device, it is especially essential to reduce the offset voltage. Therefore, a comparator which is essentially offset-free using a complicated CMOS inverter, capacitor, and switch as shown in FIG. 5 has been proposed. ■G is the input voltage s, VRKF is the reference voltage, VDD is the positive power supply voltage, Cc is the input voltage, SWa, Swc
is a switch driven by a clock φ, SWb is a switch driven by a clock φ having the opposite phase to φ, MNφ,
MPφ is an N-channel MOS transistor, a P-channel MOS transistor, and a Latch 1 n CM, respectively.
The latch is raised by the output fmm level of the OS inverter, and Q is determined by the latch output. FIG. 6 shows the waveform of the clock φ and the operating state of the comparator. When φ is in the high preset mode, SWa+bWc is closed, VRE'F is applied to node (2), and a predetermined voltage VM between VDD and ground potential, which determines the inverter's transfer characteristic F, is applied to nodes (2) and (2). Next, when φ changes to low and enters comparison mode, SW
a, 5ItlVc is opened and SWb is closed, and the voltage at node (2) becomes Vgo, and the voltage at node (2) changes to VE - v + vM. In other words, the voltage at the ef node (2) increases or decreases from vM depending on the magnitude of %VN and VRKF, and this voltage change is amplified by an inverter and voltage comparison is performed. This L sea urchin 1 (
The method of detecting the voltage difference between the WK of tal and the two switches is offset-free in principle, but as an answer, there is no voltage dependence such as a metal-insulator monometallic M (polysilicon) structure. (MOS: G-type, junction capacitance changes depending on voltage) becomes reliable, and it becomes safe to add a process to manufacture the container as an IC process, which complicates the process and inevitably lowers the yield.

It has a drawback that leads to high IC costs.

In addition, in order to provide peace of mind to the answer Jt', it is not possible to downsize, it is not possible to operate at high speed, and there are variations in capacity,
It has the disadvantage of poor reliability due to leakage from the valley.

(Means for Solving the Problems) The present invention was proposed in order to improve all the above-mentioned drawbacks, and for the purpose of the present invention, the entire structure - insulator - polysilicon (polysilicon) structure with voltage dependence, etc. VcMOS without any connection
The object of the present invention is to provide a high-accuracy, high-speed voltage comparator that reduces the influence of the offset voltage of a differential amplifier by using a transistor gate container and a switch.

In order to achieve the above object, the present invention provides a voltage comparator that compares the magnitude of two voltages, including three N-type MOS transistors and two P-type MOS transistors, and a first N-type MOS transistor. The source of the transistor is connected to the low power supply terminal, a voltage of one foot is applied to the gate, and the sources of the second and third N-type MOS transistors are connected to the drain.
A comparator analog voltage is applied to the gate of the second N-type MOS transistor via the first switch, and the first
A reference overvoltage is applied to the second switch which operates in opposite phase to the switch, a reference voltage is applied to the gate of the third N-type MOS transistor, and a reference voltage is applied to the drain of the second N-type MOS transistor. is connected to the drain of the first P-type MOS transistor, and this connection serves as the output terminal of the output point ki1, and the drain of the second P-type MOS transistor is connected to the drain of the third N-type MOS transistor/transistor. , this connection point is used as a second output terminal, the gate and drain of the first P-type MOS transistor are all connected by a third switch operating in the same phase as the second switch, and the source is connected to a high power supply terminal, The gate and drain of the second P-type MOS transistor are connected to a fourth switch operating in the same phase as the second switch:
2 of the latch, whose source is connected to the high power supply terminal, and which captures the magnitude of the -2 input terminal voltages at the change point of the clock voltage and outputs it as a high or low logic level. The gist of the invention is a voltage comparator characterized in that the first output terminal and the second output terminal are connected to respective input terminals of the voltage comparator.

A key point of non-invention is that in a voltage comparator, before starting the comparison operation, the P channel M
The purpose is to set the biases of the OS transistor and the N-channel MOS transistor so that the operations of both transistors are not unbalanced.

Next, description will be given of all the accompanying drawings which are embodying the invention.

It should be noted that the embodiments are merely illustrative, and it goes without saying that various changes and improvements may be made without departing from the spirit of the present invention.

Next, examples of the present invention will be described. FIG. 1 shows a first embodiment of the present invention, and FIG. 2 shows all the waveforms of each clock. VIN is the input voltage, VREF is the reference voltage, VB bias voltage, VDD is the power supply voltage, M, N1 to MN
3 is an N-channel MOS transistor, MPI, MP2μ
P-channel MUS transistor, SW2. swa, SW
4 is a switch driven by a clock signal φ1, SWI is a switch driven by a clock φ having an opposite phase to φ, VOUT, voU'rh MOS transistors MN 1 , M, N 2 .

MN3. The mutually complementary output voltages s of the differential amplifiers configured in MPI and MP2 are differential JJ 1
A latch whose input is the output of the 1a circuit, IN is an input terminal of the latch, Q is an output terminal of the Qfl latch, and φL is a clock voltage for driving the latch.

To explain the configuration in detail, MN2. MN3 is a transistor for driving the differential amplifier, and the input voltage VTN is applied to the gate of MN2 via the switch SWIffi, and the reference voltage VItE'F is applied to the gate via the switch SW2'. On the other hand, always refer to the gate of MN3 *:
E VREF is applied. The sources of MN2 and MN3 are commonly connected and connected to the drain of current source transistor MNI.

A bias voltage VBI of a constant value is applied to the gate of MNI so that a constant current flows in the on state. MPI is M
Use a load transistor for N2! +, the gate and drain of MPI are connected through switch 5W3rC. M
P2 is a load transistor for MN3, and similarly M
The gate and drain of P2 are connected by switch SW4. Difference kfJ amplifier output vOUT and negative phase output VOU
T is a latch (Latc) driven by the clock φLK.
h) is manually operated.

The comparator operation is a preset mode in which φ1 is at a high level, an Ang mode in which φ is at a high level and φL is at a high level, and 7. is divided into high level and nine low level latte modes. In preset mode, SW3. The bias voltage is automatically set by closing SW4 and shorting the gates and drains t of MPI and MP2, respectively. At this time, SW2 is also closed, and the reference [EE V
my is applied. Therefore, if there is an unbalance in threshold voltage, etc. between differential bare transistors MN2 and MN3 and MPI and MP2, MP
Bias voltages for I and MP2 are set.

Now, consider a case where there is an imbalance between the threshold voltages of the drive transistors MN2 and MN3 and the threshold voltages of the load transistors MPI and MP2. Current formula in the saturation region of MOS transistor IDS = β (VGS −V
T )2 (however, the drain voltage dependence is small, so ignore it fF-)) If we use f and assume that the drain currents of MN2 and MP1 are equal and the drain currents of MN3 and MP2 are equal, then equations (1) and (2) are obtained. is obtained.

IN(VGS-VTN, )” = βP(VDS3.
VTP, )” (13βN (VGS-VT
N, )" = βp (VDS, VTP, )'
(2) However, βN and βP are mobility constants s of N-channel transistor and P-channel transistor, respectively.
VGs is transistor MN2 in preset mode.
．． The gate voltage applied to MN3, VTN.

VTN! , VTP, , VTP, u each 0MN
2. MN3゜MPl, MP2 (7) L4 low value voltage, VD
S, , VDS, and I'm are the source voltages applied to MPI and MP2, respectively.

(11, From equation (2), imbalance of bias voltage between MPI and MP2 (△VB miVDS, -VDS2)
'/'1(3) The expression is given.

The first term is based on the threshold voltage imbalance of the drive transistor, and the second term is based on the threshold voltage imbalance of the load transistor.

The threshold voltage imbalance of the differential bare transistors contributes to the ``11'' load transistor MPI,
The bias voltage difference of MP2, ie, the output voltage difference in preset mode, appears as ΔVOUT=VOUT−VOUT.

Next, in amplifier mode, SW3. SW4 is opened and set in the preset mode, and a bias voltage of 7tMP1°MP2 is maintained at the gate-source response of MP1 and MP2, tCGS, (4s), respectively.

Furthermore, when SW2 opens and SWI closes, the input voltage V is applied to the gate of MN1.

The gain GA of the differential amplifier in amplifier mode is given by equation (4).

However, gn11UMN2. The transconductance of MN3, rl, is MN2. Output resistance of MN3, rt'D, M
P1.

This is the output resistance of MP2.

Since IGAI is sufficiently larger than 1, the input voltage difference required to cancel the output voltage difference ΔVOUT' that occurs in the preset mode is sufficiently small between ΔVOUT/GA and ΔVOUT. On the other hand, △VOUT is approximately equal to the input equivalent off-point (vQA) of the differential amplifier when there is no preset mode. Therefore, with the addition of a preset mode, it is possible to reduce the total F input conversion offset to 1/GA.

The latch captures the differential amplifier output at the point where the clock φL switches from high level to low level and enters latch mode.
Rapidly amplify input voltage differences to logic amplitude levels.

If the input conversion offset of lunch is m pressure t VOL, then
Input-referred offset voltage VO for the entire comparator
C is given by equation (5).

Key word (VOA+VOL) If the above-mentioned bare circuit is constructed in this configuration, the controller (input conversion) γ offset voltage can be reduced without using a capacitive element.

FIG. 3 shows an 81!2 embodiment of the present invention, which reduces the influence of parasitic displacement and fully guarantees highly accurate comparator operation. Normally, a MOS transistor has a gate-drain capacitance and a gate-source capacitance. Figure 3 shows load transistors M P 1 and MP
2 gate/drain capacitance COD, + CGD2s
Only the gate-source capacitance CGS, + CGS, is shown. MP3 is a P-channel MOS transistor whose gate length is equal to that of MPI and whose gate width is 1/2 that of MPI, and its source and drain are fully coupled and connected to the gate of MPI. VOUT is applied to the gate of MP3.

Further, MP4 is a P-channel MOS transistor whose gate length is equal to that of MP2 and whose gate width is 1/2 that of MP2, and its source and drain are fully coupled and connected to the gate of MP2. Other M wires, terminal relationships, etc. are the same as in FIG.

Comparator operation is also MP3. It is the same as FIG. 1 except for the MP4 part. MP3. In the configuration shown in FIG. 1 without MP4, the gate-drain capacitance of MPI and MP2 is 1i Q)
The presence of D, , CGD has the disadvantage that the original gain in the amplifier mode is reduced and the effect of offset reduction is reduced. This can be explained as follows. Considering only the MP1 part in the amplifier mode, the gate RTC will be in the state shown in Figure 4 where no power is applied. At this time, the equilateral differential resistance req seen from the support terminal is given by equation (6) O (Here, ω=2πf, f is the signal frequency 9g□, )1
Therefore, the percentage of sleep is high! If a transistor is used, r decreases. Since reqq becomes the load resistance of the drive transistor MN2, a decrease in gain occurs in the amplifier mode.

The decrease in req is caused by the change in the negative phase output voltage applied to the gate via COD, k, forming a negative feedback path, so the change in the positive phase output VOUT f CGD,
If it is applied to the gate of MPI through a capacitance i of the same magnitude as , and a gate voltage change is fully compensated for, no decrease in r6q will occur. M
The PI is the ninth CGD operating in the saturation region, with h-gate and drain overlapped structures being dominant. Therefore,
Transistor M in off state where only the overlap capacitance is visible
The above compensation effect can be achieved at P3. MP4 and MP
It has the same persistence as 3.

As described above, with this configuration, even if gate-drain capacitance is present as a parasitic capacitance, a decrease in amplifier mode gain does not occur, and the effect of offset reduction can be guaranteed.

Note that even if an N-channel MOS transistor is used in place of the P-channel MOS transistor in the above explanation, and a P-channel MOS transistor is used in place of the N-channel MOS transistor, the same operation and effect can be obtained even if the high and low power supplies are reversed. It is intended to be presented.

(Effect of the invention) As shown in the diagram above, since the invention uses a differential amplifier that completely sets the bias voltage of the load transistor by itself, the offset of the comparator can be reduced without using a capacitive element without voltage dependence. High precision is possible. Measure 1: An A/D conversion LSI can be realized using ordinary low-cost CMOS process technology for digital circuits, and is effective in reducing the cost and increasing the functionality of analog-digital mixed LSIs.

In addition to this, the second operation, which has no capacitance, becomes faster and can be made smaller. Furthermore, it has the effect of improving reliability because there is no variation in capacity or leakage from the capacitor.

[Brief explanation of the drawing]

Fig. 1 shows a first embodiment of the present invention, Fig. 2 is a timing chart of a comparator of the embodiment, Fig. 3 shows a second embodiment of the invention, and Fig. 4 shows a load transistor. 5
The figure shows a conventional comparator using a CMOS inverter, and FIG. 6 shows a timing chart of the conventional comparator. VDD...Positive power supply voltage VIN...Input voltage vxF...Reference voltage SW2. *SWb+ 5Wo---Switch φ
......Clock voltage for driving swa and swc 7...Clock voltage Cc for driving SWb...Capacity Latch 1...Clock Latch Q driven by φ... Latch output terminal MNφ...
・N-channel MOS transistor MPφ...P-channel MOS transistor vB engineering...Bias voltage VOUT, VOUT...Difference @ output voltage of two glazes of amplifier Latch...Differential input/output type latch IN
, IN...Latch input terminal Q, Q...Latch output terminal φL...Clock suitable voltage MN for driving the latch
1. MN2. MN3...N channel MOS transistor MPI, MP2...P channel MOS transistor S
W1. SW2. SW3. SW4...Switch φ,...
・・・・・・SW2. SW3. Clock 4 voltage φ for driving SW4, ...... Clock voltage CGS for driving SW1, ...... Gate-source '1 of MPI
48CGD,...MPI gate/drain capacitance CGS,...MP2 gate 0 source capacitance C
GD,...MP2 gate/drain 6mMP
3... P-channel MOS with the same gate length and 1/2 channel width as MPI) Ranjisk MP4...
... P-channel MOS transistor with the same gate length as MP2 and 1/2 channel size Patent applicant Nippon Telegraph and Telephone Corporation Figure 1 VIN V Kasumi σ

Claims (2)

[Claims] (1) A voltage comparator that compares the magnitude of two types of voltage is equipped with three N-type MOS transistors and two P-type MOS transistors, and the source of the first N-type MOS transistor is connected to the low power supply terminal. A constant voltage is applied to the gate, the sources of the second and third N-type MOS transistors are connected to the drain, and the comparison voltage is applied to the gate of the second N-type MOS transistor via the first switch. A reference voltage is applied through a second switch that operates in opposite phase to the first switch, and a third N-type M
A reference voltage is applied to the gate of the OS transistor, and the second
The first P-type M is connected to the drain of the N-type MOS transistor.
The drains of the OS transistors are connected, and this connection point is used as the first output terminal.The drain of the third N-type MOS transistor is connected to the drain of the second P-type MOS transistor, and this connection point is used as the second output terminal. The output terminal is connected to the gate and drain of the first P-type MOS transistor by a third switch operating in the same phase as the second switch, and the source is connected to the high power supply terminal. The gate and drain are connected by a fourth switch operating in the same phase as the second switch, the source is connected to a high power supply terminal, and has two input terminals, and the voltage of the two input terminals at the change point of the clock voltage is connected to the second switch. The first output terminal and the second output terminal are respectively connected to the two input terminals of a latch that captures the magnitude of the voltage and outputs it as a high or low logic level. (2) A third P-type MOS transistor with the same gate length and half the gate width as the first P-type MOS transistor of the voltage comparator
an S transistor and a fourth P-type MOS transistor having the same gate length and half the gate width as the second P-type MOS transistor.
an S transistor, the source and drain of the third P-type MOS transistor are connected to the gate of the first P-type MOS transistor, the gate is connected to the second output terminal, and the fourth The voltage comparison according to claim 1, wherein the source and drain of the P-type MOS transistor are connected to the gate of the second P-type MOS transistor, and the gate is connected to the first output terminal. vessel.