JPH058606B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a chopper type comparator used in an integrated A/D converter or the like.

[Background of the invention]

The conventional CMOS chip type comparator is described in the literature (IE ³ VOL SC-14No.6DEC1979,
pp.926-932). Figure 1 shows this comparator. This comparator is pMOS
A CMOS inverter consisting of 21 and nMOS 22, and a switch 40 that shorts the input and output of the inverter.
, reference voltage V _ref input terminal 13, and input signal V _io
It consists of an input terminal 12, a coupling capacitor 31, and switches 41 and 42 for switching the coupling capacitor to the terminal 12 or 14. Note that terminal 10
is an input terminal of the comparator, terminal 11 is an output terminal, and capacitor 32 is a load capacitance. This circuit operates with a two-phase clock as follows. During the clock period .phi., or reset period, switches 40 and 41 are closed and set so that when input terminal 10 is at the reference voltage, the output is at the logic threshold voltage.
In the next clock period, switch 40 is opened to operate the inverter as an amplifier, and at the same time, switch 41 is opened and switch 42 is closed to change the input voltage from the reference voltage to the input voltage. Then, the difference between the input voltage and the reference voltage is amplified and output.

This circuit is simple and excellent, but since the switch 40 is closed during the reset period and the input and output of the inverter are shorted, a through current flows from the power supply to the ground.
Not suitable for reducing power consumption. In particular, if the comparator is designed to increase its operating speed, it has the disadvantage of increasing power consumption.

The operating speed during the clock period can be expressed by equation (1).
However, the operating speed will be expressed by the rate of change of the output voltage _V0 .

dV ₀ /dt=-1/C _L k (g _nN + g _nP ) ΔV (1) Here, _CL is the capacitance value of the load capacitor 32, ΔV is the difference between the input voltage V _io and the reference voltage V _ref , and k is the The capacitance value of the coupling capacitor 31 is determined by the voltage division ratio of the input signal ΔV as C _C ,
Letting C _S be the parasitic capacitance due to the gate capacitance of the inverter input terminal, k=C _C /(C _C +C _S ).
g _nN and g _nP are nMOS22 and pMOS21, respectively
is the mutual conductance of

From equation (1), increasing the rate of change in the output voltage can be achieved by increasing the mutual conductance g _n . The mutual conductance g _nN of nMOS is written by equation (2).

g _nN = β _N (W/L) _N (V _GS − V _T ) ...(2) Here, β _N is the conductance constant, (W/L) _N is the ratio of the gate width W and gate length L of the transistor,
V _GS is the gate-source bias, and V _T is the threshold voltage. In the case of the comparator shown in FIG. 1, the gate-source bias voltage is set to the logic threshold voltage _VLT , so _VGS = _VLT . Therefore, in order to increase the mutual conductance, it is necessary to increase (W/L) _N . By the way, the through current during the reset period can be written as equation (3).

I=1/2β _N (W/L) _N (V _GS −V _T ) ² …(3) However, V _GS = V _LT . Therefore, in conventional comparators, when (W/L) _N is increased to increase the mutual conductance, the through current also increases, which has the disadvantage of increasing power consumption.

[Purpose of the invention]

An object of the present invention is to provide a comparator circuit with low power consumption.

[Summary of the invention]

In the present invention, the mutual conductance is (W/L)
is proportional to the effective gate bias (V _GS - V _T ), while the through current is proportional to (W/L) and proportional to the square of the effective bias (V _GS - V _T ), and (W By inventing a circuit configuration that can increase /L) and reduce the effective gate bias, we aimed to increase speed and reduce power consumption.

A chopper type comparator according to a typical embodiment of the present invention includes input means 41 and 42 for selectively applying an input voltage or a reference voltage to an input terminal 10, and a source thereof connected to a first operating potential point. , a P-channel MOS transistor 21 whose drain is connected to the output terminal 11, and an N-channel MOS transistor 22 whose source is connected to the second operating potential point and whose drain is connected to the output terminal 11. The gates of the P-channel MOS transistor 21 and the N-channel MOS transistor 22 are capacitively coupled to the input terminal 10, and the reference voltage is applied to the input terminal 10 by the input means 41 and 42. When applying the voltage, the P channel MOS transistor 21 and the N channel
It comprises means 40-1 and 40-2 for setting the gate potential of the MOS transistor 22, and when the input voltage is applied to the input terminal 10 by the input means 41 and 42, the gate potential setting means 40- A chopper type comparator that generates an output signal at the output terminal 11 by amplifying the difference between the reference voltage and the input voltage by stopping the operation of the reference voltage and the input voltage, the gate potential setting means 40-1, 40-2
sets the gate of the P-channel MOS transistor 21 to a first potential different from the first operating potential point.
a first means 40-2 for setting the potential to N;
It is characterized by comprising a second means 40-1 for setting the gate of the channel MOS transistor 22 to the potential of the second operating potential point and a second potential different from the first potential. (See Figure 2).

Therefore, in order to ensure the operating speed of the comparator, even if the mutual conductance (W/L) of the P channel and N channel MOS transistors is the same as before, the first value set by the first means 40-2 is The potential is set at a level slightly lower than the potential at the first operating potential point, and the second potential set by the second means 40-1 is set at a level slightly higher than the potential at the second operating potential point. Therefore, it is possible to significantly reduce the through current flowing through the P-channel and N-channel MOS transistors.

Furthermore, even if the first and second potentials are set to a relatively shallow bias as described above and the mutual conductance (W/L) of the P-channel and N-channel MOS transistors is increased accordingly, the through current can be kept at the same value as before. In this case, the operating speed of the comparator can be significantly improved by significantly increasing the mutual conductance (W/L).

[Embodiments of the invention]

Hereinafter, the present invention will be explained in detail with reference to Examples. FIG. 2 is a diagram showing a first embodiment of the present invention. The inverter connection of the conventional comparator was removed, a new gate bias terminal 13 of the pMOS 21 was provided, and a coupling capacitor 31-1 for inputting a signal to the pMOS 21 was provided. This circuit also operates with a two-phase clock. Switches 40-1, 40-2 and 41 are closed during the clock period φ (reset period). The gate voltage of pMOS21 becomes the gate bias voltage V _P applied to terminal 13, and
The gate voltage of the nMOS 22 is determined to a certain reset level V _R by the current flowing through the pMOS. Since switch 41 is closed, coupling capacitor 31
-1 and 31-2, charges are accumulated so that the output becomes the reset level V _R when the input terminal 10 is at the reference voltage. switch 40- in the next clock period
1, 40-2, 41 are opened to operate as an amplifier, and at the same time, switch 41 is opened and switch 42 is closed to change the input voltage from the reference voltage to the input voltage. Then, the difference between the input voltage and the reference voltage is amplified and output.

In this circuit, the output voltage V _R at reset is lower than the logic threshold V _LT . However, this will not be a problem if the level is shifted by connecting it to the next stage latch or comparator with a coupling capacitor.

In order to explain the effects of the present invention, a design method will be described that increases the speed several times while keeping the power consumption, that is, the through current, the same as that of a conventional comparator.

The operating speed of the comparator of the present invention can be expressed by equation (4).

dV ₀ /dt=-1/C _L (k _N g _nN + k _P g _nP ) ΔV (4) where k _N is the NMOS side voltage division ratio of the input signal, and k _P is the pMOS side voltage division ratio of the input signal. The sizes of the coupling capacitors 31-1 and 31-2 are C _CP , C _CN ,
The pMOS21 and nMOS gate parasitic capacitance is C _SP ,
Assuming C _SN , k _P =C _CP /C _CP +C _SP , k _N =C _CN /C _CN +C _SN . Note that the input signal voltage division ratios of the conventional comparator and the comparator of the present invention are approximately equal.

k _P =k _N =k Furthermore, the mutual conductance and through current of the comparator of the present invention can be expressed by equations (2) and (3), which are the same as those of the conventional type.

For example, if the effective bias voltage (V _GS -V _T ) and (W/L) of the comparator of the present invention are equal to the effective bias voltage (V _GS -V _T ) and (W/L) of the conventional comparator, the clock period The operating speed and through current are equal at .

Next, if the gate size (W/L) of the transistor is multiplied by x ² and the effective bias voltage is multiplied by 1/x so as not to change the through current, it can be seen from equation (2) that the mutual conductance becomes x times. If the partial pressure ratio
If k _P , k _N and load capacity C _L remain almost unchanged,
Since the operating speed during the clock period is proportional to the mutual conductance, it is multiplied by x.

The effective bias voltage is approximately 2V for a conventional 5V supply. In the comparator of the present invention, the effective bias voltage can be reduced to approximately 0.3V, ie, just below the subthreshold voltage. The effective bias voltage will be about 1/7, so ideally the operating speed during the comparator clock period should be about 7
This will allow you to double the amount.

In reality, since the transistor size (W/L) is ^doubled by x, the parasitic capacitance increases, the voltage division ratios k _P and k _N decrease, and the load capacitance also increases, so the improvement is not as good as x. Taking into account the increase in parasitic capacitance, the improvement in operating speed is calculated by 2.4 times when the gate capacitance is 2% of the coupling capacitance, 2.0 times when it is 3% of the coupling capacitance, and 2.0 times when the gate capacitance is 3% of the coupling capacitance, although the details are omitted. It is 1.6 times more effective.

Since the comparator operates with a two-phase clock, in order to improve the overall operating speed, it is necessary to increase the operating speed during the clock period and at the same time
The operating speed must also be improved.

The operating speed of the comparator of the present invention during the clock period φ is expressed by the time constant τ, as follows: τ=C _L +C _S +C _C /g _n /2 (5). However, it was assumed that g _nP = g _nN .

It can be seen that if the effective bias voltage is multiplied by 1/x, the operating speed is multiplied by x/2, unless an increase in parasitic capacitance is taken into consideration. When calculating by including the increase in parasitic capacitance, when the gate capacitance is 2% of the coupling capacitance, it is 3.6 times,
At 3%, the improvement effect is 3.0 times, and at 5%, the improvement effect is 2.4 times. Therefore, the comparator of the present invention has improved operating speed during both two-phase clock periods.

It is desirable that the performance of the comparator is high not only in speed but also in gain. Gain A can be expressed by the following equation.

A=g _n ·R _put (6) Here, R _put is the output resistance of the inverter. The output resistance of an inverter is inversely proportional to the through current. Multiply the effective gate bias by 1/x and set the gate size as
According to the above design method of multiplying x ^{by 2} , the through current is equal to that of the conventional type, so the output resistance is equal to that of the conventional type, and the mutual conductance is x times higher, so the gain is x times higher.
In other words, according to the present invention, a high speed and high gain comparator can be obtained.

Next, a second embodiment of the present invention is shown in FIG.
The connection of the coupling capacitor in the first embodiment is changed, and the same effect as in the first embodiment can be obtained.

Next, a third embodiment of the present invention is shown in FIG.
A common gate amplifier made up of transistors 23 and 24 was inserted into the inverter in the first embodiment. Terminals 15 and 16 are terminals that apply gate bias. This circuit has one amplifier stage and the same gain as two conventional amplifier stages.Compared to a conventional comparator in which two stages are connected in series, this circuit has the same gain, shorter delay time, and half the power consumption. Become a comparator.

Finally, we will discuss countermeasures against clock feed through. A problem with conventional comparators is offset errors caused by clock feedthrough, where the control clock of the reset switch 40 leaks into the signal. Therefore, reset switch 40
It was necessary to use CMOS and compensation switches to reduce the clock feedthrough that leaked into the inverter's input side to almost zero. However, there were problems such as the compensation effect changing due to the phase shift of the clock.

In the comparator of the present invention, the reset switch is divided into two, 40-1 and 40-2. Feedthrough of switch 40-1 and switch 40-2
If the polarities of the feedthroughs are opposite and the sizes are almost equal, the offset error will be small even if there is a feedthrough. Therefore, transistors with complementary polarities are used for switch 40-1 and switch 40-2.
At this time, even if the clock phase is slightly shifted, the offset error does not change much.

〔Effect of the invention〕

As explained above, according to the present invention, a low consumption comparator can be obtained.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram of a conventional comparator, Fig. 2 is a circuit diagram showing a first embodiment of the present invention, Fig. 3 is a circuit diagram showing a second embodiment, and Fig. 4 is a circuit diagram of a conventional comparator. FIG. 2 is a circuit diagram showing an example. 21, 22...Transistor constituting an inverter, 31-1, 31-2...Coupling capacitor, 40
-1, 40-2...Reset switch, 10...Comparator input terminal, 11...Comparator output terminal.

Claims (1)

[Claims] 1. An input means for selectively applying an input voltage or a reference voltage to an input terminal, and a P channel whose source is connected to a first operating potential point and whose drain is connected to an output terminal.
a MOS transistor, and an N-channel MOS transistor whose source is connected to a second operating potential point and whose drain is connected to the output terminal, the gates of the P-channel MOS transistor and the N-channel MOS transistor and the input terminal is capacitively coupled, and when the reference voltage is applied to the input terminal by the input means, means for setting the gate potential of the P channel MOS transistor and the N channel MOS transistor is provided. When the input voltage is applied to the input terminal by the input means, the operation of the gate potential setting means is stopped to generate an output signal that amplifies the difference between the reference voltage and the input voltage. It is a chopper type comparator generated at the output terminal, and the gate potential setting means is connected to the P channel.
a first switch means for connecting the gate of the MOS transistor to a gate bias potential point having a different potential from the first operating potential point; and
A chopper type comparator comprising second switch means connecting between the gate of the MOS transistor and the output terminal. 2. The drain terminal of the P-channel MOS transistor and the output terminal are connected via a source-drain path of another P-channel MOS transistor whose gate is grounded, and the drain terminal of the N-channel MOS transistor and the output terminal are connected. 2. The chopper type comparator according to claim 1, wherein the chipper type comparator is connected to the source-drain path of another N-channel MOS transistor whose gate is grounded.