JPH0263316A - Comparator - Google Patents

Abstract

PURPOSE: To simplify the configuration of the comparator by using a capacitor so as to provide a self-bias voltage to an amplifier at application of a 1st input signal and so as to store the self-bias voltage to be applied to the amplifier in the case of receiving a 2nd input signal. CONSTITUTION: A bias circuit consisting of a capacitor C1 and a switch 40 allows a bias voltage Vgps to a transistor(TR) P1 to be immune to a noise component Vn, and the bias circuit stores a self-bias voltage produced when a switch 30 is closed. When the switch 30 is open, the stored self-bias voltage is applied between gate and source electrodes of the TR P1. Thus, regardless of fluctuation in the source electrode voltage of the TR P1 due to noise, a drain current of the Tr P1 is kept constant for a period of a comparison operating time zone of the comparator. Thus, the circuit configuration is simplified.

Description

DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to comparators, and in particular to comparators using intermittent operating, self-biased transistor amplifiers that are susceptible to power supply noise. Concerning vessels.

BACKGROUND OF THE INVENTION Comparators are useful in a variety of applications where it is desired to obtain a digital representation of the relative magnitude of two (or more) analog input signals. In some applications, it is desirable for the comparator to be of a rather simple construction and to include some form of drift compensation (e.g. auto-zeroing). One type of converter is the so-called flash (parallel-simultaneous operation) type analog-to-digital converter.
A number of comparators will be used, expressed as EXP(N)-1, where N equals the number of bits of the digital signal to be converted. For an 8-bit direct (pufflash) converter, for example, 255 comparators may be required. As a practical matter, the large number of comparators makes it difficult to employ a differential amplifier with a complicated circuit configuration.

A comparator with a relatively simple circuit configuration and featuring drift compensation is disclosed in U.S. Pat.
No. 57,583 (inventor: Davis, the same inventor as the present invention). The embodiment of the analog-to-digital converter shown by Davis is such that the input signals to be compared are connected to three stages of MOS transistors (inverting).
It includes a comparator coupled alternating current (AC) to the amplifier.

Auto-zero operation can be achieved by applying the first of the two input signals to be compared to the input terminals of the amplifier via a coupling capacitor, or by simultaneously shorting the input and output terminals of the amplifier. It is done. This short circuit between the input and output terminals causes the amplifier to self-bias itself within its operating range for maximum gain and linearity, and forces the input coupling capacitor to bias the input coupling capacitor equal to the difference between the input signal voltage and the amplifier's self-bias voltage. A compensation voltage, ie an offset voltage, is accumulated.

After the automatic zero adjustment operation, the short circuit between the input and output terminals of the amplifier is removed and the first input signal is replaced with the second input signal. The offset voltage of the amplifier is stored in the coupling capacitor during the auto-zero operation period, and the same capacitor is used during the comparison operation period when coupling the second input signal. , the amplifier's offset voltage is effectively canceled, and the polarity of the amplifier's output signal thus becomes a precise indication of the relative magnitude relationship of the two input signals.

In the comparator embodiment of the Davies patent described above, the amplifier is realized by a cascade of three stages of non-complementary MOS transistor amplifiers. composed of complementary MO9 (
A method for amplification using an inverter stage (hereinafter referred to as CXOS) has already been disclosed. For an example of a multi-stage connection of self-biased CMOS inverter amplifiers in discontinuous operation, see John W. E1 & 5ons, 1988.
It is described by Gregorian et al. in Chapter 6.3 r MO9 Comparator J (pages 425-437) of the annual book "Analog MO9 Integrated Circuits for Signal Processing".

In the CMOS comparator example described by Gregorian et al., the input signals to be compared are alternately applied to the input nodes of a CMOS inverter by coupling capacitors.

The inverter includes a switch connected between an input node and an output node of the inverter, and a power supply terminal connected to a positive power supply (Vdd) and a negative power supply (Vss). During the auto-zeroing window, a reference (ground) level signal is applied to the coupling capacitor, closing the amplifier feedback switch, which self-biases the amplifier, and then bringing the coupling capacitor back to the reference (ground) level. ) and the amplifier self-bias operating point voltage. In the comparison mode of operation, the input voltages to be compared (with respect to ground level) are applied to the capacitors and the feedback switch is opened, which causes the amplification (sensing) of the difference between the input voltages at the CMOS inverter.
becomes possible.

As in the circuit configuration of the Davis patent, the accumulation of the amplifier self-bias voltage on the coupling capacitor and the comparison phase during the auto-zeroing period effectively compensates for the amplifier offset voltage and drift effects (with the exception of the comparison operation time drift is negligible during the period of the band).

<Problems to be Solved by the Invention> The present invention places major emphasis on the discovery of problems hitherto unrecognized regarding AC-coupled comparators of the type described above. , is relatively insensitive to the effects of power supply noise, whereas a comparator using a CMO9 amplifier such as the one proposed by Gregorian et al.
It was discovered that it is very sensitive to noise. This undesirable characteristic tends to prevent the use of "CMO9" type comparators in certain applications. For example, analog-to-digital converters constructed in integrated circuit form Because analog elements (eg, comparators) and digital elements (eg, clocks, gates, etc.) are present on the same semiconductor substrate, power supply noise tends to be relatively large in such converters. Since digital circuits are essentially switching devices, they tend to induce noise on the circuit's power supply line, which can interfere with the analog functions of the comparators used in the converter. could be.

5 Partly because the comparator described by Gregorian et al. has a higher sensitivity to power supply noise.

In this specification, it is interpreted that this is due to the use of a CMOS amplifier as an active gain element.

Prior art (non-complementary) amplifiers use passive load elements and are relatively insensitive to power supply noise; however, in conventionally designed CMOS amplifiers, each transistor It is true that such amplifiers, which act, so to speak, as active (amplifying) loads for other transistors, exhibit very high noise sensitivity when self-biased for use in analog applications. Prior to the invention, any variation in the supply voltage at the transistor source electrode of a self-biased CMOS inverter necessarily modulated the gate-to-source voltage of the transistor, thereby producing a variation in drain current. In comparator applications, the effect of such drain current variations is to create an offset error during self-biasing (auto-zeroing) operation, which is described herein as non-compensable. Let me explain.

To make matters worse, the noise present on the power supply line of a self-biased CXOS inverter is not just superimposed on the inverter output. It is actually
Amplified by an inverter.

In particular, in a CXOS inverter configured with multiple transistors with approximately equal transconductance values, the gain of the signal applied to one power supply input terminal is greater than the gain of the inverter with respect to the input signal applied to the inverter input terminal. is only 8 dB smaller, so the self-biased CMOS inverter
dB of gain and receives 1 millivolt of noise at one power supply terminal, the noise generated at the inverter output is 10 millivolts, or a full order of magnitude greater than the supply voltage noise. It's going to be a big deal.

If you notice a problem with noise susceptibility in a comparator using a CMO3j@I@ device (inverter), you will attempt to solve the problem by prior art methods such as filtration, shielding, lower impedance power lines. The structure of the system, etc. Alternatively, since the circuit configuration of a differential amplifier inherently exhibits a high level of power supply noise resistance, it may be considered to use the circuit configuration of the differential amplifier as is. Due to the possibility of reducing the transconductance of one transistor relative to other transistors,
Let us also consider making this transistor (1) function more as a passive load element rather than as an active amplification element of the inverter.

However, such prior art approaches to the problem of noise rejection have various drawbacks. Technologies such as filtration, shielding, and low impedance power line configurations
Often it is impractical for integrated circuit applications. The use of differential amplifiers as is is difficult in cases where a large number of comparators are required (e.g. Fuller and Schau type conversion circuits),
Techniques for reducing transconductance, which are impractical in other applications where single-circuit simplicity is desired, have the disadvantage of also reducing the amplifier gain for the input signal, thereby resulting in A circuit becomes more complex if additional amplifier stages are added to compensate for the reduced gain.

Thus, the present invention provides a comparator which has a high level of power supply noise rejection capability, overcomes the shortcomings of known comparators and outperforms the prior art of noise suppression described above, and which operates intermittently. Biased 0M
There is a need for an O5 comparator, and the present invention is directed as a primary emphasis to meeting this need.

According to the technical idea of the present invention, a device for comparing input signals includes an amplifier and an input circuit, and selectively applies the input signal to the amplifier. Generates a self-bias for the amplifier when an input signal is applied. The second bias circuit stores a self-bias for application to the amplifier upon application of the second input signal.

The above-mentioned technical idea and further developed technical idea of the present invention will be explained below with reference to the accompanying drawings. Corresponding elements in the figures have been given similar reference numerals.

<Embodiment> The comparator shown in FIG. 1 includes an amplifier 5. It includes an input circuit 6 and a timing signal generator 7. Amplifier 5 includes a pair of complementary MOs transistors P! , Nl, these transistors have two drain electrodes connected to the output terminal 4 and two source electrodes connected separately to each of the first and second voltage source terminals 1.2. The gate electrode of P-channel transistor P1 is connected to capacitor C2.
It is connected to the power supply terminal 1 via the switch 40 and connected to the #ll1lI input terminal 3 via the switch 40.

Amplifier input terminal 3 is also connected to the gate electrode of N-channel transistor Ml and further coupled to output terminal 4 via switch 30. The input circuit 6 inputs two signals to be compared, a first input signal and a second input signal (Vl,
V2) for receiving the first and second input terminals (8, 9
), the circuit 6 alternately couples two input signals v1, v2 to the input terminal 3 of the amplifier 5 by means of an input capacitor C1, the first electrode of which is connected to the input terminal 3; The second electrode of the capacitor is connected to switch 1
0.20 each to the first and second input terminals (8, 9) of the entire comparator.

The timing signal generator 7 includes a clock signal source 11, which is connected to a timing unit 12 for supplying a clock signal CL. This timing unit 12 includes switch group 10.20.3
A plurality of switch control signals St, S2, S3, and S4 are provided to separately control 0.40. Timing unit 7 is structurally suitable if it produces switch control signals having timing relationships similar in overall effect to the exemplary timing signal relationships as shown in FIG. 2 and described below. It may take any suitable form.

Regarding the operating power for the amplifier 5, the power supply terminal 2 is connected to a reference voltage with almost no noise (for example, the ground 13 as shown in Figure 1), and the power supply terminal 1 is connected to a voltage source that easily picks up noise. , which is positive with respect to the reference voltage, is supplied to the amplifier. This is illustrated as a power supply 14, which is connected to supply a positive power supply voltage Vdd having a noise component Vn to the power supply terminal l.

The condition of having a power supply that is almost unaffected by noise and a power supply that is affected by noise means that the comparator in FIG. ),
An example of an application may be found in the manufacture of integrated circuits where they share one common voltage source. Analog-to-digital converters are an example of such an application. As mentioned above, noise generated by the switching operation of digital elements may be transmitted to analog elements (comparators) via the Vdd power supply line, but generally speaking, this Vdd power supply line is ,
The amplifier 5, which has a relatively high impedance compared to the ground point in the integrated circuit and is therefore likely to pick up noise, is a conventional 0MO transistor as described above.
5 design, the presence of a power supply noise component Vn at the source electrode of the P-channel transistor P1 would cause a fluctuation in the gate-source voltage Vgsp of the P-channel transistor P1, which would cause the comparator to automatically zero. It produces variations in drain current during the adjustment window, and these variations appear in the operation of the comparator as uncompensable offset errors.

According to one aspect of the technical idea of the present invention, the bias circuit including the capacitor C2 and the switch 40 changes the bias voltage Vgsp to the transistor Pl to a noise component vn
However, this bias circuit stores and stores the self-bias voltage generated when the switch 30 is closed, and when the switch 30 is opened, a pair of voltages is applied between the gate and source electrodes of the transistor PI. This stored self-bias voltage is applied. As will be explained later, this keeps the drain current of the transistor P1 constant during the comparison operation period of the comparator, despite noise-induced fluctuations in the source electrode voltage of the transistor PI.

As will be explained in due course, regarding the operation timing of the switch 40, the power supply noise component is connected to the coupling capacitor a, which would normally cause a comparison error.
This has the additional effect of ensuring that no data is accumulated in t.

The foregoing and other features of the comparator of FIG. 1 are detailed below with reference to the timing diagram of FIG. Automatic zero adjustment operation time (auto zero) is set by switch 10.3.
It begins at time T1 with a closure of 0.40. At this point the two input signals (Vl, V2) to be compared (7
) Of which, the MI signal (vl) is connected to the input coupling capacitor C1.
is coupled to input node 3 of CMO8 amplifier 5 via . By closing the two switches 30, 40, the respective gate electrodes of the transistors P1 and N1 are connected to the two commonly connected drain electrodes of these transistors P1, N1, so that the amplifier 5 is self-isolated for linear operation. Be biased. #, two transistors pt, Nl with approximately equal transconductance and threshold voltage
With respect to If the value voltage is different from the assumed conditions, the above DC Ingredients can be determined.

The component vn of the power supply noise at the power supply terminal l is generated between the automatic zero adjustment operation time period Tl and the first partial time period Tl-72 of 〒3.
During the period, the gate-source voltage V of the transistor Pi
Change gsp. This causes a variation in the drain current of transistor P1, resulting in an amplified ACJ& component of noise being present at input node 3, along with the desired DC component of the self-bias voltage.

Therefore, during the first partial time period 〒1-〒2 of the self-bias establishment time period ↑1-T3, the input coupling capacitor C1 is connected to the input voltage v1 and the self-bias voltage (Vdd
A voltage equal to the difference between the amplified noise KVn and the amplified noise KVn will be stored therein.

The self-bias noise component is generated during the self-bias establishment time period (
During the second sub-time period (T2-T3) of TI-73), switch 40 is open, while switch 30 remains closed at that time. During this period, some significant effects appear. The first such effect is that when switch 40 opens at time 72, the self-bias voltage sampled during the Tl-72 time period is now stored in capacitor C2. The voltage stored in capacitor C2, of course, includes an incremental voltage value due to noise at the moment switch 40 opens.

However, for purposes of the present invention for biasing transistor P1, it is only necessary that capacitor C2 be charged to a value approximately equal to the DC component of the self-biasing voltage. In other words, capacitor C
Since C2 is not directly involved in comparing the two input voltages v1, v2, noise-induced errors in storing the self-bias voltage in capacitor C2 have virtually no effect. What the capacitor C2 should do is apply a constant gate-source voltage Vgs to the transistor Pi. This keeps the drain current of transistor P1 constant, thereby essentially making it ``free from noise effects''.

The second half of the automatic zero adjustment operation time period (2-3)
During the input coupling capacitor C1 is charged to a voltage equal to the difference between the input signal v1 and the now essentially "noise free" self-bias voltage produced at the input node 3. If switch 40 had not been opened during the T2-73 time period, the voltage at node 3 would contain an amplified noise component that would build up in coupling capacitor C1 upon opening switch 30. Unlike the case of bias capacitor C2, where the self-bias voltage applied will also contain a noise component, any noise component accumulated in coupling capacitor C1 will result in an uncorrectable comparison error. . The opening of switch 40 during the second half of the auto-zeroing period results in the final charge applied to capacitor C1 being
"no noise effects", thus preventing the uncorrectable comparison errors mentioned above from occurring. In other words, such an error is prevented by opening the switch 40 earlier than the opening of the switch 30.

At time 13, switch 30 is opened. Now amplifier 5
, allowing transistor N1 to perform an amplifying action with transistor PI as a load element. During the T3-74 period, there is no new signal applied to input node 3, thus allowing time for any switching transients to decay.

At time point 74, the switch 20 is closed and the switch 10 is opened, thereby changing the comparison operation time period (↑4-
75) starts. Switch 2 disconnects coupling capacitor C1 from input terminal 8 by opening switch IO.
0, the input signal v2 is transferred to the coupling capacitor C1
is introduced into input node 3 via. Recall that capacitor CI is already charged to a voltage equal to the difference between the input voltage vl and the self-bias voltage at node 3, so during the comparison operating window: When voltage v2 replaces voltage v1, the voltage at node 3 will increase relative to the self-bias voltage value if v2 is greater than vl, so that the output voltage at terminal 4 of the inverting amplifier 5 will be This decreases relative to the static operating point voltage value (Vdd/2). Conversely, if the input voltage v2 is smaller than vl, the voltage at the input node 3 decreases relative to the self-bias voltage value, and more specifically, the difference (between the input voltage v1 and the self-bias voltage) decreases. This causes the output voltage at terminal 4 to decrease in proportion to Vdd
It is amplified and increases beyond the static operating point voltage (self-bias) value of /2.

What should be noted is the latter half of the automatic zero adjustment operation time (
During period T2-73), input voltage v1 is stored in capacitor C1, capacitor C2 provides a constant bias to transistor P1, and furthermore,
During the comparison operation period (T4-75), the input signal v2 is now applied to the capacitor C1, and the above-mentioned constant bias without noise influence is also applied to the transistor P1.
This means that the noise present at the power supply terminal 1 has virtually no effect on the comparison operation.

Therefore, the presence of noise at the power supply voltage terminal 1 does not adversely affect the accuracy of the comparison operation.

At time 15 at the end of the comparison operation period, switch 20
will be opened. According to another aspect of the technical idea of the present invention, the complementary MOS transistor By implementing the switching circuit with a transmission gate, switching transients can be suppressed in the comparator of FIG. 1. This is done with each transistor transmission gate configured using an N-channel transistor for switch 30 and a P-channel transistor for switch 40, or vice versa. Alternatively, each of switch 30 and switch 40 may be implemented with a two-transistor transmission gate consisting of a pair of complementary transistors with parallel-connected conductive paths to which complementary gate control signals are applied. If the switch 30 is realized by a set of one transistor transmission gate, the switch IO is also preferably realized by a similar gate.
As a result, when both switches 30.10 are turned off (open), similar off-time transient states occur on the coupling capacitor C! is applied to the picture electrode, so that there is no change in the voltage stored thereon due to the transient condition.

According to another feature of the invention, for certain applications (e.g., high speed analog-to-digital converters), the value of bias capacitor C1 may be approximately 0.1 to 5.0 pico.
It has been found desirable to limit the range to farads.

Capacitors much larger than this preferred range are relatively difficult to integrate and require charging times that take up a significant portion of the auto-zeroing period, which makes high speed operation (e.g. 1OMHz and above) impossible. inhibit. Capacitors much smaller than this preferred range.

There may be insufficient charge duration to maintain the self-bias voltage over the entire comparison operation period, which may result in an unremarkable comparison result. A preferred value for bias capacitor C2 is approximately 1.0 picofarad. It is desirable that the coupling capacitor CI also has a value within the above-mentioned range, and preferably the bias capacitor C2
is the same value.

In a typical analog-to-digital converter application, the output at terminal 4 is detected before the end of the comparison window and stored in a latch for subsequent processing in the converter. , applied to the decoder. In precision comparator applications where detection of extremely small voltage differences is desired, prior to storing the comparison result in a latch, or storing the comparison result somewhere (e.g. in a decoder). It may be desirable to amplify the output signal of the comparator of FIG. 1 prior to use in a conventional self-biased CMOS amplifier. could be used for this purpose.

However, this is not always the case.

According to yet another aspect of the technical idea of the present invention, in applications where additional amplification is required and power supply noise is expected, the biased intermittently operated as shown in FIG. Additional amplification may be provided by cascading an additional amplifier to the comparator of FIG.

In FIG. 3, the output terminal 4' of the Ps@ device 5' is connected via an additional coupling capacitor 01' to the input terminal 3' of an additional amplifier 5' biased in discontinuous operation. Amplifier 5' is substantially equivalent to amplifier 5. Amplifier 5'
See the corresponding elements in! ! ! The numbers are shown with a prime sign. The timing signal generator 7 (not shown in FIG. 3) causes the timing of the added amplifier switch group to correspond to the timing of the comparator switch group as shown in FIG. 4. Switch 30' operates simultaneously with switch 30, and switch 40' operates simultaneously with switch 40.

The operation of the modified comparator is similar to that of the previously described comparator, except that an additional amplifier and coupling capacitor function as an additional comparator, and during the auto-zeroing period ( The self-bias voltage generated by the amplifier 5 during the second half (time T2-73) of the comparison operation period (time T4-75) is compared with the output generated by the amplifier 5 during the comparison operation time period (time T4-75). This is a point to be compared with voltage. Similar to the case of main amplifier 5, #! of the cascade connection! The width amplifier 5' eliminates power supply noise by sampling and accumulating the self-bias voltage of the bias capacitor C2', but in this case, the bias capacitor C2 is The gate-source voltage of transistor PI' is maintained constant over the entire comparison operation period.

FIG. 5 shows a modification of the comparator of FIG. 1, which also has an input terminal 51 for receiving an additional input signal v3.

Terminal 51 is connected to input node 3 of amplifier 5 via coupling capacitor c1. This modification allows comparison of any combination of input signals, and can be expanded by adding more input terminals and switches.

FIG. 6 illustrates the operation of the comparator of FIG. 5 for comparing vl and v2 and Vl and v3. This operation is the same as that previously discussed in connection with FIG. and T8-T?
) are different in certain respects. Automatic zero adjustment operation (〒1-
After 73 ), switch 20 is closed to compare v2 and vl. After this, a predetermined time delay (T5-TEI)
, the added switch 50 continues to be opened, and as a result v3
and Vt. For the comparison of V2 and vl or v2 and v3, switch 20, but not switch IO, is closed during the auto-zero operation period, and then the comparison operation is performed to compare with Vl or V3, whichever is desired. The appropriate switch (10 or 50) will be closed during the time period.

In FIG. 7, the comparator of FIG. 1 is modified so that a switch 40 is connected between the gate of transistor P1 and output terminal 4. In FIG. The operation of the comparator is substantially the same as previously described, with the difference that the variant provides a lower impedance path for charging the bias capacitor C2. In the modified circuit, the charging f4 current flows only through one switch (40), so the impedance is lower; in contrast, in the comparator before modification, it flows through two 1 switches (30, 40). The charging current flows. The lower impedance provided by the modified circuit reduces the time required to charge the bias capacitor (between time Tl-72 in FIG. 2).
Improve the speed of comparator operation.

Regarding the circuit before the change, the integrated circuit layout consists of two switches, a capacitor CI, and a transistor P1.
Arrangements in which the gates of the gates are commonly circuit-connected may be advantageous, and such applications are preferred.

FIG. 8 shows a variation of the comparator of FIG.
-Vsg).

The changes are made in the points where the power terminals 2 are connected to the ground and the Vss power supply, respectively. Since the transistor N1 is affected by noise in the voltage (Vgs) between the gate and source of the transistor N1, the capacitor C2 is connected between the gate and source terminals of the transistor N1, and the capacitor C2 is connected between the gate and source terminals of the transistor N1.
It is connected to the input node 3 via a switch 40. The operation of the modified circuit is substantially the same as that already discussed, but the difference is that the transistor 21' has a more amplifying effect on the Ms amplifier 5, and the transistor N1 has a better effect on noise. There will be no load. Note that the modified circuit is equivalent to reversing the transistor types and power-to-ground connections (as well as power supply polarity) in the circuit before modification.

To summarize the present invention, the #1 width amplifier includes an input circuit that alternately selects input signals to be compared, and a first circuit that generates a self-bias when one of the input signals is selected. It has a bias circuit. The second bias circuit stores a self-bias for use on the amplifier when the second input signal is selected to eliminate noise that may ride on the power supply voltage applied to the amplifier.

Other disclosure matters> In connection with the above description, the following items are further disclosed.

l) selectively applying input signals to an amplifier, generating a self-biasing voltage for the amplifier upon application of one of the input signals; and for application to the amplifier upon application of another of the input signals; A method of comparing multiple input signals consisting of accumulating a self-biasing voltage.

2) the process samples and holds the self-bias voltage in a capacitor during a portion of the time that the feedback is applied to the amplifier to generate the sampled self-bias voltage; 2. A method of comparing two input signals according to claim 1, comprising: applying the sampled voltage to selected transistors of the amplifier to control the characteristics of the amplifier.

3) Choose a value for the capacitor in the range of O.1 picofarads to 5.0 picofarads.

3. A method of comparing two input signals according to claim 2, further comprising the step of sequentially coupling said capacitor to a control electrode and one end of a conductive path of said selected transistor.

4) the storing step includes: providing a storage capacitor and coupling the storage capacitor to receive a chain self-bias voltage during a first portion of the first operating time period; uncoupling the storage capacitor during a second portion of the time period and throughout a second operating time period when the other of the input signals is applied to an input node of the amplifier; and further comprising sequentially coupling the storage capacitor to a control electrode of a selected transistor of the amplifier.

The one input signal is t! A method of comparing two input signals according to claim 1, wherein the two input signals are applied to an input node of the amplifier during a time period of 1IJ1.

5) during one of each of the first and second non-overlapping time periods, alternately applying the first and second input signals to the amplifier input node via a coupling capacitor to create a self-biasing voltage at the node; applying negative feedback between the input and output nodes of the chain amplifier during a first time period to expand the input node to the storage capacitor during a first portion of the first time period; applying the generated self-bias voltage at a selected one of the input node and the output node during a second portion of the first time period and during the entire period of the second time period; uncoupling the storage capacitor from a selected one of the output nodes and sequentially coupling the storage capacitor to a control electrode of a first transistor of the amplifier; How to compare input signals.

6) an amplifier; and an input circuit for selectively applying a plurality of input signals to the amplifier; and for generating a self-bias voltage for the amplifier to a bee applying one of the input signals. and a second bias circuit for accumulating the self-bias voltage for application to the amplifier while applying the other of the input signals.

7) the bias circuit includes: a sample and hold circuit having an input node coupled to receive the self-bias voltage and having an output node coupled in series to a control electrode of a selected transistor of the amplifier; and a timing circuit coupled to the sample and hold circuit for causing the core sample and hold circuit to sample the self-bias voltage for a portion of the time period upon application of one of the input signals. Comparator described in item 6.

8) the bias circuit includes a capacitor coupled between a control electrode and one end of a conductive path of a selected transistor of the amplifier; and a capacitor coupled between the control electrode of the selected transistor and an input node and an output node of the amplifier. The comparator according to appendix 6, comprising: a switch connected between the selected one of the two.

9) the amplifier includes a selected transistor for receiving the self-biasing voltage; the selected transistor is a field effect transistor having a source electrode and a drain electrode; and the biasing circuit includes a selected transistor having a source electrode and a drain electrode. 7. A comparator according to claim 6, comprising a capacitor connected to a gate electrode and a switch connected between the gate electrode and a selected one of an input node and an output node of the amplifier.

10) , the additional capacitor has a capacitance value ranging from 0.1 pico Farad to 5.0 pico Farad,
Comparator as described in Supplementary Note 9.

11) an amplifier having an input node and an output node;
and a second non-overlapping time period to the input node of the amplifier via a coupling capacitor to the first
and an input circuit for alternately applying a second input signal.

To develop a self-bias voltage at the node,
a feedback circuit for providing negative feedback between the input node and the output node of the amplifier during the first time period; a bias circuit configuration responsive during the il portion of the first time period to store the self-bias voltage generated in the amplifier; A circuit path coupled for continuous application to a control electrode of a selected transistor.

A comparator for comparing a first input signal and a second input signal provided therein.

12) Input terminal, output terminal, first power supply terminal, second
a first and second complementary MOS transistor having a drain electrode connected to the output terminal and a source electrode connected to each one of the power supply terminals; and a first capacitor. the first transistor having a gate electrode coupled to the first power supply terminal via a gate electrode and to a selected one of the input terminal and the output terminal via a first switch; the input terminal further connected to the gate electrode of the second transistor and coupled via a second switch of the output terminal; and a timing signal generator coupled to the switch for controlling operation. A combination consisting of , .

13) The timing unit is configured to sequentially close two switches during a first operating period, close one switch and open the other switch during a second operating period. 13. The combination according to claim 12, wherein a control signal is generated and this signal is applied to both switches to open them during the operating period of 3.

14) The combination according to appendix 12, wherein the MA capacitor has a value in the range of 0.1 pico farads and 5.0 pico farads.

15) The combination according to appendix 12, further comprising an input circuit for alternately applying a first input signal and a second input signal to the input terminal of the amplifier via a coupling capacitor.

16) a first node having an input node and a control electrode connected to the input node and a conductive path connected between the output node and a reference potential source;
a second transistor having a conductive path connected between the output node and a supply voltage source; a first transistor for connecting the input node to the output node and a control electrode of the second transistor; and a switching circuit having a second mode of operation for decoupling the input node from the output node and from the control electrode of the second transistor.

17) responsive during the first mode of operation of the switching circuit for applying a first input signal to the input node; and for applying a second input signal to the input node of the switching circuit; 17. The amplifier of claim 16, further comprising an input circuit responsive during the second mode of operation of the switching.

18) The switching circuit includes a first switch connected between the input node and the output node, and a second switch connected between the input node and the control electrode of the second transistor. and the amplifier further.

a first mode of operation coupled to the node and the switch for closing both switches and applying the input signal to the input node; 17. The amplifier of claim 16, further comprising a control circuit having a second mode of operation in which the input signal is not applied, thereby causing an output signal indicative of the relative amount of the input signal to be generated at the output node.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a partial block diagram of a CMO9 comparator according to an embodiment of the present invention. FIG. 2 is a timing diagram illustrating aspects of the operation of the comparator of FIG. FIG. 3 is a circuit diagram illustrating a variation of the comparator of FIG. 1, in which the gain and noise rejection capabilities of the comparator are enhanced. 4 is a timing diagram illustrating aspects of the operation of the comparator of FIG. 3; FIG. FIG. 5 is a circuit diagram illustrating a comparator that is a variation of the comparator of FIG. 1 and is capable of comparing multiple input signals. FIG. 6 is a timing diagram illustrating the operation of the comparator of FIG. FIG. 7 is a circuit diagram illustrating a variation of the comparator of FIG. 1, having an alternative switch-connected configuration. FIG. 8 is a circuit diagram illustrating a variation of the comparator of FIG. 1, operating from a negative power supply. Similar reference numerals are given to similar elements in the figures, and the numerals represent the following: 1.2. ,,,First and second power supply terminals 3...Input terminal 4 to the amplifier ,,,,,
, Output terminal 5 , Amplifier 6 , Input circuit 7 , Timing signal generator 8.9.5
1. ,,,input terminal l0120.30.40.30', 40', 50.
,,,Switch F/'g. Fig. Procedural amendment (method) % formula % Name of invention comparator 3 Relationship with the case of the person making the amendment Patent applicant address North Central Expressway, Dallas, Texas, USA 135004 Proxy address 150 K (03) 4964420 Tokyo 1-20-2 Dogenzaka, Shibuya-ku Target of date correction of amendment order August 14, 1999 (shipped August 29, 1999) Drawings (engraving of all drawings)

Claims (1)

[Claims] An amplifier, an input circuit for selectively applying first and second input signals to the amplifier, and a first circuit for generating a self-bias voltage in the amplifier when the first input signal is applied. A comparator comprising: a bias circuit; and a second bias circuit that stores a self-bias voltage for applying to the amplifier when a second input signal is applied.