JPH03259496A - Output circuit - Google Patents

Abstract

PURPOSE:To prevent a tentative large current from being supplied even at a transient period when each output transistor (TR) turns from OFF to ON by using a constant current bias means so as to make a bias of each output TR constant so as to make constant current operation. CONSTITUTION:A source of a FET (Field effect transistor) 7 is connected to a drain of a FET 8. The FET 8 is an NMOS (N-channel metal oxide semiconductor) FET and its source is grounded and its gate is connected to a source of a FET 9 and also connected to a drain and a gate of a FET 10 respectively. The FETs 8, 9, 10 constitute a constant current bias means and a constant current bias circuit comprising the FETs 9, 10 is used to set a current flowing through the FET 8 constant thereby acting the FET 7 like a constant current operation. Thus, no tentative large current is supplied even at a transient period when the output TRs 5,7 are turned off to on.

Description

[Detailed Description of the Invention] "Industrial Application Field" This invention relates to an output circuit that is built into a memory or the like and is composed of a plurality of output transistors, and particularly relates to an output circuit that is built in a memory or the like and is composed of a plurality of output transistors. The present invention relates to an output circuit that suppresses noise generation.

"Prior Art" FIG. 2 is a circuit diagram showing an example of an output circuit comprised of a plurality of output transistors built into a memory (eg, RAM, random access memory) or the like.

In this figure, 1 is a NOR gate, and its first input terminal is connected to the first input terminal of a NAND gate 3 via an input terminal 2 (L). Further, its second input terminal is connected to the second input terminal of the Nant gate 3, and its output terminal is connected to the input terminal FE T (field eff
ect transistor) 5. The output terminal of the Nant gate 3 is connected to the inverter 6.
It is connected to the gate of FET7 via. Above F'
A power supply voltage V0 is applied to the drain of the ET 5, and its source is commonly connected to the drain of the FET 7. The output signal Po is then taken out from this common connection portion. The source of FET' 7 is grounded. Note that the above FET 5 is a PMOS (P
The FET 7 is of the NMOS (N-channel metal oxide semiconductor) type.

In the output circuit having the above configuration, an OE (output enable) signal of "L" level is applied to the first input terminal of the NOR gate 1 and the first input terminal of the NAND gate 3 via the inverter 2. , when the level of the I signal applied to the second input terminal of each of the NOR gate 1 and the NAND gate 3 changes from "L" to "H", the level of the output signal Po changes from "H" to "L".

"Problem to be Solved by the Invention" By the way, in the conventional output circuit described above, in order to increase the speed of the circuit, the channel width of F'ET 7 must be increased to a certain extent, otherwise the output signal end and the ground will be connected. It is not possible to deal with the load including the parasitic capacitance that occurs between the two. However, if the channel width is increased to a certain extent, a large current corresponding to the capacity of the FET 7 will flow at the same time that the FET 7 is turned on during the transition period. A problem arises when the ground level fluctuates, causing noise and causing other circuits to malfunction.

This invention was made in view of the above-mentioned circumstances, so FE
The purpose of this invention is to provide an output circuit in which a large current does not flow temporarily during the transition period when T7 is turned on from off.

"Means for Solving the Problem" The present invention is characterized in that, in an output circuit constituted by a plurality of output transistors, a constant current bias means is provided for operating at a constant current while keeping the bias of each of the output transistors constant. .

"Operation" According to the configuration of the present invention, since the bias of each output transistor is kept constant by the constant current bias means and constant current operation is performed, even in the transition period when each output transistor is turned on from off, there is no temporary effect. A large current does not flow through the

Therefore, there is almost no variation in the ground level caused by the flow of a large current, so almost no noise is generated and there is almost no influence on other circuits.

"Embodiments" Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing the configuration of an output circuit according to an embodiment of the present invention. In this figure, parts common to those in FIG. 2 described above are designated by the same reference numerals, and the explanation thereof will be omitted.

In this figure, the source of FET 7 is connected to the drain of FET 8. FET 8 is NMOS type FE
Its source is grounded, its gate is connected to the source of FET 9, and connected to the drain and gate of FET 10, respectively. FET 9 is a PMOS type FET, and the power supply voltage V is applied to its drain. is applied and the gate is grounded. On the other hand, the FET 1O mentioned above is an NMOS type FET, and its source is grounded. These FETs 9 and 10 constitute a constant current bias circuit.

Here, the channel width of FETl0 is W. , the channel length is Ll. , the flowing current is ■1°, the channel width of FET8 is W8, and the channel length is L8, then this FET
The current I8 flowing through 8 is Ws L+n ■・-1soo'Le”・・W8 L I.

=kl,. , (k-wlo-LIl), and F
The value is proportional to the current 1+o flowing through ET 10. Therefore, by changing the proportionality constant k shown in the above equation,
The current I6 can be maintained at a desired constant value. As a result, even if the channel width of the FET 7 is widened to increase the speed of the circuit, a current corresponding to the capacity of the FET 7 will not flow when the EFT 7 is turned on from off during the transition period. Therefore, fluctuations in the ground level are less likely to occur, and almost no noise is generated.

In this way, by setting the current (2) flowing through the FET 8 to a constant value by the constant current bias circuit composed of the FETs 9 and 10, the FET 7 can be operated at a constant current.

In addition, in the above embodiment, a PMOS type was used as the FET 9, but an NMOS type may also be used. However, in this case, the bias should be the power supply instead of the ground.

"Effects of the Invention" As explained above, according to the output circuit according to the present invention,
Since the constant current bias means keeps the bias of each output transistor constant and causes them to operate at a constant current, no large current temporarily flows even during the transition period when each output transistor changes from off to on. Therefore, fluctuations in the ground level during the transition period are less likely to occur, and almost no noise is generated, so that this noise has almost no influence on other circuits.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing the configuration of an output circuit according to an embodiment of the present invention, and FIG. 2 is a circuit diagram showing the configuration of a conventional output circuit. 5.9...PMOS type FET. 7.8.9...NMOS type FET (8,9,
10 constitutes constant current bias means). Figure 2

Claims (1)

[Claims] 1. An output circuit comprising a plurality of output transistors, characterized in that the output circuit comprises a constant current bias means for causing each of the output transistors to operate at a constant current with a constant bias.