JPH01289319A - Current source circuit and digital/analog converter using it - Google Patents

Abstract

PURPOSE:To guarantee the operation with high reliability as a current source circuit, to reduce the production of glitch considerably simultaneously and to attain high speed operation by fixing a gate of a transistor(TR) connected to a load by a DC bias of a prescribed potential. CONSTITUTION:A source of the 1st MIS TR Q11 is connected to the 1st power supply line Vss of a prescribed potential, and sources of the 2nd and 3rd MIS TRs Q12-13 are connected to a drain of the 1st MIS TR Q11. A drain of the 2nd MIS TR Q12 is connected to the 2nd power supply line Vcc of a prescribed potential different from the 1st power supply line, a drain of the 3rd MIS TR Q13 is connected to an output terminal OUT, a digital input data is applied to th gate of the 2nd MIS TR Q12 to give 1 prescribed current to a load LD connected to the output terminal. Thus, the operation with high reliability is obtained as the current source circuit and production of glitch is reduced remarkably to speed up the operation.

Description

[Detailed Description of the Invention] [Summary] The present invention aims to improve operational reliability and enable high-speed operation with respect to the configuration of current source circuits, particularly current source circuits used in current output type D/A converters. A first MIS transistor as a current source that operates under a predetermined DC bias, and a second MIS transistor having a channel of the same conductivity type as that of the first MIS transistor.
and a third MIS transistor having a channel of the same conductivity type as the first MIS transistor and having a gate fixed at a DC bias of a predetermined potential, and a source of the first MIS transistor has a channel of the same conductivity type as the first MIS transistor. the second and third M
The source of the IS transistor is connected to the drain of the first MIS transistor, the drain of the second MIS transistor is connected to a second power line having a predetermined potential different from the first power line, and the 30th Ml5 transistor The drain of the second MIS is connected to the output terminal, and the drain of the second MIS
Digital input data is applied to the gate of the transistor to cause a predetermined current to flow through a load connected to the output jli.

[Industrial application field]

The present invention relates to a current source circuit, and particularly to the configuration of a current source circuit used in a current output type digital-to-analog converter (hereinafter referred to as a D/A converter).

[Conventional technology]

D/A converters are broadly classified into current output types such as current addition type and current switching type, and voltage output types such as voltage addition type and voltage switching type. Current output type D/A whose output appears in the form of current
Converters are often used.

FIG. 9 schematically shows a configuration example of a typical current output type D/A converter. In the same figure, 11, I2, I
3,..., indicate current sources, SW, , SW2, S
W3, . . . indicate switches that are turned on and off in response to the level of each corresponding bit of binary digital input data. Each current source ring and corresponding switch constitute a current source circuit. In the configuration of FIG. 9, for example, when the switch SW+ is closed, the corresponding current source! , appears at the output terminal OUT. In other words, an amount of current corresponding to the input digital signal appears at the output terminal OUT as an analog amount, and D/A conversion is performed.

FIG. 1O shows a circuit configuration of a current source circuit as an example of a conventional type. The example in the figure shows the configuration of one bit of digital input data.

In the figure, Ω1 represents an n-channel metal-oxide-semiconductor (MOS) transistor, more broadly a metal-insulator-semiconductor (MIS) transistor, as a current source, whose source is a power supply line vss at a predetermined potential. (“L”
A predetermined DC bias VB is applied to the gate so that the transistor Q1 is always on. Therefore, the level of node N1 is Vss
The potential is fixed to be higher than the potential by the threshold level (Vth) of transistor 01 (approximately 2 V). Q2 is an n-channel MO3 transistor,
Its source is connected to the drain of transistor Q1,
The drain is connected to another power supply line Vcc (“H”) at a predetermined potential.
level). Digital data DIl+ is applied to the gate of transistor Q2. Mouth 3
is an n-channel MO3 transistor, whose source is connected to the drain of the transistor Q1, and whose drain, that is, the output terminal OUT, is connected to the power supply line V via the load LD.
connected to cc. The gate of the transistor Q3 receives data D1. l is applied via the inverter INV.

Note that the transistor Q1 is the current source 1. in FIG. ,I2,
Corresponding to I3,..., transistors Q2 and Q3
is switch 5i11. , SW2, SL,...
corresponds to

Assume now that the Vcc (7) potential is 5V, and the VSSO) potential is OV1, and the potential of the node Nl is 2V.

According to the circuit configuration of FIG. 10, data 0111 is “H”
When the level is low, transistor 02 is turned on, and on the other hand, the gate of transistor Q3 is connected through inverter 1 to
Since the level data is applied, the transistor Q3 is in a cut-off state. At this time, no current flows through the load LD. Furthermore, when the data DI11 is "L level", the transistor Q2 is in the cut-off state, and the transistor Q2 is in the cut-off state.
Since "H" level data is applied to the gate of transistor Q3, the transistor Q3 is turned on. by this,
A predetermined current flows through the load LD. In other words, by alternately turning on and off transistors Q2 and Q3 in response to data DIN, a predetermined current is supplied to load LD! . is flowing.

However, according to the circuit configuration of FIG. 10, as shown in FIG. 11, the data DIN changes from "H" level to I1.
1" level, that is, when the transistor Q3 transitions from the cut-off state (the gate-source voltage is -5V) to the on-state (the gate-source voltage is +3V), the voltage between the gate and source of the transistor Q3 and A "glitch" due to clock feedthrough occurs due to the capacitive coupling of parasitic capacitance between the gate and drain and the magnitude of the change in the gate-source voltage. That is, the predetermined current I.

A problem arises in that a larger current flows transiently (indicated by the broken line G in FIG. 11), resulting in unstable operation.

The first example of a circuit configuration proposed to deal with this problem is
This is shown in Figure 2.

The feature of this circuit is that the transistor Q connected to the load side
6 is fixed at a constant voltage Vcc without depending on data D11l, and data 01
11 is of the p-channel type. On the right, the level of node N2 is lower than the potential of Vss, as in the case of FIG.
The voltage is fixed at a higher potential (approximately 2V) by vthO.

According to the circuit configuration of FIG. 12, data 0111 is “L”
When it is at level, transistor 05 is turned on and the potential of node N2, that is, the source potential of transistor 06, is raised from 2V to 5V, and the same voltage of 5V as the source potential is applied to the gate of transistor Q6. The transistor 6 is in a cut-off state. At this time, no current flows through the load LD. On the other hand, data DI
When N is at the "H" level, transistor 05 is cut off and the potential of node N2 returns to the original 2V, and since a voltage of 5V is applied to the gate of transistor Q6, transistor Q6 is in an on state. becomes. As a result, a predetermined current flows through the load LD.

In this manner, in the circuit configuration shown in FIG. 12, the transistor Ω6 connected to the load side is turned on and off in response to changes in its source potential. Therefore, when the data DIN changes from the "L" level to the "H" level, that is, the transistor Q6 shifts from the cut-off state (gate-source voltage is OV) to the on-state (gate-source voltage is +3V). Considering the time point, the magnitude of the change in gate-source voltage (3V) is smaller than that in the case of Fig. 10 (8V), so the parasitic capacitance between the gate-source and gate-drain of transistor 06 is Charge leakage caused by capacitive coupling is suppressed.

In other words, it has a circuit configuration that is effective against glitches.

[Problem to be solved by the invention]

According to the conventional configuration described above (FIG. 12), the gate of the transistor Q6 connected to the load side is connected to a constant voltage Vc.
By fixing it to c, the occurrence of glitches is reduced, but on the other hand, the following problems occur.

Considering the time when the transistor RO 6 is in the on state, the potential of the output terminal 0[IT, that is, the drain potential, becomes a level lower than the potential of Vcc by the voltage drop of the load LD. At this time, if the drain potential drops to a level below the level (Vcc-Vth), which is lower than the gate potential (Vcc) by the amount of vth, the current will flow toward the output end, resulting in a cut-off state. A problem arises in that the transistor Q6 that is supposed to be turned on may turn on depending on the situation. In other words, the problem arises that the on/off operation of the transistor 06 becomes uncertain, and the reliability of its operation as a current source decreases.

Also, the change due to the OUT terminal voltage is the V of the current source transistor Q4. , changes in RDS, etc., making it difficult to stably maintain the output current at a predetermined value. Therefore, it is necessary to use a transistor with a long gate length as the current source transistor 04 so that the output current is not so affected by changes in the drain potential.

However, when a transistor with a long gate length is formed on a chip, the area of the transistor cell becomes large.
Naturally, the parasitic capacitance between the gate and source and between the gate and drain also increases. When the parasitic capacitance becomes large, it takes a long time to charge and discharge the charge to the container, which causes a problem that high-speed operation cannot be realized.

Furthermore, a p-channel transistor Q is used as a switch.
5 and an n-channel transistor Q6, for example, if a p-type substrate is used, an n-type well must be provided in the p-type substrate in order to form the p-channel transistor Q5. This is not preferable because the cell area becomes larger than when two transistors of the same conductivity type channel are formed.

The present invention was created in view of the above-mentioned problems in the prior art, and aims to provide a current source circuit that improves operational reliability and enables high-speed operation, and a D/A converter using the same. There is.

[Means and operations for solving the problem] The problem with the conventional technology described above is that when one transistor not connected to a load is in an on state, the other transistor connected to a load is in an off state. and by fixing the gate of the other transistor with a DC bias of a predetermined potential so that when the one transistor is in the off state, the other transistor remains in the on state. .

Therefore, according to one embodiment of the present invention, a 10th Ml5 transistor as a current source that operates in response to a predetermined DC bias, and a second MIS transistor having a channel of the same conductivity type as the first MIS transistor. , a third MIS transistor having a channel of the same conductivity type as the first MIS transistor, and having a gate fixed at a DC bias of a predetermined potential.
the first MIS transistor;
The source of the S transistor is connected to a first power supply line at a predetermined potential, the sources of the second and third MIS transistors are connected to the drain of the first MIS transistor, and the drain of the second MIS transistor is The third MIS transistor is connected to a second power supply line having a predetermined potential different from the first power supply line, the drain of the third MIS transistor is connected to the output terminal, and digital input data is applied to the gate of the second MIS transistor. , there is provided a current source circuit characterized in that a predetermined current is caused to flow through a load connected to the output terminal.

A DC bias of a predetermined potential to be applied to the gate of the third transistor is determined as follows.

Assume now that the conductivity types of the channels of the first, second, and third transistors are n-type.

In this configuration, when the digital input data is at the "BI" level, the second transistor is in the OFF state, and therefore the third transistor is in the ON state, so that a predetermined current (I ) needs to be streamed. The conditions are: ■=β(VG-v,-vth)”/2−−−−−−−−
−■ holds true. However, β, V, and VsSV□ are the current amplification factor and gate potential (
DC bias), source potential, and threshold level.

On the other hand, when the digital input data is at the ``H'' level, the second transistor is in the on state, and therefore the third transistor is in the off state, so the predetermined current ■ must not flow through the output terminal. .The conditions are: ■=β(-v,-vth)2/2...
...■ holds true.

Since β and VLh are constants, from the formulas ■ and ■, the gate potential (DC bias) VG and the source potential V1
All you have to do is decide. This ensures highly reliable operation as a current source circuit. On the other hand, since the gate of the third transistor is fixed at a DC bias VG of a predetermined potential, the occurrence of glitches is significantly reduced, thereby increasing the speed of operation.

Further, in a preferred embodiment of the present invention, a fourth MIS transistor may be provided in series with the first transistor as a current source. In this way, the so-called "two-level stacking"
By adopting a transistor configuration, the cell area is reduced isometrically and the parasitic capacitance of the transistor is reduced.
High-speed operation can be further promoted. Details will be explained using examples described later with reference to the accompanying drawings.

Furthermore, according to another aspect of the present invention, a plurality of the above-mentioned current source circuits are provided, and a predetermined DC bias is applied to each gate of the first MIS transistor and the third MIS transistor in each current source circuit. a bias circuit for applying each bit of the digital input signal to the gate of the second MIS transistor in each current source circuit;
A digital-to-analog converter is provided, characterized in that an amount of current corresponding to the digital input signal is taken out as an analog amount from an output end.

Note that other structural features and details of the operation of the present invention will be explained using the embodiments described below with reference to the accompanying drawings.

〔Example〕

FIG. 1 shows the circuit configuration of a current source circuit as an embodiment of the present invention. The illustration in the figure is for simplification of explanation.
The configuration of one bit of digital input data is shown.

In FIG. 1, Q11 is an n-channel MO3 transistor as a current source, and its source is connected to the low-level power supply line vSS (voltage is OV), and its gate is connected so that the transistor Q11 is always on. A predetermined DC bias V11 is applied. Q12 is an n-channel type MO3 transistor, and its source is connected to the drain of transistor Q11, and its drain is connected to a high-level power supply line Vcc (voltage is 5V).

Digital input data D! is input to the gate of transistor Q12. is applied. Q13 is n-channel type MO3
a transistor, the source of which is a transistor Q1
1, and the drain, that is, the output terminal 0υ
The terminal is connected to the power supply line Vcc via the load LD. A DC bias v1□ of a predetermined potential is applied to the gate of the transistor Q13.

The magnitude of this DC bias VI□ and the transistor Q13
The source potential of is determined from the equations (1) and (2) described above. In this case, Vcc (51/)>V, □
It goes without saying that there is a relationship of >source potential>Vss (OV).

In this way, by appropriately setting the magnitude of V12 and the source potential, the digital input data DI)1 becomes
When the data DIN is at the HII level, the transistor 012 is turned on and the source potential of the transistor 013 rises to the "H" level, thereby turning the transistor Q13 into a cut-off state.On the other hand, when the data DIN is at the "L" level, the transistor Q12 is turned on. is cut off, the transistor 13 is turned on, and a predetermined current flows through the load LD. At this time, the output terminal O
Although the potential of UT becomes lower than the potential of Vcc due to the voltage drop of the load, since the magnitude of v,2 is set to satisfy the above-mentioned conditions, the on state of transistor Q13 is reliably maintained. . As a result, highly reliable operation as a current source circuit can be obtained, and since the gate of the transistor Ω13 is fixed at a predetermined DC bias vl□, the occurrence of glitches can be greatly reduced. This leads to faster operation.

FIG. 2 shows a circuit configuration of a modification of the embodiment shown in FIG. In the example shown in FIG. 1, p
Channel type MO3 transistor Q21, Q22, Ω23
This shows the case configured by

The mode of operation, the magnitude of the DC bias v2□, and the method for determining the source potential of the transistor 023 are the same as in the embodiment of FIG. 1, and therefore their explanation will be omitted. However, in this case, when the data Dl is at the "L" level, the transistor Q23 is cut off, and when the data DIN is at the 'H' level, the transistor Q23 is turned on, and a predetermined current flows through the load LD.

FIG. 3 shows a circuit configuration of a current source circuit as another embodiment of the present invention.

In the configuration of the embodiment shown in FIG.
33, and as a structural feature of this embodiment, an n-channel transistor Ω34, which receives a predetermined DC bias v3□ and operates as a current source, is connected between the drain of the transistor Q31 and the sources of the transistors Q32 and 033. It is set in.

In this way, by adopting a two-stage transistor configuration as a current source, the cell area can be reduced isometrically and the parasitic capacitance of the transistor can be reduced, thereby increasing the operating speed of the circuit shown in Figure 1. It can be further accelerated. The reason for this is explained below in Figure 4(a).
This will be explained with reference to FIG. 5(b) and FIGS. 5(a) and 5(b).

Figures 4(a) and (b) respectively show the configuration of a single transistor used as a current source and its equivalent circuit, and Figures 5(a) and (b) respectively show a two-stage transistor used as a current source. The structure of a stacked transistor and its equivalent circuit are shown. In this case, for a single transistor, the drain voltage V. The rate of change in the output current I0 with respect to the change in is dIo/dVo = l/ro...
・・・・・・・・・・・・・・・・・・・・・(1) On the other hand, for a two-stage stacked transistor, dlo/dVo= 1/ (g-・ro-ro) −
−(2). However, g represents the transfer conductance of the transistor. Also, the output current I0 is ■=
β((VG −vth) −v.

-vo” /2)・・・・・・・・・・・・・・・・
...It is expressed as (3). Here, β is β=W・μ・ε. Ya/ (L -t,,)...
...It is expressed as (4). Here, W is the gate width, L is the gate length, μ is the carrier mobility, and ε. 8 represents the dielectric constant of the gate insulating film, and tOwl represents the thickness of the gate insulating film.

As is clear from the above equations (1) to (4), linearity is guaranteed even if the gate length of the two-stage stacked transistor is shorter than that of a single transistor. This means that if the same current is passed through a transistor, if the gate length becomes 1/n, the gate width will also become 1/n, and the area of the channel region will become 1/n2. .

Returning to FIG. 3, in this embodiment, among the two-stage transistors 031 and Ω34 as current sources, the transistor Q34, which is closer to the switching transistor Q33, has a smaller channel region than the other transistor Q31. It is formed small. - In general, many parasitic capacitances such as junction capacitances are formed in transistors, but if the capacitances are charged and discharged, it becomes disadvantageous in terms of operating speed. Therefore, in this embodiment, the cell size (channel region) of the transistor Q34 connected to the source potential v2 of the switching transistor Q33, which has a large voltage change compared to the change in the potential v1 at the connection point between the transistors Q31 and Ω34, is formed small. This reduces the amount of charging and discharging to the parasitic capacitance and enables high-speed operation.

FIG. 6 shows a circuit configuration of a modification of the embodiment shown in FIG. In the example shown in FIG.
62, Ω63, and Ω64.

Its operating mode, the method for determining the magnitude and source potential of the DC bias v63 of the transistor Q63 connected to the load, and the channel area of the transistor Q64 closer to the switching transistor Q63 compared to that of the other transistor 061. Since the formation of a small size is the same as that of the embodiment shown in FIG. 1, the explanation thereof will be omitted.

However, in this case, as shown in FIG. 7, when the data DIN is at the "H" level, the transistor Q62 is in the γ-off state, and the potential of the node NN is at the "H" level, so the transistor Ω63 is turned on. , a predetermined current ■ to the load LD. is flowing. When the data DIN changes to the "L" level, the transistor Q62 is turned on and the potential of the node NN drops to the "L" level, thereby cutting off the transistor Q63 and stopping the flow of the current I.

FIG. 8 shows an example of the configuration of a D/A converter using the current source circuit of FIG. 6.

In the figure, I81 to lSo are current source circuits shown in FIG. 6, and VC is a bias circuit, and a predetermined DC bias V is applied to each gate of transistor Q61, transistor Q64, and transistor Q63 of each current source circuit. @l, V11□, v6. It has the function of supplying According to the D/A converter of FIG. 8, the corresponding transistor Q62 in each current source circuit turns on and off in response to each bit data of the digital input signal DIM, so that the corresponding transistor Q62 in each current source circuit A predetermined current is taken to the output terminal OUT via the transistor Q63. In other words, an amount of current corresponding to the input digital signal DIN is output as an analog amount to the output terminal 0.
[Appears in IT and performs D/A conversion.

〔Effect of the invention〕

As explained above, according to the present invention, by fixing the gate of the transistor connected to the load with a DC bias of a predetermined potential, highly reliable operation as a current source circuit can be guaranteed, and at the same time, It is possible to significantly reduce the occurrence of glitches and speed up the operation.

Furthermore, when a two-stage stacked transistor configuration is adopted as the current source, the cell area can be reduced isometrically, thereby reducing the parasitic capacitance of the transistor and further promoting high-speed operation.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing the configuration of a current source circuit as an embodiment of the present invention, FIG. 2 is a circuit diagram of a modification of the embodiment of FIG. 1, and FIG. 3 is a circuit diagram of a modification of the embodiment of the present invention. 4(a) and (b) are diagrams showing the configuration of a single transistor used as a current source and its equivalent circuit, and FIG. 5(a) and (b) are diagrams showing the configuration of a current source circuit. 2 used as a current source
Diagrams showing the configuration of stacked transistors and their equivalent circuits; FIG. 6 is a circuit diagram of a modification of the embodiment in FIG. 3; FIG.
Figure 8 is a circuit diagram showing an example of the configuration of a D/A converter using the current source circuit of Figure 6. Figure 9 is a typical current output type D/A converter. FIG. 10 is a circuit diagram showing the configuration of a current source circuit as an example of a conventional type. FIG. 11 is an operating waveform diagram of the circuit shown in FIG. 10. FIG. 12 is a conventional circuit diagram. FIG. 2 is a circuit diagram showing the configuration of a current source circuit as another example of the current source circuit. (Explanation of symbols) Q11, Ω21. Ω31. Ω61...first M
IS transistor, Ω12, Q22. Ω32. Ω62
...Second MIS transistor, Ω13. Ω23.
Ω33. Ω63...30th Ml5 transistor,
Ω34. Ω64...Fourth MIS transistor, 0
111...Digital input data, LD...Load, Vcc, Vss...Power line, OUT...Output terminal, V11+ V121 V21+ v221 V31+
V321 V3j+Vf11+Vli□, v63...
Predetermined DC bias, IS, ~■S1... current source circuit, VC... bias circuit.

Claims (1)

[Claims] 1. Predetermined DC bias (V_1_1, V_2_1; V
The first MIS transistor (Q11, Q21, Q31) as a current source that operates in response to
, Q61) and a second MIS transistor (Q1
2, Q22, Q32, Q62), and has a channel of the same conductivity type as the first MIS transistor, and has a gate with a DC bias (V_1_2) at a predetermined potential.
, V_2_2; V_3_3, V_6_3).
Q63), and the source of the first MIS transistor is connected to the first power supply line (Vss, Vcc) at a predetermined potential.
), the sources of the second and third MIS transistors are connected to the drains of the first MIS transistors, and the drains of the second MIS transistors are connected to the drain of the third MIS transistor is connected to the output terminal (OUT), and the digital input data (D_I_N) is applied to the gate of the second MIS transistor; A current source circuit characterized in that a predetermined current is caused to flow through a load (LD) connected to the output terminal. 2. It further includes a fourth MIS transistor (Q34, Q64) as a current source that operates in response to a predetermined DC bias (V_3_2, V_6_2), and the fourth MIS transistor
The transistor is connected between the first MIS transistor and the second and third MIS transistors, has a channel of the same conductivity type as the first MIS transistor, and has a channel of the same conductivity type as the first MIS transistor. 2. The current source circuit according to claim 1, wherein the channel region is formed small. 3. A plurality of current source circuits according to claim 1 (IS_i to I
S_n), the first MIS transistor and the third MIS transistor in each current source circuit
a bias circuit (VC) that supplies a predetermined DC bias to each gate of the second MIS transistor in each current source circuit, and applies each bit of the digital input signal to the gate of the second MIS transistor in each current source circuit, A digital-to-analog converter characterized in that an amount of current corresponding to the digital input signal is taken out as an analog amount from an output terminal (OUT).