JPH0787374B2 - Current source circuit and digital / analog converter using the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] Regarding the configuration of a current source circuit, in particular, a current source circuit used in a current output type D / A converter, it is necessary to improve the operation reliability and enable high-speed operation. For the purpose, a first MIS transistor as a current source which operates by receiving a predetermined DC bias, a second MIS transistor having a channel of the same conductivity type as the first MIS transistor, and a first MIS transistor Between a third MIS transistor having channels of the same conductivity type and having a gate fixed by a DC bias of a predetermined potential, and between the drain of the first MIS transistor and the sources of the second and third MIS transistors. Has a channel of the same conductivity type as that of the first MIS transistor, has a channel region smaller than that of the first MIS transistor, and receives a predetermined DC bias. A fourth MIS transistor functioning as a current source, the source of the first MIS transistor is connected to the first power supply line of a predetermined potential, and the drain of the second MIS transistor is different from the first power supply line. The drain of the third MIS transistor is connected to the second power supply line of a predetermined potential, the drain of the third MIS transistor is connected to the output terminal, digital input data is applied to the gate of the second MIS transistor, and the load connected to the output terminal is predetermined. It is configured to pass the current of.

[Industrial application field]

The present invention relates to a current source circuit, and more particularly to a configuration of a current source circuit used in a current output type digital-analog converter (hereinafter referred to as a D / A converter).

[Conventional technology]

D / A converters are roughly classified into current output types such as current addition type and current switching type, and voltage output types such as voltage addition type and voltage switching type, but from the viewpoint that high-speed operation can be realized, A current output type D / A converter whose output appears in the form of current is often used.

FIG. 9 schematically shows a configuration example of a typical current output type D / A converter. In the figure, I ₁ , I ₂ , I ₃ , ...,
Indicates a current source, and SW ₁ , SW ₂ , SW ₃ , ... Represent switches which are turned on / off in response to the level of each corresponding bit of binary digital input data. A current source circuit is configured by each current source and the corresponding switch. 9th
In the configuration shown, for example, when the switch SW ₁ is closed, the current of the corresponding current source I ₁ appears at the output terminal OUT. That is, a current of an amount corresponding to the input digital signal appears as an analog amount at the output terminal OUT, and D / A conversion is performed.

FIG. 10 shows a circuit configuration of a current source circuit as an example of a conventional example. The illustration of FIG.
The structure of bits is shown.

In the figure, Q1 is an n-channel metal as a current source.
An oxide-semiconductor (MOS) transistor, or more broadly, a metal-insulator-semiconductor (MIS) transistor, the source of which is connected to a power supply line Vss (“L” level) of a predetermined potential, and the gate of which is the transistor. A predetermined DC bias VB is applied so that Q1 is always on. Therefore, the level of the node N1 is fixed at a potential higher than the potential of Vss by the threshold level (Vth) of the transistor Q1 (about 2V). Q2 is an n-channel MOS transistor, its source is connected to the drain of the transistor Q1, and its drain is connected to another power supply line Vcc (“H” level) of a predetermined potential. Transistor Q
Digital data D _IN is applied to the gate of 2.
Q3 is an n-channel MOS transistor, the source of which is connected to the drain of the transistor Q1, and the drain, that is, the output terminal OUT, is connected to the power supply line Vcc through the load LD. Data D _IN is applied to the gate of the transistor Q3 via the inverter INV.

The transistor Q1 is composed of the current sources I ₁ , I ₂ , I ₃ , and
…, Correspondingly, transistors Q2 and Q3 have switches SW ₁ , S
Corresponds to W ₂ , SW ₃ , ...

Now, it is assumed that the potential of Vcc is 5V, the potential of Vss is 0V, and the potential of the node N1 is 2V.

According to the circuit configuration of FIG. 10, when the data D _IN is at the “H” level, the transistor Q2 is turned on, while the “L” level data is applied to the gate of the transistor Q3 via the inverter INV. Therefore, the transistor Q3 is cut off. At this time, no current flows in the load LD. Further, when the data D _IN is at the “L” level, the transistor Q2 is in the cut-off state, and the “H” level data is applied to the gate of the transistor Q3, so that the transistor Q3 is in the on state. As a result, a predetermined current flows through the load LD.
In other words, the transistors Q2 and Q3 are turned on / off alternately in response to the data D _IN , so that the load LD has a predetermined current.
I ₀ is designed to flow.

However, according to the circuit configuration of FIG. 10, as shown in FIG. 11, when the data D _IN changes from the “H” level to the “L” level, that is, the transistor Q3 is in the cutoff state (between the gate and the source). When the voltage shifts from -5V) to the ON state (gate-source voltage is + 3V),
A "glitch" due to clock feedthrough occurs due to the capacitive coupling of the parasitic capacitance between the gate and source and between the gate and drain of Q3 and the magnitude of the change in the gate-source voltage. That is, a current larger than the predetermined current I ₀ transiently flows (indicated by a broken line G in FIG. 11), which causes a problem that the operation becomes unstable.

The configuration example of the circuit proposed to deal with this is No. 12
As shown in the figure.

This circuit is characterized by the transistor Q6 connected to the load side.
Has a constant voltage Vcc independent of the data D _IN
, And that the transistor Q5 that responds to the data D _IN is a p-channel type. The level of the node N2 is Vss as in the case of FIG.
It is fixed to a potential (about 2V) higher than the potential of by the amount of Vth of the transistor Q4.

According to the circuit configuration of FIG. 12, when the data D _IN is at the “L” level, the transistor Q5 is turned on and the potential of the node N2, that is, the source potential of the transistor Q6 is raised from 2V to 5V. Since the same voltage of 5 V as the source potential is applied to the gate, the transistor Q6
Is cut off. At this time, no current flows in the load LD. On the other hand, when the data D _IN is at “H” level, the transistor Q5 is cut off and the potential of the node N2 is
Returning to 2V, since the voltage of 5V is applied to the gate of the transistor Q6, the transistor Q6 is turned on. As a result, a predetermined current flows through the load LD.

As described above, in the circuit configuration of FIG. 12, the transistor Q6 connected to the load side is turned on / off in response to a change in the source potential thereof. Therefore, the data
When D _IN changes from “L” level to “H” level, that is, transistor Q6 is in the cut-off state (gate-source voltage is 0V) to on state (gate-source voltage is +3).
Considering the point of transition to V), the magnitude of the change in the gate-source voltage (3V) is smaller than that in the case of Fig. 10 (8V), so the gate-source and gate-drain of transistor Q6 Leakage of electric charges caused by capacitive coupling of parasitic capacitances between them is suppressed. That is, the circuit configuration is effective against glitches.

[Problems to be Solved by the Invention]

According to the conventional configuration (FIG. 12) described above, the generation of glitch is reduced by fixing the gate of the transistor Q6 connected to the load side to a constant voltage Vcc.
On the other hand, the following problems occur.

Considering when the transistor Q6 is in the ON state, the output terminal
The potential of OUT, that is, the drain potential becomes a level lower than the potential of Vcc by the amount of the voltage drop of the load L. At this time,
Level lower than the gate potential (Vcc) by Vth (Vcc
If the drain potential drops to a level below −Vth),
On the contrary, a current flows toward the output terminal side, and the transistor Q6, which should be in the on state, may be in the cutoff state in some cases. That is,
The on / off operation of the transistor Q6 becomes uncertain, and the reliability of the operation as a current source decreases.

Further, the change due to the OUT terminal voltage makes it difficult to stably maintain the output current at a predetermined value due to a change in V _DS of the current source transistor Q4 and a change in R _DS . Therefore, as the current source transistor Q4, it is necessary to use a transistor having a long gate length so that the output current is not so affected by the change in the drain potential.

However, when a transistor with a long gate length is formed on the chip, the area of the transistor cell increases,
Naturally, the parasitic capacitance between the gate and the source and between the gate and the drain also increases. When the parasitic capacitance becomes large, it takes a long time to charge and discharge the electric charge to the capacitance, which causes a problem that a high speed operation cannot be realized.

Furthermore, a p-channel transistor Q5 is used as a switch.
And the n-channel transistor Q6 is used,
For example, if a p-type substrate is used, it is necessary to provide an n-type well in the p-type substrate in order to form the p-channel type transistor Q5. This is not preferable because the cell area becomes larger than the case where two transistors of the same conductivity type channel are formed.

The present invention was created in view of the above-mentioned problems in the conventional technology, and an object thereof is to provide a current source circuit that enhances operation reliability and enables high-speed operation, and a D / A converter using the current source circuit. There is.

[Means and Actions for Solving Problems]

The problem in the above-described conventional technique is that when one transistor not connected to the load is in the on state, the other transistor connected to the load is in the off state,
The problem is solved by fixing the gate of the other transistor by a DC bias of a predetermined potential so that when the one transistor is in the off state, the other transistor is surely maintained in the on state.

Therefore, according to one aspect of the present invention, a first MIS transistor as a current source that operates by receiving a predetermined DC bias, and a second MIS having a channel of the same conductivity type as the first MIS transistor. A transistor and the first M
A third MIS transistor having the same isoelectric channel as the IS transistor and having a gate fixed with a DC bias of a predetermined potential, and the source of the first MIS transistor is a first power supply of a predetermined potential. Connected to a line, and the sources of the second and third MIS transistors are connected to the first MIS.
The second MIS transistor is connected to the drain of the transistor, the drain of the second MIS transistor is connected to the second power supply line of a predetermined potential different from the first power supply line, and the drain of the third MIS transistor is connected to the output terminal. , The second
There is provided a current source circuit characterized in that digital input data is applied to the gate of an MIS transistor, and a predetermined current is caused to flow through a load connected to the output end.

The DC bias of the predetermined potential to be applied to the gate of the third transistor is determined as follows.

Now, assume that the conductivity type of the channels of the first, second and third transistors is n-type.

In this configuration, when the digital input data is at the "L" level, the second transistor is in the off state, and the third transistor is in the on state, so that the output terminal has a predetermined current (I). ) Need to be flushed. As a _{condition, I = β (V G -V} S -V th) 2/2 ...... is true. However, β, V _G , V _S , and V _th are the third
Represents the current amplification factor, gate potential (DC bias), source potential, and threshold level of the transistor.

On the other hand, when the digital input data is at "H" level, the second transistor is in the ON state, and therefore the third transistor is in the OFF state, so that the output terminal has a predetermined current I
Don't wash away. As a _{condition, I = β (-V S -V} th) 2/2 holds ....

Since β and V _th are constants, the gate potential (DC bias) V _G and the source potential V _S may be determined from the equations and. As a result, reliable operation of the current source circuit can be guaranteed. On the other hand, since the gate of the third transistor is fixed by the DC bias V _G of a predetermined potential, the occurrence of glitches is greatly reduced, and thus the operation speed can be increased.

Further, in a preferred embodiment of the present invention, a fourth MIS transistor may be provided as a current source in series with the first transistor. As described above, by adopting the so-called "two-stage stacked" transistor configuration, the cell area can be equivalently reduced, the parasitic capacitance of the transistor can be reduced, and high-speed operation can be further promoted. The details will be described using an embodiment described later with reference to the accompanying drawings.

Further, according to another aspect of the present invention, a plurality of the above-mentioned current source circuits are provided, and the gates of the first MIS transistor, the third MIS transistor and the fourth MIS transistor in each current source circuit are provided. Each of the current source circuits is provided with a bias circuit that supplies a predetermined DC bias, and each bit of the digital input signal is applied to the gate of the second MIS transistor in each current source circuit. There is provided a digital-analog converter characterized in that an electric current is taken out as an analog quantity.

Details of other structural features and operations of the present invention will be described using embodiments described below with reference to the accompanying drawings.

〔Example〕

FIG. 1 shows a circuit configuration of a current source circuit as an embodiment of the present invention. The illustration of FIG.
The structure of one bit of digital input data is shown.

In FIG. 1, Q11 is an n-channel type MOS as a current source.
A transistor whose source is a low-level power line
It is connected to Vss (voltage is 0V), and the gate has a certain direct current bias V that keeps the transistor Q11 always on.
₁₁ is being applied. Q12 is an n-channel MOS transistor, the source of which is connected to the drain of the transistor Q11, and the drain is the high-level power supply line Vcc (voltage is 5V).
Connected to V). Digital input data D _IN is applied to the gate of the transistor Q12. Q13 is an n-channel MOS transformer, its source is connected to the drain of the transistor Q11, and its drain, that is, the output terminal OUT is connected to the power supply line Vcc via the load LD. A direct current bias V ₁₂ having a predetermined potential is applied to the gate of the transistor Q13.

The magnitude of this DC bias V ₁₂ and the source potential of the transistor Q ₁₃ are determined by the above equations and. In this case, Vcc (5V) between each potential> V _12> source potential> Vs
Of course, there is a relationship of s (0V).

As described above, by appropriately setting the magnitude of V ₁₂ and the source potential, when the digital input data D _IN is at “H” level, the transistor Q12 turns on and the source potential of the transistor Q13 rises to “H” level. As a result, the transistor Q13 is cut off. On the other hand, when the data D _IN is at "L" level, the transistor Q12 is cut off and the transistor Q13 is turned on, and a predetermined current flows through the load LD. At this time, the potential of the output terminal OUT becomes lower than the potential of Vcc due to the voltage drop of the load, but since the magnitude of V ₁₂ is set so as to satisfy the above-mentioned condition, the on-state of the transistor Q13 is sure to be on. Maintained at. by this,
With reliable operation as a current source circuit,
Occurrence of the glitch is greatly reduced by the gate of the transistor Q13 is fixed at a predetermined DC bias V _12. This leads to faster operation.

FIG. 2 shows a circuit configuration of a modification of the embodiment shown in FIG. In the example shown in the figure, a p-channel type MOS transistor is used instead of the n-channel type MOS transistors Q11, Q12 and Q13 in FIG.
The case where the transistors Q21, Q22, and Q23 are used is shown.

The mode of operation and the method of determining the magnitude of the DC bias V ₂₂ and the source potential of the transistor Q 23 are the same as in the case of the embodiment of FIG.
However, in this case, the transistor Q23 is cut off when the data D _IN is at the “L” level, the transistor Q23 is turned on when the data D _IN is at the “H” level, and a predetermined current flows through the load LD.

FIG. 3 shows a circuit configuration of a current source circuit as another embodiment of the present invention.

Compared with the configuration of the embodiment of FIG. 1, an n-channel type transistor
Q11 to Q13 are replaced with n-channel type transistors Q31 to Q33. Further, as a structural feature of the present embodiment, an n-channel type transistor Q34 which receives a predetermined DC bias V ₃₂ and operates as a current source is a drain of the transistor Q31. And the sources of the transistors Q32 and Q33.

Thus, by adopting the two-stage stacked transistor structure as the current source, the cell area can be equivalently reduced and the parasitic capacitance of the transistor can be reduced, thereby further increasing the operating speed of the circuit of FIG. Can be promoted at high speed. The reason for this will be described below with reference to FIG.
A description will be given with reference to (b) and FIGS. 5 (a) and (b).

4 (a) and 4 (b) respectively show the configuration of a single transistor used as a current source and its equivalent circuit, and FIGS. 5 (a) and 5 (b) respectively show a two-stage circuit used as a current source. The structure of a stacked transistor and its equivalent circuit are shown. In this case, for the single transistor,
The ratio of the change in the power current I _{0 to} the change in the drain voltage V ₀ is expressed by dI ₀ / dV ₀ = 1 / r ₀ (1), while for the two-stage stacked transistor, dI ₀ / dV ₀ = 1 / (g _m · r ₀ · r ₀ ) ... (2) However, g _m represents the transfer conductance of the transistor. Further, the output current I ₀ is represented by I = beta _{[(V G -V th) · V} 0 -V 0 2/2 ] ... (3). Here, β is represented by β = W · μ · ε _OX / (L · t _OX ) (4). Where W is the gate width, L is the gate length, μ
Is the carrier mobility, ε _OX is the dielectric constant of the gate insulating film, t _OX
Indicates the thickness of the gate insulating film, respectively.

As is clear from the above equations (1) to (4), linearity is guaranteed even if the gate length of the two-stage stacked transistor is shorter than that of the single transistor. This means that when the same current is passed through the transistor, if the gate length becomes 1 / n, the gate width also becomes 1 / n and the area of the channel region becomes 1 / n ^2. is there.

Returning to FIG. 3, in this embodiment, of the two-stage stacked transistors Q31 and Q34 as current sources, the transistor Q34, which is closer to the switching transistor Q33, has a smaller channel region than the other transistor Q31. Has been formed. In general, many parasitic capacitances such as junction capacitances are formed in a transistor, but when the capacitance is charged and discharged, it is disadvantageous in terms of operating speed. Therefore, in this embodiment, the switching transistor Q33 whose voltage change is larger than the change in the potential V1 at the connection point of the transistors Q31 and Q34.
The cell size (channel region) of the transistor Q34 connected to the source potential V2 is formed to be small so that the amount of charging / discharging of the parasitic capacitance can be small, and high speed operation is enabled.

FIG. 6 shows a circuit configuration of a modification of the embodiment shown in FIG. The example shown in the figure shows a case where p-channel type MOS transistors Q61, Q62, Q63 and Q64 are used instead of the n-channel type MOS transistors Q31, Q32, Q33 and Q34 in FIG.

Its operation mode, the magnitude of the DC bias V ₆₃ of the transistor Q63 connected to the load and a method of determining the source potential,
Also, the channel region of the transistor Q64 closer to the switching transistor Q63 is used as the other transistor Q61.
The formation of smaller parts in each case is the same as in the case of the embodiment shown in FIG. 1, and therefore its explanation is omitted.

However, in this case, as shown in FIG.
When D _IN is at “H” level, the transistor Q62 is in the cutoff state, and the potential of the node NN is at “H” level, so that the transistor Q63 is turned on and the predetermined current I ₀ flows through the load LD. When the data D _IN changes to the “L” level, the transistor Q62 turns on and the potential of the node NN drops to the “L” level, whereby the transistor Q63 cuts off and the current I ₀ stops flowing.

FIG. 8 shows a configuration example of a D / A converter using the current source circuit of FIG.

In the figure, IS _{1 to} IS _n are current source circuits shown in FIG. 6, VC is a bias circuit, and transistor Q61, transistor Q64 and transistor of each current source circuit are shown.
Predetermined DC bias for each gate of Q63 V ₆₁ , V
_It has the function of supplying ₆₂ and V ₆₃ . According to the D / A converter of FIG. 8, the corresponding transistor in each current source circuit corresponds to each bit data of the digital input signal D _IN.
By turning on and off Q62, a predetermined current is output through the corresponding transistor Q63 in each current source circuit.
It is supposed to be taken by. That is, a current of an amount corresponding to the input digital signal D _IN appears as an analog amount at the output end OUT, and D / A conversion is performed.

〔The invention's effect〕

As described above, according to the present invention, by fixing the gate of the transistor connected to the load with a DC bias of a predetermined potential, it is possible to guarantee a highly reliable operation as a current source circuit, and at the same time, It is possible to significantly reduce the occurrence of glitches and speed up the operation.

Further, when a two-stage stacked transistor structure is used as the current source, the cell area can be equivalently reduced, thereby reducing the parasitic capacitance of the transistor and further promoting high-speed operation.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing the configuration of a current source circuit as an embodiment of the present invention, FIG. 2 is a circuit diagram of a modification of the embodiment of FIG. 1, and FIG. 3 is another embodiment of the present invention. Is a circuit diagram showing the configuration of the current source circuit of FIG. 4, FIGS. 4 (a) and 4 (b) are diagrams showing the configuration of a single transistor used as a current source and its equivalent circuit, and FIGS. 5 (a) and 5 (b) are Used as a current source 2
FIG. 6 is a diagram showing the structure of a stacked transistor and its equivalent circuit. FIG. 6 is a circuit diagram of a modified example of the embodiment shown in FIG. 3. FIG. 7 is an operation waveform diagram of each part of the circuit shown in FIG. FIG. 10 is a circuit diagram showing a configuration example of a D / A converter using the current source circuit of FIG. 9, FIG. 9 is a diagram schematically showing a configuration example of a typical current output type D / A converter, FIG. Is a circuit diagram showing the configuration of a current source circuit as an example of the conventional type, FIG. 11 is an operation waveform diagram of the circuit of FIG. 10, and FIG. 12 is a circuit showing the configuration of a current source circuit as another example of the conventional type. Fig. (Explanation of symbols) Q11, Q21, Q31, Q61 ... first MIS transistor, Q12, Q22, Q32, Q62 ... second MIS transistor, Q13, Q23, Q33, Q63 ... third MIS transistor, Q34, Q64 …… 4th MIS transistor, D _IN …… Digital input data, LD …… Load, Vcc, Vss …… Power line OUT …… Output end, V ₁₁ ,, V ₁₂ ,, V ₂₁ ,, ₂₂ , V ₃₁ , V ₃₂ , V ₃₃ , V ₆₁ , V ₆₂ , V ₆₃ …… Predetermined DC bias, IS _{1 to} IS _n …… Current circuit, VC …… Bias circuit.

Claims (2)

[Claims] 1. A first MIS transistor as a current source that operates by receiving a predetermined DC bias _{(V 31, V 61) (} Q31, Q
61), a second MIS transistor (Q32, Q62) having a channel of the same conductivity type as that of the first MIS transistor, and a channel of the same conductivity type as the first MIS transistor, and having a predetermined gate. A third MIS transistor (Q33, Q63) fixed with a DC bias (V ₃₃ , V ₆₃ ) of electric potential; a drain of the first MIS transistor and a source of each of the second and third MIS transistors. Has a channel of the same conductivity type as that of the first MIS transistor and has a channel region smaller than that of the first MIS transistor, and has a predetermined DC bias (V ₃₂ , V ₆₂ ).
And a fourth MIS transistor (Q34, Q64) functioning as a current source in response to the first potential of the first potential of the first MIS transistor.
Is connected to a power supply line (Vss, Vcc) of the second MIS transistor, and the drain of the second MIS transistor is connected to a second power supply line (Vcc, Vss) having a predetermined potential different from that of the first power supply line.
The drain of the third MIS transistor is an output terminal (OUT)
And a digital input data (D _IN ) is applied to the gate of the second MIS transistor to cause a predetermined current to flow through a load (LD) connected to the output end. Source circuit. 2. A plurality of current source circuits according to claim 1 (IS ₁
~ IS _n ) and a bias circuit (VC) for supplying a predetermined DC bias to each gate of the first MIS transistor, the third MIS transistor and the fourth MIS transistor in each current source circuit. , Each bit of the digital input signal (D _IN ) is applied to the gate of the second MIS transistor in each current source circuit, and the current corresponding to the digital input signal from the output end (OUT) is used as an analog amount. A digital-analog converter characterized by being taken out.