JPS60167528A - Digital-to-analog converting circuit - Google Patents

Digital-to-analog converting circuit

Info

Publication number
JPS60167528A
JPS60167528A JP2414284A JP2414284A JPS60167528A JP S60167528 A JPS60167528 A JP S60167528A JP 2414284 A JP2414284 A JP 2414284A JP 2414284 A JP2414284 A JP 2414284A JP S60167528 A JPS60167528 A JP S60167528A
Authority
JP
Japan
Prior art keywords
current
circuit
constant
constant current
accuracy
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2414284A
Other languages
Japanese (ja)
Inventor
Shigeatsu Asari
栄厚 浅利
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP2414284A priority Critical patent/JPS60167528A/en
Publication of JPS60167528A publication Critical patent/JPS60167528A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00Analogue/digital conversion; Digital/analogue conversion
    • H03M1/66Digital/analogue converters
    • H03M1/74Simultaneous conversion

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Analogue/Digital Conversion (AREA)

Abstract

PURPOSE:To simplify the conversion into a semiconductor and to improve easily the converting accuracy of a D/A converting circuit, by providing a constant current source and (n) stages of control circuits for differential current switching circuits of said current source to specify each constant current value together with addition circuits of each constant current and addition current loads. CONSTITUTION:A constant current source contains TRs Q13-Q16 and resistances R5-R8, and the current values I1-I4 are set at In=AX2<n-1> (A: constant) by those resistances R5-R8. Then TRs Q1-Q4 control the differential current switching circuit of the constant current circuit, and a current mirror circuit A adds the constant currents. Thus inputs D1-D4, output currents and voltages are shown in a table. Here I2=2I1, I3=4I1 and I4=8I1 are satisfied together with TRQ17=Q15, R9=R10 and R12=1/2R9 respectively. Then TRs Q1-Q4 are turned on and off when inputs D1-D4 are set at 0 and 1. Therefore a load current I5 produces a current output of an integer multiple and the output voltage V3 is equal to the output voltage of an integer multiple as shown in the table. As a result, the potentials of 16 stages are produced with 4 bits. The converting accuracy is decided by the accuracy of the resistances which decide each constant current value.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は、デジタル信号からアナログ信号に変換するD
/A変換回路に関する。
DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a D
/A conversion circuit.

従来例の構成とその問題点 近年、電子回路をもって構成した各電子機器は、半導体
技術の進展により、アナログ技術とデジタル技術の合体
化が進み、その結果アナログ、デジタル処理の面からD
/A変換、A/D変換の必要性が大きく、重要なものと
なっている。又、電子機器そのものの信頼性、形状、重
量といった面からも可能な限シ半導体化を行ないたいと
いう要望が大きい。しかしながら従来のD/A変換にお
いては、第1図及び第2図(&) (b) (Q)に示
す様に、抵抗分割を制御することによって希望する電位
を得るラダー抵抗型とパルス巾のデユーティ比を変化さ
せ積分することにより希望する電位を発生させるパルス
デューティ型とがあるが、前者のラダー抵抗型では抵抗
値の精度でD/A変換精度が決定されるため各抵抗素子
に対する精度補正個所が多くなる欠点があり、又全体を
半導体化する上でチップ面積が大きく、レーザートリミ
ング個所が多い等、コスト上からも大きな欠点を肩して
いる。又、後者のパルスデューティ型においては半導体
化に際してチップ面積は狭くて良い利点があるが、パル
ス波によるノイズ輻射の点や正確なりロック発生回路等
を必要とする欠点を有しており、使用範囲が限定される
とか、コストが高くなる等の欠点があった。
Conventional configurations and their problems In recent years, advances in semiconductor technology have led to the integration of analog and digital technologies in electronic devices configured with electronic circuits.
/A conversion and A/D conversion are becoming increasingly necessary and important. Furthermore, there is a strong desire to use semiconductors as much as possible in terms of the reliability, shape, and weight of electronic devices themselves. However, in conventional D/A conversion, as shown in Figures 1 and 2 (&) (b) (Q), there is a ladder resistance type that obtains the desired potential by controlling resistance division, and a ladder resistance type that obtains the desired potential by controlling the resistance division. There is a pulse duty type that generates a desired potential by changing the duty ratio and integrating it, but in the former ladder resistance type, D/A conversion accuracy is determined by the accuracy of the resistance value, so accuracy correction is made for each resistance element. It has the disadvantage of requiring a large number of parts, and also has major disadvantages in terms of cost, such as the large chip area and the large number of laser trimming parts when converting the entire device into a semiconductor. In addition, the latter pulse duty type has the advantage of having a small chip area when converted into a semiconductor, but has the disadvantages of noise radiation due to pulse waves and the need for an accurate lock generation circuit, etc., and the range of use is limited. There were disadvantages such as limited availability and high cost.

発明の目的 本発明は、上記の様な従来の欠点を大巾に改善し、バイ
ポーラIC内部にも容易に装備することができるD/A
変挾回路を提供することを目的とする。
Purpose of the Invention The present invention provides a D/A that greatly improves the conventional drawbacks as described above and that can be easily installed inside a bipolar IC.
The purpose is to provide a changing circuit.

発明の構成 本発明は、この目的を達成するため、バイポーラトラン
ジスタによる定電流回路と定電流回路を定数)なる値を
持つ様に構成し、各定電流回路の定電流を加算するカレ
ントミラー回路と加算電流負荷を設けてなり、容易に半
導体化を実現し得ると共に、精度向上のだめの補正個所
束くて済み、又バイポーラICの同一チップ内に他の回
路と共に実装できるD/A変換回路を提供する。
Structure of the Invention In order to achieve this object, the present invention comprises a constant current circuit using bipolar transistors and a constant current circuit so as to have a constant value, and a current mirror circuit that adds the constant currents of each constant current circuit. Provides a D/A conversion circuit that includes an additional current load, can be easily realized as a semiconductor, eliminates the need for a large number of correction points for accuracy improvement, and can be mounted together with other circuits in the same chip of a bipolar IC. do.

実施例の説明 以下、本発明の一実施例を第3図に基づいて説明する。Description of examples Hereinafter, one embodiment of the present invention will be described based on FIG. 3.

第3図は4ビットD/A変換回路を示すものである。定
電流回路は、トランジスタQ13と抵抗R5、トランジ
スタQ14と抵抗R6、トランジスタQ+sと抵抗R7
、トランジスタQ1gと抵抗R8で構成され、各々の定
電流値は工11工2、工3、工4である。これら定電流
回路ではトランジスタQ4s、Q14、Q、ts、Q、
Il+のベースに■1なる電位を与えているので、各定
電流値は、抵抗R5、R6、R7、Raの値で任意に設
定でき、この回路での各定電流値はIn=AX2(Aは
定数)となる様に設定している。したがって、各定電流
値は工2=2工11工3=本11工4−8工lである。
FIG. 3 shows a 4-bit D/A conversion circuit. The constant current circuit includes transistor Q13 and resistor R5, transistor Q14 and resistor R6, transistor Q+s and resistor R7.
, a transistor Q1g, and a resistor R8, and their respective constant current values are 11, 2, 3, and 4. In these constant current circuits, transistors Q4s, Q14, Q, ts, Q,
Since a potential of ■1 is applied to the base of Il+, each constant current value can be set arbitrarily by the values of resistors R5, R6, R7, and Ra, and each constant current value in this circuit is In=AX2(A is a constant). Therefore, each constant current value is 2 = 2 = 11 = 11 = 4-8.

トランジスタQ、sとQ6、Q7とQ8、Q9とQ、1
0. Q、11とQ12は定電流回路をスイッチする差
動電流切換回路、トランジスタQl、 Q2、Qs、 
Q4はこの切換回路を制御する制御回路であり、各段は
制御回路で制御される定電流源となる。抵抗R9、Rl
x、RIOとトランジスタQ17、Qll+はカレント
ミラー回路であり、各定電流を加算するため、トランジ
スタQ6、Q8、Qlo、Q、tzのコレクタに接続し
である。抵抗Ftttはカレントミラー負荷で、トラン
ジスタQrsのコレクタ電流に比例した電位を発生する
。即ち、この電位をVs、コレクタ電流を工Sとすると
、出力電位はVswRu×ニーである。前記差動電流切
換スイッチの片側のペース電位は■2で与えられてお如
、他方は抵抗R1,IhR8,14f通じて電位が与え
られているので、制御回路のトランジスタQ1、Q2、
Q3、Q4のオン、オフにより各定電流はスイッチされ
る。Dl、D2、D3、D4は制御トランジスタQt、
 J、Qs、 Qaをオン、オフする制御用入力である
Transistors Q, s and Q6, Q7 and Q8, Q9 and Q, 1
0. Q, 11 and Q12 are differential current switching circuits that switch constant current circuits, transistors Ql, Q2, Qs,
Q4 is a control circuit that controls this switching circuit, and each stage becomes a constant current source controlled by the control circuit. Resistor R9, Rl
x, RIO and transistors Q17, Qll+ are current mirror circuits, and are connected to the collectors of transistors Q6, Q8, Qlo, Q, and tz in order to add each constant current. The resistor Fttt is a current mirror load and generates a potential proportional to the collector current of the transistor Qrs. That is, when this potential is Vs and the collector current is S, the output potential is VswRu×knee. The pace potential on one side of the differential current changeover switch is given by (2), and the potential is given on the other side through the resistors R1, IhR8, 14f, so that the transistors Q1, Q2, and
Each constant current is switched by turning Q3 and Q4 on and off. Dl, D2, D3, D4 are control transistors Qt,
This is a control input that turns on and off J, Qs, and Qa.

今、入力D1、D2、Da%D4にトランジスタQ1、
Qs。
Now, the transistor Q1 is connected to the inputs D1, D2, and Da%D4.
Qs.

Q3、Q4をオン、オフする電位データが入力した場合
、次表に示す如き、電流出力及び出力電圧が得られる。
When potential data for turning on and off Q3 and Q4 is input, current output and output voltage as shown in the following table are obtained.

ここで、各定電流値It、工2、工3、工4は前述の如
く、工2−2工1、工3−4工1、工4−8工1であシ
、トランジスタQ17りQ息8、抵抗R・x R1ζ抵
抗R1z−火R9という条件が滴ださ扛ておシ、入力D
I〜D4が0のとキ、トランジスタQ1〜q4がオフし
、1のときオンするものとする。
Here, the constant current values It, 2-2, 3, and 4 are as described above, 2-2 1, 3-4 1, 4-8 1, transistor Q17 Breath 8, Resistance R x R1ζResistance R1z - Fire R9 conditions are dropped, input D
It is assumed that transistors Q1 to Q4 are turned off when I to D4 are 0, and turned on when they are 1.

表から明らかな様に、工5は整数倍の電流出方を発生し
、したがって出力電圧v3は整数倍の出力電圧となる。
As is clear from the table, the circuit 5 generates a current output that is an integral multiple, and therefore the output voltage v3 becomes an output voltage that is an integral multiple.

したがって各入力データをバイナリ−コードで入力すれ
ば、4ビツトの場合は16段の電位を発生することにな
る。
Therefore, if each input data is input in binary code, 16 stages of potentials will be generated in the case of 4 bits.

この様にnピッ) D/A変換回路は、定電流源をn段
用いれば良く、又D/A変換の精度は、各定電流値の精
度に着目すればよいので、具体的には定電流値を決定す
る各回路の抵抗の管理をすれはよいことになる。又、半
導体構成上からも、各段の抵抗素子がチップ内で相互歪
の少ガい様に近接した個所に配置できるなど、管理、設
計も容易である0 発明の効果 本発明のD/A変換回路によれば、以上の説明から明ら
かな様に、バイボーラエC内部に容易に装備でき、また
D/A変換精度の管理も容易であり、回路そのものが素
子数も少なくシンプルでかつ容易にビット数対応もでき
、また回路構成上不良を発生する要素がバイポーラ半導
体回路と差異が々いためこの回路を装備したことによっ
て不良率が上昇するということもない等、生産性、実装
性、コスト面等において極めて大きな効果を発揮する。
In this way, the D/A conversion circuit can use n stages of constant current sources, and the accuracy of D/A conversion can be determined by focusing on the accuracy of each constant current value. This makes it easier to manage the resistance of each circuit that determines the current value. In addition, from the standpoint of the semiconductor structure, the resistance elements of each stage can be placed close to each other within the chip to minimize mutual distortion, making management and design easy. As is clear from the above explanation, the conversion circuit can be easily installed inside the bibolar E-C, the D/A conversion accuracy can be easily managed, and the circuit itself has a small number of elements, is simple, and can easily convert bits. In addition, the elements that cause defects in the circuit configuration are very different from bipolar semiconductor circuits, so installing this circuit will not increase the defective rate, etc., in terms of productivity, implementation, cost, etc. It is extremely effective.

【図面の簡単な説明】[Brief explanation of drawings]

第1図及び第2図は従来例を示し、第1図はラダー型の
基本構成図、第2図(a) (1)) (0)はそれぞ
れパルスデューティ型における各種パルス波形とその出
力電圧を示す図、第3図は本発明の一実施例の回路図で
ある。 (Q13とR11Q+4とR6、Q+sとR7、Qts
とRs)・・・定電流回路、(QllとQ6、Q7とQ
8、Q9とQ+o、QlとQ、u)・・・差動電流切換
回路、(Ql、Q、z、Q3、Q4)・・・制御回路、
(R9、R12、RIO,Ql7、Qlg )・・・カ
レントミラー回路、(Rn)・・・負荷。 第7図 第 2 し1 (J 略− り コ 9 ≧\ 0−−□−−−一−
Fig. 1 and Fig. 2 show conventional examples, Fig. 1 is a basic configuration diagram of a ladder type, and Fig. 2 (a) (1)) (0) shows various pulse waveforms and their output voltages in a pulse duty type, respectively. FIG. 3 is a circuit diagram of an embodiment of the present invention. (Q13 and R11Q+4 and R6, Q+s and R7, Qts
and Rs)...constant current circuit, (Qll and Q6, Q7 and Q
8, Q9 and Q+o, Ql and Q, u)...differential current switching circuit, (Ql, Q, z, Q3, Q4)...control circuit,
(R9, R12, RIO, Ql7, Qlg)...Current mirror circuit, (Rn)...Load. Fig. 7 No. 2 1 (J Omitted- Riko 9 ≧\ 0--□--1-

Claims (1)

【特許請求の範囲】[Claims] バイポーラトランジスタによる定電流回路と定電流回路
をスイッチする差動電流切換回路とで構成する定電流源
と、差動電流切換回路を制御する制御回路とをn段設け
ると共に、前記各定電流回路の定電流値が工n−AX2
(Aは定数)なる値を持つ様に構成し、各定電流回路の
定電流を加算するカレントミラー回路と加算電流負荷を
設けてなるD/ム変換回路。
A constant current source composed of a constant current circuit using a bipolar transistor and a differential current switching circuit that switches the constant current circuit, and a control circuit that controls the differential current switching circuit are provided in n stages, and each of the constant current circuits is Constant current value is n-AX2
(A is a constant), and includes a current mirror circuit that adds the constant currents of each constant current circuit and an addition current load.
JP2414284A 1984-02-09 1984-02-09 Digital-to-analog converting circuit Pending JPS60167528A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2414284A JPS60167528A (en) 1984-02-09 1984-02-09 Digital-to-analog converting circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2414284A JPS60167528A (en) 1984-02-09 1984-02-09 Digital-to-analog converting circuit

Publications (1)

Publication Number Publication Date
JPS60167528A true JPS60167528A (en) 1985-08-30

Family

ID=12130071

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2414284A Pending JPS60167528A (en) 1984-02-09 1984-02-09 Digital-to-analog converting circuit

Country Status (1)

Country Link
JP (1) JPS60167528A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01289319A (en) * 1988-05-17 1989-11-21 Fujitsu Ltd Current source circuit and digital/analog converter using it
JPH0390135U (en) * 1989-12-26 1991-09-13
EP0603904B1 (en) * 1992-12-25 2005-08-03 Canon Kabushiki Kaisha Digital-to-analogue conversion circuit

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01289319A (en) * 1988-05-17 1989-11-21 Fujitsu Ltd Current source circuit and digital/analog converter using it
JPH0390135U (en) * 1989-12-26 1991-09-13
EP0603904B1 (en) * 1992-12-25 2005-08-03 Canon Kabushiki Kaisha Digital-to-analogue conversion circuit

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