JPS59122120A - Digital-analog converter - Google Patents

Digital-analog converter

Info

Publication number
JPS59122120A
JPS59122120A JP22741682A JP22741682A JPS59122120A JP S59122120 A JPS59122120 A JP S59122120A JP 22741682 A JP22741682 A JP 22741682A JP 22741682 A JP22741682 A JP 22741682A JP S59122120 A JPS59122120 A JP S59122120A
Authority
JP
Japan
Prior art keywords
current
beta
transistor
current source
digital
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP22741682A
Other languages
Japanese (ja)
Inventor
Toshiyasu Yoshizawa
吉沢 寿康
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP22741682A priority Critical patent/JPS59122120A/en
Publication of JPS59122120A publication Critical patent/JPS59122120A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00Analogue/digital conversion; Digital/analogue conversion
    • H03M1/66Digital/analogue converters

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Analogue/Digital Conversion (AREA)

Abstract

PURPOSE:To prevent the fluctuation in a D-A conversion output current due to the variance of beta by adding sum of base currents of transistors (TRs) constituting a current source and TRs constituting a switch to the current source. CONSTITUTION:Let a current of the current source 32 be I, then almost the same current I flows also to diodes 30, 26, TRs 28, 1 and resistors 27, 5. A VBE31 of a TR31 is given by VBE=VBE28+VBE29-VBE30. Since VBE=VBE30, the relation of VBE31=VBE29 is obtained. Further, a current flowing to a TR29 is I/beta and a current flowing to a TR31 is 2 (I/beta), when the emitter area of the TR31 is twice that of the TR29. On the other hand, when a TR31 is conductive by an input signal, 2 (I/beta) is added to the emitter current, resulting in being (1+I/beta) I, and an output current IOUT at a terminal 23 is IOUT=(1+1/beta) (1-1/beta). This equation indicates that the stability is improved by nearly 1/beta times that of a conventional circuit.

Description

【発明の詳細な説明】 〔発明め技術分野〕 本発明に、デジタル・アナログ変換器に1関し、更に詳
細にはトランジスタの飛流利得のばらつきによるデジタ
ル・アナログ変換器の精度の劣化を減少させ得る高精度
のデジタル・アナログ変換器に関する。
[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a digital-to-analog converter, and more particularly, to a method for reducing deterioration in precision of a digital-to-analog converter due to variations in flying gain of transistors. Regarding obtaining high precision digital-to-analog converters.

〔発明の技術的背景とその問題点〕[Technical background of the invention and its problems]

従来のデジタル・アナログ変換器(以下DACと称する
)の−例として、R−2Rはしご形抵抗網を用いた4ピ
ツ)DACを、第111Jに示す。npnバイポーラト
ランジスタlと抵抗]’15によシ宅流源を構成し、同
様にトランジスタ2と抵抗6゜トランジスタ3と抵抗7
.トランジスタ4と抵抗8により各々同−眠流値の電流
源を構成し、該電流値は、バイアス端子9の電圧VBに
よジ決定する。一方、4ビツト〜・デジタル・データ入
力端子群18に印加されたデータによりnpnバイポー
ラトランジスタ10と11.12と13.14と15及
び16と17によって構成される差動スイッチを切換え
、前記電流源の電流を、Fiシご形抵抗網19へ流すか
、電源21へ流すかを選別し、出力端子20には、該デ
ジタル中データに対応して重みづけされた電圧すなわち
、デジタル中アナログ変換された電圧VOutが出力さ
れるものである。
As an example of a conventional digital-to-analog converter (hereinafter referred to as DAC), a 4-pin DAC using an R-2R ladder resistor network is shown in No. 111J. npn bipolar transistor l and resistor] '15 constitutes a current source, and similarly transistor 2 and resistor 6, transistor 3 and resistor 7
.. The transistor 4 and the resistor 8 each constitute a current source having the same current value, and the current value is determined by the voltage VB of the bias terminal 9. On the other hand, the data applied to the 4-bit digital data input terminal group 18 switches the differential switch constituted by the npn bipolar transistors 10, 11, 12, 13, 14, 15, 16, and 17, and It is selected whether to flow the current to the Fi wire resistor network 19 or to the power supply 21, and the output terminal 20 receives a weighted voltage corresponding to the digital data, that is, the digital data is converted to analog data. The voltage VOut is output.

このようなりACにおける精度は主に、電流源の精度に
よるところが大きい。これを単一半導体基板(以下IC
と称する)上に形成する場合の誤差要因としては、下記
三項目が挙げられる。■トランジスタのベースφエミッ
タ間電圧VBE のばらつき△VBB、■トランジスタ
の電流利得βのばらつき△β、■抵抗値Rのばらつき△
Rがある。■に関してはバイアス1圧VBを太き(し、
抵抗REにかかるな圧を大きくして減少でき、■に関し
ては、抵抗の而Sを大きくすることにより減少できる。
The accuracy in AC is largely dependent on the accuracy of the current source. This is a single semiconductor substrate (hereinafter referred to as IC)
The following three items can be cited as error factors when forming on the top of ■Variation in transistor baseφemitter voltage VBE △VBB, ■Variation in transistor current gain β △β, ■Variation in resistance value R△
There is R. Regarding ■, increase the bias 1 pressure VB (and
This can be reduced by increasing the pressure applied to the resistor RE, and (2) can be reduced by increasing the resistance S.

■に関して図面を参照し説明する。第1図に示されるD
ACにおける。1ビツトの電流源とスイッチ回路を第2
図に示す。ここで出力端子23に流れる電流を求める。
(2) will be explained with reference to the drawings. D shown in Figure 1
In AC. The 1-bit current source and switch circuit are connected to the second
As shown in the figure. Here, the current flowing through the output terminal 23 is determined.

抵抗RE、5を流れる電流IU各ビットで等しいとして
、トランジスタ1のコレクタ萌1流は(1−1/β〕・
■となり、スイッチトランジスタ11が導通の時のコレ
クタ電流は(1−1/β)・(1−1/β)・Iとなり
、端子23の出力電流I outに、 I out = (1−2/79+’/79N )”I
ここでβ75凡、△βばらついたとすると、2つのピッ
ト間の出力電流差は、 △■ユ(2/β)・(Al7β片・・・・・・・・・・
・・・・(11で与えられこれが誤差となる。これは同
一エミッタ電流の時のベース電流の差に起因するため。
Assuming that the current IU flowing through the resistors RE and 5 is equal for each bit, the collector current of the transistor 1 is (1-1/β).
■The collector current when the switch transistor 11 is conductive is (1-1/β)・(1-1/β)・I, and the output current I out of the terminal 23 is I out = (1-2/ 79+'/79N)"I
Here, assuming that β75 and △β vary, the output current difference between the two pits is △■U(2/β)・(Al7β piece...
(11) This is an error. This is due to the difference in base current when the emitter current is the same.

バイアスVB 9よシ引き込む電流を減少させればよく
、そのために第3図のようにトランジスタ25を接続し
たダーリントン接続とすることもでき、この場合の出力
電流差は △エユ(1/β)・(Al7β片・・・・・・・・・・
・・・・(21となf)Al1  に改善されるが、ト
ランジスタ25と1の△VBE  が増加するという欠
点があった。
It is only necessary to reduce the current drawn by the bias VB 9, and for this purpose, a Darlington connection with a transistor 25 connected as shown in FIG. 3 can be used. In this case, the output current difference is ΔE (1/β)・(Al7β piece...
(21 and f)Al1 is improved, but there is a drawback that ΔVBE of transistors 25 and 1 increases.

また、スイッチ用トランジスタ11のベース電流が補償
されていないという欠点があった。
Another drawback is that the base current of the switching transistor 11 is not compensated for.

〔発明の目的〕[Purpose of the invention]

本発明はトランジスタの電流利得βのばらつきによるデ
ジタル・アナログ変換器の精度の劣化を改善したデジタ
ル・アナログ変換器を提供することを目的とするもので
ある。
SUMMARY OF THE INVENTION An object of the present invention is to provide a digital-to-analog converter in which deterioration in accuracy of the converter due to variations in current gain β of transistors is improved.

〔発明の概要〕[Summary of the invention]

本発明ハ、電流源トランジスタとスイッチトランジスタ
のベース電流を補償することにより、出力電流へのβの
影響を減少させβのばらつきによる精度劣化を改善する
ようにしたものである。
The third aspect of the present invention is to reduce the influence of β on the output current by compensating the base currents of the current source transistor and the switch transistor, thereby improving accuracy deterioration due to variations in β.

〔発明の実施例〕[Embodiments of the invention]

以下1図面を用いて本発明の詳細な説明する。 The present invention will be described in detail below using one drawing.

第4図に本発明で−用いられるベース電流補償回路を示
す。その動作にm流源32の電流をIとすると、ダイオ
ード30,26.hランジメタ28゜1、抵抗27.5
にもほぼIが流れる。ここでトランジスタ31のVBE
31U、 VBE31 = VBE28+VBK29−VBE30
ここで VBE28=VBE30より。
FIG. 4 shows a base current compensation circuit used in the present invention. In its operation, if the current of the m current source 32 is I, the diodes 30, 26 . h range metal 28゜1, resistance 27.5
Almost all I flows through it. Here, VBE of transistor 31
31U, VBE31 = VBE28+VBK29-VBE30
Here, from VBE28=VBE30.

Vl(E31  =  VBE29 となる。さらにトランジスタ29を流れる電流HI/β
 であり、トランジスタ31H)ランジスタ29の2倍
のエミッタ面積とすると(すなわち逆方向飽和電流Is
  は2倍となる)トランジスタ31を流れる電流は2
・(I/β)となる。
Vl (E31 = VBE29. Furthermore, the current HI/β flowing through the transistor 29
, and if the emitter area is twice that of the transistor 29 (transistor 31H) (that is, the reverse saturation current Is
is doubled) The current flowing through the transistor 31 is 2
・(I/β).

一方トランジスタ1のコレクタ電流は(1−1//)・
■であるデジタル・う−一夕により、トランジスタ11
が導通とすると、そのエミッタ電流は。
On the other hand, the collector current of transistor 1 is (1-1//)・
■ Transistor 11
When is conducting, its emitter current is.

2・(■/β)が加算され(1+1/β)・■ となる
・したがって端子23の出力電流工outは。
2・(■/β) is added and becomes (1+1/β)・■ Therefore, the output current of the terminal 23 is.

Iout = (1+1/β01−1/7)となり、2
つのピット間での差電流△Iは。
Iout = (1+1/β01-1/7), 2
The difference current △I between the two pits is.

△エニ(1/β)・(2/β)・(△β/β)となり第
2図、すなわち(1)式に比較して1/β、第3図、す
なわち(2)式に比較して2/β改善される。
△any (1/β)・(2/β)・(△β/β), which is compared to Figure 2, that is, equation (1), and 1/β, and Figure 3, that is, compared to equation (2). It is improved by 2/β.

本発明のDACの一実施例を第5図に示す。これは、は
しご形抵抗網を用いた4ピツ)DACに第4図のベース
補償回路を適用したものである。
An embodiment of the DAC of the present invention is shown in FIG. This is an application of the base compensation circuit shown in FIG. 4 to a 4-pin DAC using a ladder-shaped resistor network.

本発明の他の実施例を第6図に示す。これは、電流源に
、2進重みづけを行なったDACであるトランジスタ3
7.38,39.40  のエミッタ面積は、それぞれ
A:2A:4A:8A(但し、Aはトランジスタ37の
エミッタ面積)の比にし精度をと#)、同様に本発明に
よるベース匿流補償トランジスタ31,45.46.及
び、47と48Fiそれぞれエミツタ面積比、または、
トランジスタの個数により、ベース電流を補償するもの
である。第5.6図の実7II!i例でに全ピント補償
したが必要に応じて上位ビットのみでもよい。また本発
明はビット数によらず適用でき、かつ、電流源の精度を
必要とするすべてのデジタル・アナログ変換器に適用で
きることは明らかである。
Another embodiment of the invention is shown in FIG. This is a transistor 3 which is a DAC with binary weighting applied to the current source.
The emitter areas of 7.38 and 39.40 are the ratios of A: 2 A: 4 A: 8 A (where A is the emitter area of the transistor 37), respectively, and the accuracy is expressed as #). Similarly, the base current compensation transistor according to the present invention 31, 45.46. and the emitter area ratio of 47 and 48Fi, respectively, or
The base current is compensated by the number of transistors. Figure 5.6 Fruit 7II! Although all focus compensation was performed in example i, only the upper bits may be compensated if necessary. Furthermore, it is clear that the present invention can be applied regardless of the number of bits, and can be applied to all digital-to-analog converters that require precision of the current source.

〔発明の効果〕〔Effect of the invention〕

このように本発明によれば、電流源を構成するトランジ
スタとスイッチを構成するトランジスタのベース電流の
和を、該電流源に加算することによff、DACの出力
電流に及はすトランジスタの電流利得の影響を減少でき
る。すなわち電流利得のばらつきが精度に及はす影響を
減少でき、かつ。
As described above, according to the present invention, by adding the sum of the base currents of the transistors constituting the current source and the transistors constituting the switch to the current source, the current of the transistor that affects the output current of the DAC is calculated as ff. Can reduce the impact of gain. That is, the influence of current gain variations on accuracy can be reduced, and.

・ベース上流補償回路は直流動作する部分で行なわれる
ため、速度劣化の要因とにならず高速動作可能で、精度
のよいデジタル・アナログ変換器を提供できる。
- Since the base upstream compensation circuit is implemented in the part that operates with direct current, it does not cause speed deterioration and can operate at high speed, making it possible to provide a highly accurate digital-to-analog converter.

【図面の簡単な説明】[Brief explanation of drawings]

第1図ははしご形回路網を用いた従来のDAC。 第2図に、第1図の回路の1ビツトを抜粋した図。 第3図id、を流源のベース電流を補償した従来例ぞれ
本発明の一実施例によるDACk示す図である。 9・・・バイアス畦圧印加端子、18.24・・・デジ
タル・データ入力端子群%19・・・はしご形抵抗網。 20.23・・・出力端子% 21,22・・・電源r
九圧印加端子、32・・・電流源。 代理人弁理士 則 近 憲 佑(ほか1名)第1図 第 21     第 3 図 第4図
Figure 1 shows a conventional DAC using a ladder network. FIG. 2 shows an excerpt of one bit of the circuit shown in FIG. FIG. 3 is a diagram illustrating a conventional DAC and an embodiment of the present invention in which the base current of the current source is compensated. 9...Bias ridge pressure application terminal, 18.24...Digital data input terminal group %19...Ladder-shaped resistance network. 20.23...Output terminal% 21,22...Power supply r
9 voltage application terminals, 32... current source. Representative Patent Attorney Kensuke Chika (and 1 other person) Figure 1 Figure 21 Figure 3 Figure 4

Claims (1)

【特許請求の範囲】[Claims] デジタル・アナログ変換器の電流源を構成するトランジ
スタのベース電流と該電流源に接続されたスイッチを構
成するトランジスタのベース電流との和の電流を該電流
源の電流に加算した電流値をもつ電流源を、具備するこ
とを特徴とするデジタル・アナログ変換器。
A current having a current value obtained by adding the sum of the base current of the transistor configuring the current source of the digital-to-analog converter and the base current of the transistor configuring the switch connected to the current source to the current of the current source. A digital-to-analog converter, comprising: a source.
JP22741682A 1982-12-28 1982-12-28 Digital-analog converter Pending JPS59122120A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP22741682A JPS59122120A (en) 1982-12-28 1982-12-28 Digital-analog converter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP22741682A JPS59122120A (en) 1982-12-28 1982-12-28 Digital-analog converter

Publications (1)

Publication Number Publication Date
JPS59122120A true JPS59122120A (en) 1984-07-14

Family

ID=16860495

Family Applications (1)

Application Number Title Priority Date Filing Date
JP22741682A Pending JPS59122120A (en) 1982-12-28 1982-12-28 Digital-analog converter

Country Status (1)

Country Link
JP (1) JPS59122120A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02104026A (en) * 1988-06-27 1990-04-17 Analog Devices Inc <Adi> High speed digital/analog converter
JP2012151728A (en) * 2011-01-20 2012-08-09 Nippon Telegr & Teleph Corp <Ntt> Digital/analog converter

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02104026A (en) * 1988-06-27 1990-04-17 Analog Devices Inc <Adi> High speed digital/analog converter
JP2012151728A (en) * 2011-01-20 2012-08-09 Nippon Telegr & Teleph Corp <Ntt> Digital/analog converter

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