JPH06314977A - Current output type d/a converter circuit - Google Patents

Current output type d/a converter circuit

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Publication number
JPH06314977A
JPH06314977A JP10255193A JP10255193A JPH06314977A JP H06314977 A JPH06314977 A JP H06314977A JP 10255193 A JP10255193 A JP 10255193A JP 10255193 A JP10255193 A JP 10255193A JP H06314977 A JPH06314977 A JP H06314977A
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Prior art keywords
output
current
circuit
resistor
mirror circuit
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JP10255193A
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Japanese (ja)
Inventor
Mitsuhiro Nakajima
光啓 中島
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Nec Ic Microcomput Syst Ltd
日本電気アイシーマイコンシステム株式会社
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Priority to JP10255193A priority Critical patent/JPH06314977A/en
Publication of JPH06314977A publication Critical patent/JPH06314977A/en
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Abstract

PURPOSE: To set the variable range of the output current optional by connecting a reference current source to a 1st current mirror circuit, using an output of a 1st amplifier for a reference potential application point and giving 1st to n-th outputs of a 2nd current mirror circuit to n-sets of weighting terminals of an R-2R resistor ladder circuit.
CONSTITUTION: A current of a reference current source 1 is given to a 1st current mirror circuit comprising transistors(TRs) 2-3 and resistors 5-7, its 1st output is inputted to a current-voltage circuit comprising a resistor 9 and an amplifier 8, in which the output is converted into a voltage and it is used for a reference voltage for an R-2R ladder circuit comprising resistors 24-29. A 2nd output of the 1st current mirror circuit is given to a 2nd current mirror circuit having n-sets of outputs comprising TRs 10-14 and resistors 15-19 and n-sets of outputs are given to n-sets of control current terminals to the R-2R resistor ladder circuit via switches 20-23 to decide an output voltage of the R-2R resistor ladder circuit.
COPYRIGHT: (C)1994,JPO

Description

【発明の詳細な説明】 DETAILED DESCRIPTION OF THE INVENTION

【0001】 [0001]

【産業上の利用分野】本発明はデジタル/アナログ変換回路に関し、特に電流出力型デジタル/アナログ変換回路に関する。 The present invention relates to an digital / analog converter, and more particularly to a current output type digital / analog converter circuit.

【0002】一般に、電流出力型デジタル/アナログ変換回路として入力された基準電流をもとにし、デジタル入力信号で出力電流を制御する回路がある。 [0002] Generally, a reference current input as a current output type digital / analog converter circuit Motonishi, there is a circuit for controlling the output current at the digital input signal.

【0003】従来の電流出力型デジタル/アナログ変換回路の一例を図2に示す。 [0003] One example of a conventional current-output type digital / analog converter circuit shown in FIG.

【0004】図において同一形状のトランジスタ36とトランジスタ37,同一抵抗値の抵抗38と抵抗39で構成し、抵抗38と抵抗39の一方の端子は電源端子に接続した第1のカレントミラー回路で、前記カレントミラー回路の入力は基準電流源1に接続し、出力は第2のカレントミラー回路の入力に接続する。 [0004] In the first current mirror circuit transistor 36 and the transistor 37 of the same shape, and a resistor 38 and a resistor 39 having the same resistance value, one terminal of the resistor 38 and the resistor 39 is connected to the power supply terminal in the diagram, the input of the current mirror circuit is connected to the reference current source 1, the output is connected to an input of the second current mirror circuit.

【0005】第2のカレントミラー回路は、カレントミラー回路の入力となるトランジスタ40と抵抗45を通し接地し、第1の出力はトランジスタ40と同一のトランジスタ41と抵抗45と同一抵抗値の抵抗46とデジタル入力信号の第1のビットで制御するスイッチ20で接地した回路で構成する基準電流源と同じ電流を出力し、第2の出力はトランジスタ40の2倍の面積のトランジスタ42と抵抗45の1/2の値の抵抗47とデジタル入力信号の第2のビットで制御するスイッチ21で接地した回路で構成し、基準電流源の2倍の電流を出力し、第3の出力はトランジスタ40の4倍の面積を持つトランジスタ43と抵抗45の1/4の抵抗値の抵抗4 [0005] The second current mirror circuit, is grounded through a transistor 40 and a resistor 45 as an input of the current mirror circuit, the resistance of the first output transistor 40 equal resistance value and the same transistor 41 and the resistor 45 and 46 and outputting the same current as the reference current source constituting a circuit is grounded by the switch 20 controlled by the first bit of the digital input signal, a second output is twice the area transistor 42 and the resistor 45 of transistor 40 and a circuit to grounded by the switch 21 controlled by the second bit of the resistor 47 and the digital input signal of half the value, and outputs a 2-fold current of the reference current source, the third output of the transistor 40 four times the resistance of the 1/4 of the resistance value of the transistor 43 and the resistor 45 having an area 4
8とデジタル入力信号の第3のビットで制御するスイッチ22で接地した回路で構成し基準電流源の4倍の電流を出力し、同様に第nの出力はトランジスタ40の2 8 and 2 digital controlled by the third bit of the input signal is constituted by a circuit which is grounded by the switch 22 outputs the four times the current of the reference current source, as well as the output of the n-th transistor 40
n-1倍の面積を持つトランジスタ44と抵抗45の2 2 of the transistor 44 and the resistor 45 having n-1 times the area
n-1分の1の抵抗値の抵抗49とデジタル入力信号の第nのビットで制御するスイッチ23で接地した回路で構成し基準電流源の2 n-1倍の電流を出力する回路で構成し、第2のカレントミラー回路の第1の出力から第nの出力までを全てに接続する出力端子を有している。 a circuit to output a 2 n-1 times the current of the reference current source constituted by a circuit that is grounded at the switch 23 for controlling a bit of the n (n-1) one-resistor 49 and the digital input signal of the resistance value and has an output terminal connected to all the first output of the second current mirror circuit to the output of the n.

【0006】次に、従来例の動作について説明する。 [0006] Next, a description will be given of the operation of the conventional example.

【0007】n個のビットで構成するデジタル入力信号を各々のスイッチに入力し、第1のビットの信号のみがHになるとスイッチ20がONして出力端子に基準電流源と同じ電流が流れ、第2のビットの信号のみがHになるとスイッチ21がONして出力端子に基準電流源の2 [0007] receives the digital input signal composed of n bits to each of the switches, the same current flows to the reference current source to the first only the signal of the bit becomes H when the switch 20 turns ON the output terminal, 2 of the only two bits of the signal becomes H when the reference current source to the output terminal switch 21 is turned oN
倍の電流が流れ、第1のビットと第2のビットが同時にONすれば出力端子に基準電流源の3倍の電流が流れる。 Times larger current flows, three times the current of the reference current source flows to the output terminal when the first bit and the second bit is ON at the same time. 同様にn個のビットの全てがONすれば2 n −1倍の電流が出力端子に流れるデジタル/アナログ変換回路である。 Similarly all n bits are digital / analog conversion circuit flowing through the 2 n -1 times the current output terminal when ON.

【0008】したがって出力端子に流れる電流をI OUT [0008] Therefore, the current flowing to the output terminal I OUT
とし、基準電流源の電流値をIrefとすると次式で表わすことができる。 And then, when the current value of the reference current source and Iref can be expressed by the following equation.

【0009】I OUT =I ref (Z 1 +2Z 2 +4Z 3 [0009] I OUT = I ref (Z 1 + 2Z 2 + 4Z 3 +
…+2 n-1n ) Z nは第nのビットがON時1、OFF時0を代入する。 ... + the 2 n-1 Z n) Z n bits of the n is substituted for ON time 1, OFF time 0.

【0010】 [0010]

【発明が解決しようとする課題】この従来の電流出力型デジタル/アナログ変換回路では、基準電流源の電流値を元に整数倍の電流値の制御しかできず、可変範囲を任意に選べず、また可変する電流値は基準電流源の電流値により限定される問題がある。 BRIEF Problem to be Solved] In this conventional current-output type digital / analog conversion circuit, based on the current value of the reference current source can only control the integer multiple of the current value, not arbitrarily choose a variable range, the current value of the variable has a problem to be limited by the current value of the reference current source.

【0011】又、出力電流のリニアリティを得る為には、カレントミラー回路を構成するトランジスタの面積比が重要となり、デジタル入力信号のビットが多くなるとカレントミラー回路を構成するトランジスタが指数的に増加し、又微少な範囲を可変する為には、基準電流源の電流値が少なくする必要があり、カレントミラー回路を構成する抵抗値が大きくなると言う問題がある。 [0011] Further, in order to obtain a linearity of the output current, the area ratio of the transistors constituting the current mirror circuit is important, the bits of the digital input signal becomes many transistors constituting the current mirror circuit increases exponentially with also in order to vary the minute range, should the current value of the reference current source is small, there is a problem that the resistance value of the current mirror circuit increases.

【0012】次に実際の値を入れて詳細に説明すると、 [0012] Next will be described in detail to put the actual value,
4個のビットのデジタル入力信号により出力電流値を1 4 bits of the output current value by a digital input signal 1
5μAから30μAの間で可変する電流入力−電流出力型デジタル/アナログ変換回路を考える。 Current input variable between 30μA from 5 .mu.A - considering the current output type digital / analog converter circuit.

【0013】4個のビットのデジタル入力信号は16ステップの設定となる為、可変する電流値を可変ステップで割ると1ステップ当り1μAの変化が必要となり、これを基準電流源の電流値とするが、このままだと0μA [0013] 4 pieces of the digital input signal bits for a set of 16 steps, the change in one step per 1μA Dividing the value of the current variable a variable step is required, this is the current value of the reference current source 0μA but that it in this state
から15μAまでの可変しかできない為、基準電流源以外に15μAの電流源を出力端子に接続する必要があり、この2個目の電流源を使用することにより15μA Because can only variable to 15 .mu.A from, it is necessary to connect the current source 15 .mu.A than the threshold current source to the output terminal, 15 .mu.A By using this two second current sources
から30μAまでの可変が可能となる。 Variable from up to 30μA is possible.

【0014】次にカレントミラー回路を構成する抵抗値について考えると、ICの内部で使用する場合、トランジスタや抵抗のバラツキを考えると抵抗の両端に発生する電圧を0.3V程度に設定する必要があり、基準電流源の電流値が1μAとすると第1のカレントミラー回路では300KΩの抵抗が2本必要となる。 [0014] Next considering the resistance value of a current mirror circuit, when used in internal IC, it is necessary to set the voltage generated across the considered resistivity variations in transistors and resistors on the order of 0.3V There, the current value of the reference current source resistor of 300KΩ is required two in the first current mirror circuit when the 1 .mu.A.

【0015】又、第2のカレントミラー回路でも300 [0015] In addition, 300 in the second current mirror circuit
KΩの抵抗が2本、150KΩの抵抗が1本、など高抵抗値の抵抗が数多く必要となり、ICでの使用には無理がある。 Two resistors of KΩ is, the resistance of 150KΩ is required a number of single resistor, such as a high resistance value, it is unreasonable for use in IC.

【0016】 [0016]

【課題を解決するための手段】本発明の電流出力型デジタル/アナログ変換回路は基準電流源を、2つの出力を持つ第1のカレントミラー回路の入力となる第1のトランジスタのコレクタに接続し、前記第1のカレントミラー回路を構成する3個のトランジスタのエミッタは抵抗を介して電源端子に接続され、第1の出力は第1の増幅器と第1の抵抗とで構成される電流−電圧変換回路の入力に接続され、前記第1の抵抗は接地され基準電流と抵抗値を乗算した電圧を発生し、増幅率1倍の第1の増幅器を通してR−2R抵抗ラダー回路の等電位端子として入力される。 Current output type digital / analog converter circuit of the present invention According to an aspect of the reference current source, connected to the collector of the first transistor serving as the input of the first current mirror circuit with two outputs said first emitter of three transistors constituting the current mirror circuit is connected to a power supply terminal via a resistor, the first output is composed of the first amplifier and a first resistor current - voltage is connected to the input of the conversion circuit, as equipotential terminal of the first resistor generates a voltage obtained by multiplying the resistance value between the grounded reference current, R-2R resistor ladder circuit through a first amplifier amplification factor 1 times It is input.

【0017】前記第1のカレントミラー回路の第2の出力はn個の出力を持つ第2のカレントミラー回路の入力となる第2のトランジスタのコレクタに接続され、前記第2のカレントミラー回路の入力を構成する前記第2のトランジスタのエミッタは第2の抵抗を介して接地され、第1の出力を構成する第3のトランジスタは第3の抵抗とデジタル入力信号の第1のビットで制御する第1 [0017] The second output of the first current mirror circuit is connected to the collector of the second transistor serving as the input of the second current mirror circuit having n outputs, the second current mirror circuit the emitter of the second transistor constituting the input is grounded through a second resistor, a third transistor constituting the first output is controlled by the first bit of the third resistor and the digital input signal first
のスイッチで接地し、第2の出力を構成する第4のトランジスタは第4の抵抗と前記デジタル入力信号の第2のビットで制御する第2のスイッチで接地し、同様に第n Grounded at the switch, the fourth transistor constituting the second output is grounded at a second switch controlled by the second bit of the digital input signal and the fourth resistor, similarly the n
の出力を構成する第5のトランジスタは第5の抵抗と前記デジタル入力信号の第nのビットで制御する第nのスイッチで接地され前記第2のカレントミラー回路の第1 The first fifth transistor constituting the output of the first n is grounded by switches said second current mirror circuit controlled by the bit of the first n of the fifth resistor and the digital input signal
の出力から第nの出力までは前記R−2R抵抗ラダー回路のn個の重み付け端子に入力される。 From the output to the output of the n input to the n weighting terminal of said R-2R resistor ladder circuit.

【0018】前記R−2R抵抗ラダー回路の出力は第2 [0018] The output of the R-2R resistor ladder circuit and the second
の増幅器の非反転入力に接続し、前記第2の増幅器は、 'S connected to the non-inverting input of the amplifier, the second amplifier,
出力を第6のトランジスタのベースに入力し、前記第6 Inputs the output to the base of the sixth transistor, said sixth
のトランジスタのエミッタは、前記第2の増幅器の反転入力に接続するのと第6の抵抗を介して接地し、電圧− The emitter of the transistor is grounded via a resistor and a sixth to connect to the inverting input of the second amplifier, the voltage -
電流変換回路を構成し、前記トランジスタのコレクタは出力端子に接続する電圧−電流変換回路を備えている。 Constitute a current conversion circuit, the collector of the transistor is voltage connected to the output terminal - has a current converter circuit.

【0019】 [0019]

【実施例】次に、本発明について図面を参照して説明する。 EXAMPLES Next, will be described with reference to the drawings the present invention.

【0020】図1は本発明の一実施例を示す回路図である。 [0020] FIG. 1 is a circuit diagram showing an embodiment of the present invention.

【0021】基準電流源1の電流をトランジスタ2, [0021] The reference current source 1 of the current transistor 2,
3,4と抵抗5,6,7で構成する2個の出力を持つ第1のカレントミラー回路の入力に接続し、前記第1のカレントミラー回路の第1の出力より抵抗9と増幅器8で構成する電流−電圧回路に入力して電圧に変換し、抵抗24から抵抗29で構成するR−2R抵抗ラダー回路の基準電圧とする。 Connected to the input of the first current mirror circuit having two outputs consist of 3, 4 and resistor 5, 6, 7, a first output from the resistor 9 and the amplifier 8 of the first current mirror circuit current configure - converted into a voltage by inputting the voltage circuit, a reference voltage of the R-2R resistor ladder circuit to a resistor 29 from the resistor 24.

【0022】基準電流源1の電流値をI refとし、電流−電圧回路の出力の電圧をV refとすると V ref =R9×I refとなる。 [0022] The current value of the reference current source 1 and I ref, current - becomes the voltage of the output of the voltage circuit to V ref and V ref = R9 × I ref.

【0023】次に、前記第1のカレントミラー回路の第2の出力はトランジスタ10からトランジスタ14と抵抗15から抵抗19で構成するn個の出力を持つ第2のカレントミラー回路の入力に接続し、そのn個の出力はデジタル入力信号で制御されるスイッチ20からスイッチ23によって前記R−2R抵抗ラダー回路へのn個のコントロール電流端子に入力し、R−2R抵抗ラダー回路の出力電圧を決める。 Next, connect the input of the second current mirror circuit having n outputs a second output of said first current mirror circuit composed of the resistor 19 from the transistor 14 and the resistor 15 from the transistor 10 , its n outputs are inputted from the switch 20 which is controlled by the digital input signal into n control current terminal to said R-2R resistor ladder circuit by the switch 23 determines the output voltage of the R-2R resistor ladder circuit .

【0024】R−2R抵抗ラダー回路の基準抵抗値をR [0024] The reference resistance value of the R-2R resistor ladder circuit R
とするとR−2R抵抗ラダー回路の出力電圧V R-2Rは V R-2R =V ref −R×I ref ×(Z n +…+Z 2 /2 When the output voltage V R-2R of R-2R resistor ladder circuit is V R-2R = V ref -R × I ref × (Z n + ... + Z 2/2
n-1 +Z 1 /2 n ) Z nは第nのビットがON時1、OFF時0を代入する。 n-1 + Z 1/2 n) Z n substitutes bit time ON 1, OFF time 0 in the n. となる。 To become.

【0025】R−2R抵抗ラダー回路の出力は増幅器3 The output of the R-2R resistor ladder circuit amplifier 3
0,トランジスタ31と抵抗32で構成する電圧−電流回路の入力に接続され、トランジスタ31のコレクタは出力端子に接続し電流出力型デジタル/アナログ変換回路を構成する。 0, voltage a transistor 31 and the resistor 32 - is connected to the input of the current circuit, the collector of the transistor 31 constitutes a connection to a current output type digital / analog converter to the output terminal.

【0026】この回路の出力電流I outは次の式で求まる。 The output current I out of this circuit is determined by the following formula.

【0027】I OUT =V R-2R /R32 =(R9/R32)I ref −(R/R32)I ref (Z [0027] I OUT = V R-2R / R32 = (R9 / R32) I ref - (R / R32) I ref (Z
n +…+Z 2 /2 n-1 +Z 1 /2 n ) 従来例で説明した、4個のビットのデジタル入力信号により、出力電流値を15μAから30μAの間で可変する電流出力型デジタル/アナログ変換回路を考える。 n + ... + Z 2/2 n-1 + Z 1/2 n) described in the conventional example, the four-bit digital input signal, the current output type digital / analog variable between the output current value from 15μA to 30μA Given the conversion circuit.

【0028】まず出力電流の最大電流値30μAは、次の式で求まる。 [0028] First, the maximum current value 30μA of the output current is determined by the following formula.

【0029】I out =(R9/R32)I refここで基準電流源の電流値を60μAとし、電流−電圧変換回路の出力電圧を3.6Vとすると R9=60KΩ,R32=120KΩ となる。 [0029] The current value of I out = (R9 / R32) I ref where reference current source and 60 .mu.A, current - if the output voltage of the voltage converting circuit and 3.6V R9 = 60KΩ, the R32 = 120k.

【0030】次に出力電流の最小電流値15μAは、次の式で求まる。 [0030] Then the minimum current value 15μA output current determined by the following equation.

【0031】I out =(R9/R32)I ref −(R/ [0031] I out = (R9 / R32) I ref - (R /
R32)I ref (8/15) R=16KΩ となる。 R32) the I ref (8/15) R = 16KΩ . 又カレントミラー回路を構成する抵抗は、5K The resistors constituting a current mirror circuit, 5K
Ωとなり、ICでの使用でも問題ない値である。 Next Ω, it is no problem value in use in IC.

【0032】 [0032]

【発明の効果】以上説明したように本発明は、基準電流源の電流値に関係なく、出力端子の電流値を決めることができる様にしたので、出力電流の可変範囲を任意に設定することができ、又、デジタル入力信号のビット数が増えても、微少な範囲の可変に対しても、トランジスタの個数や抵抗の値を小さくすることができ、IC化においてチップの縮小に対して効果があるという結果を有する。 The present invention described above, according to the present invention, regardless of the current value of the reference current source, since the manner it is possible to determine the current value of the output terminal, possible to arbitrarily set the variable range of the output current can be, also increasing the number of bits of the digital input signal, even for variable minute range, it is possible to reduce the value number and resistance of the transistor, the effect with respect to the chip shrink in an IC with the result that there is.

【図面の簡単な説明】 BRIEF DESCRIPTION OF THE DRAWINGS

【図1】本発明の実施例の回路図 Circuit diagram of an embodiment of the invention, FIG

【図2】従来の例の回路図 Figure 2 is a circuit diagram of a conventional example

【符号の説明】 DESCRIPTION OF SYMBOLS

1 基準電流源 2〜4,10〜14,31,36〜37,40〜44 1 reference current source 2~4,10~14,31,36~37,40~44
トランジスタ 5〜7,9,15〜19,24〜29,32,38,3 Transistor 5~7,9,15~19,24~29,32,38,3
9,45〜49 抵抗 8,30 増幅器 20〜23 スイッチ 33 入力端子 34 電源端子 35 出力端子 9,45~49 resistance 8,30 amplifier 20-23 switch 33 input terminal 34 power supply terminal 35 Output terminal

Claims (1)

    【特許請求の範囲】 [The claims]
  1. 【請求項1】 基準電流源を、2つの出力を持つ第1のカレントミラー回路の入力に接続し、前記第1のカレントミラー回路の第1の出力は他端が接地された第1の抵抗の一端と第1の増幅器の入力に接続し、該第1の増幅器の出力を基準電位供給点となし、R−2R抵抗ラダー回路の等電位端子を前記、基準電位供給点に接続し、前記第1のカレントミラー回路の第2の出力は、n個の出力を持つ第2のカレントミラー回路の入力に接続し、該入力はエミッタが第2の抵抗を介して接地された第2のトランジスタで構成され、前記第2のカレントミラー回路の第1の出力を構成する第3のトランジスタは第3の抵抗とデジタル入力信号の第1のビットで制御する第1 The method according to claim 1 the reference current source, connected to the input of the first current mirror circuit having two outputs, a first output of said first current mirror circuit a first resistor whose other end is grounded one end and connected to an input of the first amplifier, and connect the reference potential supply point and without the output of the first amplifier, the equipotential terminal of R-2R resistor ladder circuit wherein, the reference potential supply point, wherein a second output of the first current mirror circuit is connected to an input of the second current mirror circuit having n outputs, input a second transistor whose emitter is grounded via a second resistor in the configuration, the third transistor constituting the first output of the second current mirror circuit a first controlled by a first bit of the third resistor and the digital input signal
    のスイッチを介して接地し、第2の出力を構成する第4 Grounded via a switch, a fourth constituting the second output
    のトランジスタは第4の抵抗と前記デジタル入力信号の第2のビットで制御する第2のスイッチを介して接地し、同様に第nの出力を構成する第5のトランジスタは第5の抵抗と前記デジタル入力信号の第nのビットで制御する第nのスイッチを介して接地され、前記第2のカレントミラー回路の第1の出力から第nの出力までは前記R−2R抵抗ラダー回路のn個の重み付け端子に入力され、前記R−2R抵抗ラダー回路の出力は、第6のトランジスタのベースが出力に接続され、エミッタが他端が接地された第6の抵抗の1端とともに反転入力に接続された第2の増幅器の非反転入力に接続し、前記第6のトランジスタのコレクタを電流出力端となすことを特徴とした電流出力型デジタル/アナログ変換回路。 The transistor is grounded via the second switch controlled by the second bit of the digital input signal and the fourth resistor, likewise the fifth transistor constituting the output of the n said fifth resistor is grounded via the switch of the n-th controlled by bits of the n digital input signal, said the first output of the second current mirror circuit to the output of the n n pieces of the R-2R resistor ladder circuit is input to the weighted terminal, the output of R-2R resistor ladder circuit, base of the sixth transistor is connected to the output, connected to the inverting input with one end of the sixth resistor to the emitter has the other end connected to ground inverting and connected to the input, the sixth current output type digital / analog conversion circuit is characterized in that formed between the current output terminal of the collector of the transistor of the second amplifier that is.
JP10255193A 1993-04-28 1993-04-28 Current output type d/a converter circuit Withdrawn JPH06314977A (en)

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Application Number Priority Date Filing Date Title
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JPH06314977A true JPH06314977A (en) 1994-11-08

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