JPH0777352B2 - DA converter - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a DA converter for converting a digital signal into an analog signal, and particularly to reduction of stray capacitance when the DA converter is integrated into a circuit. Regarding

[Conventional technology]

FIG. 2 is a block diagram showing the configuration of a conventional DA converter. The digital signal input from the digital signal input terminal 1 is held in the latch circuit 2 for a certain period of time and then D-
It is provided to the A converter block 3. A clock signal (hereinafter abbreviated as CLK) 50 is given to the latch circuit 2,
Captures digital signals when is “H”. The DA conversion block 3 comprises a current switch circuit 4 and a current source circuit 5. A bias voltage is applied from the bias circuit 6 to the current source circuit 5. The current switch circuit 4 switches according to the digital signal given from the latch circuit 2, and selectively causes the current generated by the current source circuit 5 to flow through the resistor 7. Then, an analog signal corresponding to the voltage drop generated in the resistor 7 is output to the analog signal output terminal 8.

FIG. 3 is a circuit diagram showing a specific circuit configuration of the DA conversion block 3. Although only the least significant bit A and the most significant bit Z are shown in this figure, there are bits having similar circuit configurations in the middle. The least significant bit A is a differential pair NPN transistor Q1, Q2 that constitutes the current switch circuit 4,
The current source circuit 5 comprises an NPN transistor Q3 and a resistor 13. A latch circuit 2 is provided at the base of the transistors Q1 and Q2.
From the digital signal input terminals 11 and 12, digital signals having opposite polarities are applied. In the transistor Q3, the collector is connected to the common emitter connection point of the transistors Q1 and Q2, the emitter is grounded via the resistor 13, and the bias voltage applied to the base from the bias circuit 6 via the bias terminal 14 is applied. Apply the corresponding current. C1
Indicates stray capacitance generated in the collector of the transistor Q3.

The most significant bit Z is also a differential pair that constitutes the current switch circuit 4.
It is composed of NPN transistors Q4 and Q5, an NPN transistor Q6 which constitutes the current source circuit 5, and a resistor 17. The connection relation of these elements is similar to that shown in the least significant bit A. C2 represents a stray capacitance generated in the collector of the transistor Q6.

Next, the operation will be described. It is now assumed that the latch circuit 2 is supplied with CLK50 as shown in FIG. 4 (a) and the digital signal input terminal 1 is supplied with a digital signal as shown in FIG. 4 (b). The latch circuit 2 latches the level of the digital signal at the rising edge of CLK50 with a delay of a fixed time and gives it to the digital signal input terminals 11, 12, 15 and 16. Digital signal input terminals 11 and 12, 15 and 16 are supplied with signals of opposite phases as shown in FIG. 4 (c), and the transistors Q1 to Q4 are turned on / off according to this signal,
The current path of the current flowing through the transistors Q3 and Q6, which are the current source circuit 5, is switched, the current flowing through the resistor 7 changes, and the analog signal corresponding thereto is output to the analog signal output terminal 8.

A bias voltage is applied to the bases of the transistors Q3 and Q6 from the bias circuit 6, and a current corresponding to this voltage flows through the transistors Q3 and Q6. Now, set the bias voltage to V ₁₄ ,
The current flowing through the transistor Q3 is I, and the resistance value of the resistor 13 is R
₁₃ , the base-emitter voltage of the transistor Q3 is V _BE3 , V ₁₄ = V _BE3 + I · R ₁₃ (1) Generally, in the N-bit D / A converter, the current I ₆ flowing through the transistor Q6 of the most significant bit Z is I ₆ = 2 ^{N -1} × I. It is generally well known that to realize this current ratio, the emitter area ratio of transistors Q3 and Q6 must be 2 ^N-1 and the resistance ratio of resistors 13 and 15 must be 1/2 ^N-1. There is. In general, the current flowing in a transistor is A _e × I _S × exp (q · V _BE / kT) A _e : emitter area coefficient I _S : reverse saturation current per unit area q: electron charge V _BE : transistor The base-emitter voltage of T: absolute temperature k: Boltzmann constant.

Here, the structure of the transistor having the emitter area ratio as described above will be described. FIG. 5 is a diagram for explaining the structure of the transistor Q1, of which FIG. 5 (a)
Is a plan view, and FIG. 5 (b) is a sectional view taken along the line AA in the plan view. In the plan view shown in FIG. 5 (a), the base region 26a surrounds the emitter region 25a and the base region 26a.
A collector region 27a is provided in a region different from the above region, and an isolation region 28a is provided so as to surround these regions.

In the sectional view shown in FIG. 5 (b), n ^{+ is formed} on the P-type substrate 30.
A buried layer 31, n ^- epitaxial layer 32 is formed. n ^-
A base region 26a made of a P diffusion region is formed on a part of the epitaxial layer 32. n ^- epitaxial layer 32
An isolation region 28a composed of ap ⁺ diffusion layer is formed with the p ⁺ diffusion layer interposed therebetween.

In general, the lowest potential (eg, ground potential) is applied to the substrate 30, so that the isolation region 28a also has the lowest potential. Further, the n ⁻ epitaxial layer 32 and the n ⁺ buried layer 31 have the same potential as the collector region 27a. Therefore, a reverse bias is applied to the junction between the n ⁺ buried layer 31 and the substrate 30, the junction between the n ⁻ epitaxial layer 32 and the isolation region 28a, and the junction between the n ⁻ epitaxial layer 32 and the substrate 30, and the depletion layer from the respective boundaries. Spreads. This depletion layer becomes the stray capacitance C1. The size of the stray capacitance C1 is such that the junction area between the n ⁻ epitaxial layer 32 and the isolation region 28a and the substrate 30 is n ^+.
Considering that it is much larger than that of the buried layer 31 and the substrate 30, it is almost proportional to the sum of the side area and the bottom area of the n ⁻ epitaxial layer 32.

FIG. 6 is a plan view when the transistor Q6 is integrated into a circuit. The easiest way to increase the emitter area ratio of transistor Q6 by 2 ^N-1 times that of transistor Q3 is to simply arrange 2 ^N-1 transistors Q3 in parallel, but this increases the area. Generally, the sixth
As shown in the figure, the transistor Q3
A plurality of emitter regions 25b having the same shape as the emitter region 25a are arranged, a collector region 27b is provided in a region different from the base region 25b, and a separation region 28b is provided so as to surround these regions. In this way, the bottom area and side area of the n ⁻ epitaxial layer 32 are smaller and the stray capacitance can be reduced as compared with the case where a plurality of transistors Q3 are arranged in parallel. However, it is apparent that the transistor Q6 has a larger side area and bottom area of the n ⁻ epitaxial layer 32 than the shape of the transistor Q3 shown in FIG. Therefore, the stray capacitance C2 of the transistor Q6 is larger than the stray capacitance C1 of the transistor Q3.

Since the digital signal is taken in by the latch circuit 2 in synchronization with the rising edge of CLK50 as described above, the high frequency component (edge portion) of CLK50 leaks to the output digital signal due to capacitive coupling inside the latch circuit 2. (N1 in FIG. 4 (c)), however, a high frequency component (edge portion) of the input digital signal leaks to the output digital signal (N2 in FIG. 4 (c)). Switching the differential transistors Q1, Q2, and Q4, Q5 with this digital signal,
A high-frequency current will flow in the stray capacitance (= stray capacitance of the collectors of transistors Q3 and Q6) attached to the common emitter of the differential transistors. Then, the high-frequency current also flows through the load resistor 7, and a voltage output corresponding to it also appears at the analog signal output terminal 8 (N3 in FIG. 4 (d)). This unnecessary voltage output is due to the size of the capacitive coupling in the latch circuit 2 and the stray capacitance attached to the common emitter of the differential transistor (the n ^- epitaxial layer 32 of the transistors Q3 and Q6 forming the current source circuit 5 as described above). (Determined by side area and bottom area). Also, CLK50
And the rising speed of the edge portion of the digital signal.

[Problems to be Solved by the Invention]

Since the conventional DA converter is configured as described above, when the number of bits is increased or the size of the transistor Q3 which is the reference forming the current source circuit 5 is increased,
The size of the other transistors forming the current source circuit 5 also increases, and the side area and bottom area of the n ⁻ epitaxial layer 32 of these transistors increase. As a result, there is a problem that the stray capacitance becomes large, and the degree to which an unnecessary signal such as clock noise leaks into the analog signal to the output terminal 8 becomes large.

The present invention has been made in order to solve the above-mentioned problems, and DA which prevents unnecessary signals from leaking to analog signals.
The purpose is to obtain a converter.

[Means for Solving the Problems]

A DA converter according to the present invention includes a plurality of current sources each including a bipolar transistor having a different size, a current source for deriving a current according to the size, and a plurality of current sources connected to each of the plurality of current sources. Of the differential pair bipolar transistor to which each digital signal is applied, and the current source is configured in a DA converter including a plurality of current changeover switches for switching the current source according to the digital signal. Of the bipolar transistors of different sizes, the bipolar transistor of the same size as the transistor of the smaller size is directly connected between the emitter common connection point of the plurality of differential pair bipolar transistors and the current source.

[Action]

According to the present invention, among the transistors of different sizes forming the current source, the transistor of the same size as the transistor of the smaller size is connected in series between the common emitter connection point of the plurality of differential pair transistors and the current source. , The stray capacitance generated at the common node of the emitters of the differential pair transistors is reduced.

〔Example〕

FIG. 1 is a circuit diagram showing an embodiment of a DA converter according to the present invention. In the figure, the difference from the conventional circuit shown in FIG. 3 is that the transistor Q1, Q2 has a common emitter connection point and the transistor Q3 has a collector, and the transistors Q4, Q5 have a common emitter connection point and the transistor Q6 has a collector. NPN transistor Q10, Q20 with the same size as Q3
Is provided respectively. The transistor Q10 has a collector connected to a common connection point of the emitters of the transistors Q1 and Q2, an emitter connected to the collector of the transistor Q3, and a base connected to the bias terminal 100. The transistor Q20 has a collector connected to a common connection point of the emitters of the transistors Q4 and Q5, an emitter connected to the collector of the transistor Q6, and a base connected to the bias terminal 100. Other configurations are the same as the conventional one.

Next, the operation will be described. An appropriate bias voltage is applied to each of the bias terminals 14 and 100 from the bias circuit 6. Then, the digital signal input terminals 11 and 12, 15 and 16
In the same manner as in the conventional case, the latch circuit 2 supplies a signal having an opposite phase. Transistors Q1, Q2, Q4 and Q5 are selectively turned on in the same manner as in the prior art in accordance with the applied signals, and an analog signal is output from analog signal output terminal 8 via resistor 7.

Since the transistors Q10 and Q20 have the same size as the transistor Q35, the side area and bottom area of the n ⁻ epitaxial layer 32 are
It is much smaller than that of transistor Q6 (see Fig. 4). Therefore, the stray capacitance C2 generated at the collector of the transistor Q20 is significantly reduced as compared with that of the transistor Q6. That is, the stray capacitance generated at the common emitter connection point of the transistors Q4 and Q5 can be reduced. Even if the transistors Q10 and Q20 are the same size as the transistor Q3, the base voltage of the transistors Q10 and Q20 is set to a value that does not limit the current flowing in the transistors Q10 and Q20, that is, a value that does not saturate the transistors Q3 and Q6. To be done. Therefore, the transistors Q10 and Q20 transmit the currents flowing in the transistors Q3 and Q6, to be precise, the currents obtained by subtracting the base currents of the transistors Q10 and Q20, to the differential pair transistors Q1 and Q2 as they are. Further, the base currents of the transistors Q10 and Q20 have a large current amplification factor and thus can be ignored, and the ratio of the currents flowing through the transistors Q3 and Q6 is the same as the conventional one.

Further, also in the DA conversion block in each intermediate bit (not shown), the emitter common connection point of the differential pair transistors forming the current switch circuit 4 and the current source circuit 5 are connected.
Transistor Q3 between the collectors of the transistors that make up
By connecting a transistor of the same size as the above, the stray capacitance generated at the common connection point of the emitters of the differential pair transistors forming the current switch circuit 4 is significantly reduced.

As a result, even if a digital signal having high frequency noise is input to the digital signal input terminals 11, 12, 15 and 16, the noise leaks less to the analog signal output to the output terminal 8 and unnecessary signals An analog signal that does not have is obtained.

In the above embodiment, the size of the transistors Q10 and Q20 is set to be the same as that of the transistor Q3, which is the smallest size of the transistors forming the current source circuit.
Any size transistor can be used as long as it is smaller than Q6.

〔The invention's effect〕

As described above, according to the present invention, a bipolar transistor of the same size as a small size transistor among the bipolar transistors of different sizes forming the current source is connected to the emitter common connection point of the plurality of differential pair bipolar transistors and the current source. Since each of them is connected in series, the stray capacitance generated at the common emitter connection point of the differential pair bipolar transistor is reduced, and as a result, the high frequency noise included in the digital signal is less likely to leak to the analog signal output. There is.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of a D-A converter according to the present invention, FIG. 2 is a block diagram showing a configuration of a conventional D-A converter, and FIG. 3 is a conventional D-A converter. FIG. 4 is a circuit diagram showing a D-A conversion block of the circuit, FIG. 4 is a diagram for explaining the circuit operation shown in FIG. 3, and FIG. 5 is a current source circuit in the circuit shown in FIG. The figure which shows the structure at the time of integrating the transistor of the minimum size among transistors into an integrated circuit, 6th
The drawing is a plan view of the transistor of the largest size among the transistors forming the current source circuit in the circuit shown in FIG. In the figure, (Q1, Q2) and (Q4, Q5) are differential pair transistors, Q3 and Q6 are current source transistors, 11, 12, 15 and 16 are digital signal input terminals, and Q10 and Q20 are NPN transistors. is there. In the drawings, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Claims] 1. A plurality of current sources, each including a bipolar transistor of a different size, for deriving a current in accordance with the size, and an emitter common connection point connected to each of the plurality of current sources, and having two inputs of opposite phase. A D / A converter comprising a differential pair bipolar transistor to which digital signals are respectively applied, and a plurality of current changeover switches for switching the current sources according to the digital signals, in which the size of the current sources is configured. D-type bipolar transistors of the same size are connected in series between the common emitter connection points of the plurality of differential pair bipolar transistors and the current source. A converter.