JPS593606Y2 - Complementary differential amplifier circuit - Google Patents

Complementary differential amplifier circuit

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Publication number
JPS593606Y2
JPS593606Y2 JP8299779U JP8299779U JPS593606Y2 JP S593606 Y2 JPS593606 Y2 JP S593606Y2 JP 8299779 U JP8299779 U JP 8299779U JP 8299779 U JP8299779 U JP 8299779U JP S593606 Y2 JPS593606 Y2 JP S593606Y2
Authority
JP
Japan
Prior art keywords
transistors
transistor
amplifier circuit
differential amplifier
collector
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP8299779U
Other languages
Japanese (ja)
Other versions
JPS562621U (en
Inventor
隆一 福田
Original Assignee
日本コロムビア株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日本コロムビア株式会社 filed Critical 日本コロムビア株式会社
Priority to JP8299779U priority Critical patent/JPS593606Y2/en
Publication of JPS562621U publication Critical patent/JPS562621U/ja
Application granted granted Critical
Publication of JPS593606Y2 publication Critical patent/JPS593606Y2/en
Expired legal-status Critical Current

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Description

【考案の詳細な説明】 本考案は相補特性を有する差動増幅回路の改良に関する
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an improvement of a differential amplifier circuit having complementary characteristics.

従来例を第1図に示す。図に於いて互いに相補特性を有
するNPN)ランジスタ3,4とPNP)ランジスタ5
,6のそれぞれのベースは、NPN)ランジスタ3とP
NP)ランジスタ5及びNPNトランジスタ4とPNP
)ランジスタロが共通接続されると共に入力端子1及び
2に接続され、NPN)ランジスタ3と4及びPNP)
ランジスタ5と6のコレクタはそれぞれNPN)ランジ
スタフと8及びPNP)ランジスタ9と10のエミッタ
に接続され、エミッタはそれぞれ共通接続されると共に
定電流源16及び15を介し負電源(−B)及び正電源
(十B)に接続される。
A conventional example is shown in FIG. In the figure, NPN transistors 3 and 4 and PNP transistor 5 have complementary characteristics.
, 6 are NPN) transistors 3 and P
NP) transistor 5 and NPN transistor 4 and PNP
) transistors are commonly connected and connected to input terminals 1 and 2, NPN) transistors 3 and 4 and PNP)
The collectors of transistors 5 and 6 are connected to the emitters of NPN) transistors 8 and PNP) transistors 9 and 10, respectively, and the emitters are connected in common, and the negative power supply (-B) and positive Connected to power supply (10B).

トランジスタ7と8及び9と10のコレクタはそれぞれ
抵抗11と12及び13と14を介し正電源(十B)及
び負電源(−B)に接続され、トランジスタ7と8のベ
ースは共通接続されると共に抵抗17及び定電圧素子1
8を介し正電源(十B)及び接地に接続され、トランジ
スタ9と10のベースは共通接続されると共に抵抗20
及び定電圧素子19を介し負電源(−B)及び接地に接
続される。
The collectors of transistors 7 and 8 and 9 and 10 are connected to a positive power supply (10B) and a negative power supply (-B) via resistors 11 and 12 and 13 and 14, respectively, and the bases of transistors 7 and 8 are commonly connected. together with resistor 17 and constant voltage element 1
The bases of transistors 9 and 10 are connected in common, and the resistor 20
and is connected to the negative power supply (-B) and ground via the constant voltage element 19.

以上の構成に於いて差動トランジスタ3と4及び5と6
のコレクタ電圧は定電圧素子18及び19によって定め
られる為、入力端子1及び2に印加される入力信号の最
大許容入力レベルは該定電圧素子18及び19の電圧に
よって制約されることになる。
In the above configuration, differential transistors 3 and 4 and 5 and 6
Since the collector voltage of is determined by the constant voltage elements 18 and 19, the maximum allowable input level of the input signals applied to the input terminals 1 and 2 is restricted by the voltages of the constant voltage elements 18 and 19.

従って該定電圧素子の電圧は入力信号レベルの大きさを
考慮する為に一般に10〜20V程度とする為、入力端
子1及び2に接続される信号源インピーダンスが高い場
合には、コレクタ遮断電流(IcB。
Therefore, the voltage of the constant voltage element is generally set to about 10 to 20 V in consideration of the magnitude of the input signal level, so when the signal source impedance connected to input terminals 1 and 2 is high, the collector cutoff current ( IcB.

)の値も無視出来ない程度となり、温度ドリフト等の問
題も生じ、又前記差動トランジスタ3、4.5.6はコ
レクタ電圧と電流によって自己発熱し、該発熱による温
度ドリフトも生じるし、該差動トランジスタのコレクタ
ベースの電圧はほぼ入力信号レベルに等しく変化する為
、信号源インピーダンスの高い場合に該トランジスタの
コレクタベース間接合容量(Cob)によるミラー効果
も生じ高域特性の劣化も伴うことになる。
) becomes a non-negligible level, causing problems such as temperature drift, and the differential transistors 3, 4, 5, and 6 self-heat due to the collector voltage and current, and temperature drift occurs due to this heat generation. Since the collector-base voltage of a differential transistor changes approximately equal to the input signal level, when the signal source impedance is high, a mirror effect occurs due to the transistor's collector-base junction capacitance (Cob), which also causes deterioration of high-frequency characteristics. become.

本考案は簡単な回路構成で、コレクタ遮断電流(ICB
O)等によるドリフトが少なく、かつ大きな許容入力信
号レベルを有する低歪率増巾器を提供するもので、第2
図に本考案の一実施例を示す。
The present invention has a simple circuit configuration, and the collector interrupting current (ICB)
This invention provides a low distortion amplifier that has little drift due to factors such as O) and a large allowable input signal level.
The figure shows an embodiment of the present invention.

図に於いて、互いに相補特性を有するPNP)ランジス
タ22とNPN)ランジスタ23及びPNP)ランジス
タ26とNPN)ランジスタ27のベースはそれぞれ対
称に共通接続されると共に入力端子1及び2に接続され
、エミッタは定電流源21と24及び25と28を介し
それぞれ正電源(十B)と負電源(−B)に接続される
と共に、NPN)ランジスタ3とPNP)ランジスタ5
及びNPN)ランジスタ4とPNP)ランジスタロのそ
れぞれのベースに接続される。
In the figure, the bases of a PNP) transistor 22, an NPN) transistor 23, a PNP) transistor 26, and an NPN) transistor 27, which have complementary characteristics, are symmetrically connected in common and connected to input terminals 1 and 2, and the emitters are connected to the positive power supply (10B) and the negative power supply (-B) via constant current sources 21 and 24 and 25 and 28, respectively, and are connected to the NPN) transistor 3 and the PNP) transistor 5.
and NPN) transistor 4 and PNP) transistor 4 are connected to their respective bases.

トランジスタ3と4のエミッタとトランジスタ23と2
7のコレクタは共通接続され、トランジスタ5と6のエ
ミッタとトランジスタ22と26のコレクタは共通接続
され、トランジスタ3と4及び5と6のコレクタはそれ
ぞれ抵抗11と12及び13と14を介し正電源(十B
)及び負電源(−B)に接続される。
Emitters of transistors 3 and 4 and transistors 23 and 2
The collectors of transistors 7 and 7 are commonly connected, the emitters of transistors 5 and 6 and the collectors of transistors 22 and 26 are commonly connected, and the collectors of transistors 3 and 4 and 5 and 6 are connected to the positive power supply through resistors 11 and 12 and 13 and 14, respectively. (10B
) and the negative power supply (-B).

以上の構成に於いて、エミッタホロワトランジスタ22
.23.26.27の動作電流は、それぞれ等しい電流
値(■0)を有する定電流源21.24.25.28に
よって定められ、それぞれ等しい電流値(■0)となる
In the above configuration, the emitter follower transistor 22
.. The operating currents of 23, 26, and 27 are determined by constant current sources 21, 24, 25, and 28, each having an equal current value (■0), and have the same current value (■0).

差動増巾トランジスタ3と4及び5と6の動作電流はそ
れぞれ定電流源24と28の電流値の和、及び定電流源
21と25の電流値の和となり、前記のトランジスタ3
と4及び5と6の特性は等しいから、定電流源の電流値
の和(2・Io)の1/2づつ流れることになり、トラ
ンジスタ3.4.5゜6の動作電流はそれぞれ定電流源
の電流値(■0)に等しくなる。
The operating currents of the differential amplification transistors 3 and 4 and 5 and 6 are the sum of the current values of constant current sources 24 and 28 and the sum of the current values of constant current sources 21 and 25, respectively, and
Since the characteristics of 4, 5, and 6 are the same, 1/2 of the sum of the current values (2・Io) of the constant current sources flows, and the operating currents of transistors 3, 4, 5, and 6 are constant currents. It becomes equal to the source current value (■0).

トランジスタ22と26及び23と27のコレクタベー
ス間電圧はそれぞれのコレクタがトランジスタ5と6及
び3と4の共通エミッタ端に接続されているから、はぼ
OVとなる。
The collector-base voltages of transistors 22 and 26 and 23 and 27 are approximately OV since their respective collectors are connected to the common emitter terminals of transistors 5 and 6 and 3 and 4.

次に入力端子2が接地の状態で入力端子1に正の入力信
号が印加されると、トランジスタ22と23のエミッタ
電位が上昇し、トランジスタ3の電流は増大し、トラン
ジスタ5の電流は減少する。
Next, when a positive input signal is applied to input terminal 1 while input terminal 2 is grounded, the emitter potentials of transistors 22 and 23 rise, the current of transistor 3 increases, and the current of transistor 5 decreases. .

同時にそれぞれ差動接続となっているトランジスタ4の
電流は減少し、トランジスタ6の電流は増大する。
At the same time, the current in transistor 4, which is differentially connected, decreases, and the current in transistor 6 increases.

従ってトランジスタ3と4及び5と6のコレクタにはそ
れぞれ負と正の差動出力が生じ、トランジスタ3,4と
5,6の出力は互いに相補特性を有する。
Therefore, negative and positive differential outputs are generated at the collectors of transistors 3 and 4 and 5 and 6, respectively, and the outputs of transistors 3 and 4 and 5 and 6 have complementary characteristics.

又入力端子1が接地の状態で入力端子2に正の入力信号
が印加されると、上述と同様にしてトランジスタ3と4
及び5と6のコレクタにはそれぞれ正と負の差動出力が
生じ、トランジスタ3,4と5,6の出力は互に相補特
性を有する。
Also, when a positive input signal is applied to input terminal 2 while input terminal 1 is grounded, transistors 3 and 4 are connected in the same way as described above.
Positive and negative differential outputs are generated at the collectors of transistors 3 and 5 and 6, respectively, and the outputs of transistors 3 and 4 and transistors 5 and 6 have complementary characteristics.

従って入力端子1及び2に同相同レベルの入力信号が印
加された場合は、トランジスタ3゜4及び5,6のコレ
クタに出力は生じない。
Therefore, when input signals of the same phase and level are applied to the input terminals 1 and 2, no output is generated at the collectors of the transistors 3, 4, 5, and 6.

この様にトランジスタ3と4及び5と6の出力はそれぞ
れ差動出力で゛あり、トランジスタ3,4と5,6の出
力は相補特性の相補プッシュプル出力が得られ、次段に
接続された相補プッシュプル回路を容易に駆動出来、従
って低歪率である。
In this way, the outputs of transistors 3 and 4 and 5 and 6 are differential outputs, and the outputs of transistors 3 and 4 and 5 and 6 provide complementary push-pull outputs with complementary characteristics, which are connected to the next stage. Complementary push-pull circuits can be easily driven and therefore have low distortion.

次にトランジスタ22.26及び23.27のコレクタ
電位は、入力信号レベルに応じトランジスタ5,6及び
3,4の共通エミッタ端の電位が変化する為、それぞれ
のベース電位に等しく、コレクタベース間電圧は入力信
号の大きさに関係なく常に一定のレベルでほぼOvに保
たれる。
Next, the collector potentials of transistors 22, 26 and 23, 27 are equal to their respective base potentials, and the collector-base voltage is always kept at a constant level, approximately Ov, regardless of the magnitude of the input signal.

従って入力端子1及び2に接続される信号源インピーダ
ンスが高い場合でも、トランジスタ22.26及び23
.27のコレクタベース間接合容量(Cob)によるミ
ラー効果は生じない為高域特性の劣化も生じない。
Therefore, even if the signal source impedance connected to input terminals 1 and 2 is high, transistors 22, 26 and 23
.. Since the mirror effect due to the collector-base junction capacitance (Cob) of No. 27 does not occur, there is no deterioration of high frequency characteristics.

又該トランジスタ22.26.23.27のコレクタエ
ミッタ間印加電圧は0.6 V程度となり自己発熱も極
めて少ない。
Further, the voltage applied between the collector and emitter of the transistor 22, 26, 23, 27 is about 0.6 V, and self-heating is extremely small.

トランジスタ3,4及び5,6のコレクタベース間電圧
は入力信号に応じ大きく変化するが、それぞれのトラン
ジスタの入力回路はトランジスタ22、26及び23.
27のエミッタホロワが接続され、該エミッタホロワの
出力インピーダンスは極めて低い値であり、ミラー効果
は生じない。
Although the collector-base voltages of transistors 3, 4 and 5, 6 vary greatly depending on the input signal, the input circuit of each transistor is composed of transistors 22, 26, 23, .
27 emitter followers are connected, and the output impedance of the emitter followers is a very low value and no mirror effect occurs.

従って上述と同様に高域特性の劣化も生じない。Therefore, similarly to the above, deterioration of high frequency characteristics does not occur.

次にトランジスタのコレクタ遮断電流(ICBO)によ
る影響は、エミッタホロワトランジスタ22゜2B、
23.27のコレクタベース間電圧はほぼOvである為
、コレクタ遮断電流(ICBO)は流れず、もちろん温
度ドリフトも生しないし、差動増巾トランジスタ3.4
,5.、 eのコレクタベース間電圧は高電圧が印加さ
れているが、それぞれの入力回路に接続されたエミッタ
ホロワの出力インピーダンスが極めて低い値であり、若
干のコレクタ遮断電流(ICBO)が存在しても問題は
なく、もちろん該コレクタ遮断電流(ICBO)が温度
ドリフトしても問題は生じない。
Next, the effect of the collector cut-off current (ICBO) of the transistor is the emitter follower transistor 22°2B,
Since the collector-base voltage of 23.27 is approximately Ov, no collector cut-off current (ICBO) flows, and of course no temperature drift occurs, and the differential amplifier transistor 3.4
,5. Although a high voltage is applied to the collector-base voltage of , e, the output impedance of the emitter follower connected to each input circuit is extremely low, so even if there is a slight collector-blocking current (ICBO), there is no problem. Of course, there is no problem even if the collector cut-off current (ICBO) drifts with temperature.

次にトランジスタのVBEの温度ドリフトによる影響は
、トランジスタ22,3,4゜26及ヒ23,5,6,
27ノvBEカソレソレ相殺サレる方向に接続されてい
る為、同一導電型トランジスタ同志及び相補トランジス
タ同志の特性が等しければ、それぞれのVBEが温度ド
リフトしても、ドリフトによる変動はない。
Next, the effect of temperature drift on the VBE of the transistors is as follows:
Since the transistors are connected in such a direction that the VBE of 27V is canceled out, if the characteristics of the transistors of the same conductivity type and the complementary transistors are the same, even if the VBE of each transistor drifts with temperature, there will be no fluctuation due to the drift.

以上の様に本考案によれば簡単な回路構成で、直流安定
性が良く、高域特性の劣化も無く、許容入力信号レベル
の大きな、低歪率増巾器を提供出来る。
As described above, according to the present invention, it is possible to provide a low distortion amplifier with a simple circuit configuration, good DC stability, no deterioration of high frequency characteristics, and a large allowable input signal level.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来例の回路図、第2図は本考案の実施例を示
す回路図である。 1,2、は入力端子、3、4.7、8.23.27はN
PN)ランジスタ、5゜6、9.10.22.26はP
NP)ランジスタ、11.12゜13、14は負荷抵抗
、15.16.21.24.25.2Bは定電流源、1
8.19は定電圧ダイオード。
FIG. 1 is a circuit diagram of a conventional example, and FIG. 2 is a circuit diagram showing an embodiment of the present invention. 1, 2 are input terminals, 3, 4.7, 8.23.27 are N
PN) transistor, 5°6, 9.10.22.26 is P
NP) transistor, 11.12゜13, 14 is load resistance, 15.16.21.24.25.2B is constant current source, 1
8.19 is a constant voltage diode.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 第1及び第2の導電型のトランジスタで構成された第1
及び第2の相補差動増幅回路の各入力回路に、定電流源
により駆動されるそれぞれ第2及び第1の導電型のトラ
ンジスタで構成されたエミッタホロワを接続し、上記各
エミッタホロワを構成する導電型の異なるトランジスタ
のそれぞれ対応する入力回路同志を共通接続すると共に
、第1の差動増幅回路のエミッタに上記エミッタホロワ
を構成する第1の導電型のトランジスタの各コレクタを
接続し、第2の差動増幅回路のエミッタに上記エミッタ
ホロワを構成する第2の導電型のトランジスタの各コレ
クタを接続したことを特徴とする相補差動増幅回路。
A first transistor comprising transistors of first and second conductivity types.
and an emitter follower constituted by a transistor of a second conductivity type and a first conductivity type driven by a constant current source is connected to each input circuit of the second complementary differential amplifier circuit, and the conductivity type constituting each emitter follower is connected to each input circuit of the second complementary differential amplifier circuit. Corresponding input circuits of different transistors are connected in common, and the collectors of the transistors of the first conductivity type constituting the emitter follower are connected to the emitter of the first differential amplifier circuit. 1. A complementary differential amplifier circuit, characterized in that collectors of transistors of a second conductivity type constituting the emitter follower are connected to an emitter of the amplifier circuit.
JP8299779U 1979-06-19 1979-06-19 Complementary differential amplifier circuit Expired JPS593606Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8299779U JPS593606Y2 (en) 1979-06-19 1979-06-19 Complementary differential amplifier circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8299779U JPS593606Y2 (en) 1979-06-19 1979-06-19 Complementary differential amplifier circuit

Publications (2)

Publication Number Publication Date
JPS562621U JPS562621U (en) 1981-01-10
JPS593606Y2 true JPS593606Y2 (en) 1984-02-01

Family

ID=29316210

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8299779U Expired JPS593606Y2 (en) 1979-06-19 1979-06-19 Complementary differential amplifier circuit

Country Status (1)

Country Link
JP (1) JPS593606Y2 (en)

Also Published As

Publication number Publication date
JPS562621U (en) 1981-01-10

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