JP2956609B2 - Bipolar multiplier - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiplier for multiplying two analog signals, and more particularly, to a complete linearized four signal suitable for being constructed on a bipolar semiconductor integrated circuit.
Regarding the quadrant multiplier.

[0002]

2. Description of the Related Art This type of bipolar folded
For example, Japanese Patent Application Laid-Open No.
Reference is made to the description in 46792.

[0003] First, a bipolar transistor model will be described.

The relationship between the collector current and the base-emitter voltage of a transistor follows an exponential law and is expressed by the following equation (1).

[0005]

(Equation 1)

[0006] Here, I _S is the saturation current, V _T is the thermal voltage, denoted as V _T = kT / q. Here, q is a unit electron charge, k is a Boltzmann constant, and T is an absolute temperature.

In the above equation (1), when a transistor having a base-emitter voltage V _{BE1 of} about 600 mV normally operates, the exponent exp (V _BE1 / V _T ) becomes a value of about 10 to “−1”. Can be ignored. Therefore, the relationship between the collector current of the transistor and the base-emitter voltage is given by the following equation (2).

[0008]

(Equation 2)

Referring to FIG. 2, the operation of the conventional bipolar folded multiplier will be described below.
Referring to FIG. 2, the emitter is connected in common to the constant current source I _0, a first input signal voltage V _x input to the npn differential pair transistors Q1, Q2 between the base and the emitter common Connected to the constant current source I ₀ , the npn-type differential pair transistors Q 4 and Q 3 having the first input signal voltage V _x as an input between the bases, and the emitters connected in common to the constant current source I ₀ connected, the differential pair transistor Q1 collector respectively, Q2, and Q3, is connected to the common emitter of Q4, the first input signal voltage V pnp type differential pair transistor _{Q5 y} and the input, Q6 between the base ,
The collectors of the transistors Q1 and Q3 are commonly connected (cross-connected) and connected to a power supply _Vcc via a load resistor RL. The collectors of the transistors Q2 and Q4 are commonly connected (cross-connected) and connected via a load resistor RL. Connected to the power supply _Vcc .

The cross-connected differential pair Q1, Q2 and Q3, Q
In the differential output current of No. 4, ΔI is given by the following equation (3).

[0011]

(Equation 3)

Here, the collector currents I _C5 and I _C6 of the transistors Q5 and Q6 are given by the following equations (4) and (5), respectively.

[0013]

(Equation 4)

The differential output current ΔI in the above equation (3) is represented by the following equation (6), and the same transfer function as that of the Gilbert cell is obtained. That is, a bipolar four-quadrant analog multiplier is obtained.

[0015]

(Equation 5)

[0016]

In analog signal processing, a multiplier is an indispensable function block, and the demand for low-voltage operation has recently been increasing.

In the conventional folded Gilbert cell shown in FIG. 2, in order to pass a signal through the pnp transistor, the frequency characteristics of the multiplier are limited by the frequency characteristics of the pnp transistor, and the high-frequency characteristics are limited. Could not be expected.

Accordingly, the present invention has been made in view of the above circumstances, and has as its object to provide a multiplier which is particularly important in analog signal processing, without sacrificing high-frequency characteristics and operating at low voltage. The object of the present invention is to provide a bipolar multiplier.

[0019]

To achieve the above object, a bipolar multiplier according to the present invention comprises a cross-connected differential pair in which the outputs of a first and a second differential pair are reversely connected to each other; A third differential pair having a constant current source as a respective load, and a current from each of the constant current sources connected to an output of the third differential pair is used for the first and second differential pairs. which was so as to be poured into each of the constant current source pairs
There is . More specifically, the present invention provides that the emitters are commonly connected.
Connected to the first and second constant current sources, respectively.
A first conductivity type in which a first input signal voltage is input between
First and second differential pair transistors,
The collectors of the first and second differential pair transistors are respectively
Are cross-connected and their connection points are each connected via a load element.
Source terminal, the emitters are connected in common, and the third constant
A second input signal voltage is input between the bases connected to the current source
And the collector is not connected to the fourth and fifth constant current sources.
A third differential pair transistor of a first conductivity type,
From the fourth and fifth constant current source sides, the first and second differential pairs
Current flows into the common emitter of each transistor
It is configured as follows.

[0020]

Embodiments of the present invention will be described below. According to a preferred embodiment of the present invention, the emitter is connected in common, connected to a first constant current source, and a first input signal voltage (V _{x in} FIG. 1) is input between bases. The first differential pair transistor (FIG. 1)
Q1, Q2) and a first input signal voltage (FIG. 1) between the bases, the emitters of which are connected in common and connected to a second constant current source.
V _x ) are inputted, and npn-type second differential pair transistors (Q4 and Q3 in FIG. 1) are provided. The collectors of the first and second differential pair transistors are cross-connected, respectively, (RL in FIG. 1) through a power supply terminal (V in FIG. 1).
_cc ). Further, in the embodiment of the present invention, the emitter is commonly connected, is connected to the third constant current source, the second input signal voltage (V _{y in} FIG. 1) is input between the bases, and the collector is the fourth input voltage. , A third differential pair transistor (Q5, Q6 in FIG. 1) connected to a fifth constant current source (I _{0 in} FIG. 1), and the output of the third differential pair transistor and the fourth, From the connection point of the fifth constant current source, the first and second
The differential pair transistors (Q1, Q2, and Q3 in FIG. 1)
A current (see I ₁ and I _{2 in} FIG. 1) flows into the common emitter connection point of Q4).

In the bipolar multiplier according to the present invention, by using the load of the differential pair transistors Q5 and Q6 as a constant current source, a negative-phase current can be output.
By flowing this differential output current into the two constant current sources of the cross-connected differential pair, the drive current of the cross-connected differential pair is reduced to the third current source.
And the output current of the differential pair is equal to each other, so that a multiplier equivalent to a Gilbert cell can be realized.

[0022]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of the present invention;

FIG. 1 is a diagram showing a circuit configuration of a bipolar multiplier according to one embodiment of the present invention. Referring to FIG. 1, in the present embodiment, a cross-coupled differential pair Q1, Q2, and Q3, Q4 to which a first input signal voltage (V _x ) is applied.
And a differential pair Q to which a second input signal voltage (V _y ) is input.
5, Q6.

The differential output current of the cross-connected differential pair is ΔI (the connection point between transistors Q1 and Q3 and transistors Q2 and Q
4) are given by the following equation (7).

[0025]

(Equation 6)

Here, the currents I ₁ and I ₂ are expressed by the following equations (8) and (9), respectively.

[0027]

(Equation 7)

Therefore, the differential output current Δ
I is represented by the following equation (10), and the same transfer function as that of Gilbert cell is obtained.

[0029]

(Equation 8)

That is, a bipolar four-quadrant analog multiplier is obtained. Note that _VLS in FIG. 1 is used for level shift.

As can be seen immediately from FIG. 1, in the present embodiment, the pnp transistor is not used in the signal path, so that the effect of suppressing the deterioration of the frequency characteristic is obtained. In this embodiment, a multiplier that can operate even at a low voltage of, for example, about 1 V can be realized. The reason is that the current is turned back by the constant current source.

[0032]

As described above, according to the present invention,
The following effects are obtained.

(1) A first effect of the present invention is that a four-quadrant multiplier excellent in frequency characteristics can be realized. The reason is that the present invention does not use a pnp transistor in the signal path.

(2) The second effect of the present invention is, for example, 1 V
This means that a multiplier that can operate even at a low voltage can be realized. The reason is that the current is turned back by the constant current source.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a bipolar multiplier according to one embodiment of the present invention.

FIG. 2 is a diagram showing a circuit configuration of a conventional four-quadrant multiplier.

[Explanation of symbols]

I ₀ constant current source Q1 to Q6 Bipolar transistor RL Load resistance VLS Power supply for level shift

Claims (3)

(57) [Claims] An emitter is commonly connected to each of the first and second emitters.
And first and second differential pair transistors of a first conductivity type connected to a second constant current source and having a first input signal voltage input between bases, wherein the first and second differential transistors are provided. The collectors of the differential pair transistors are cross-connected to each other, the connection points are respectively connected to the power supply terminals via load elements, the emitters are connected in common, connected to a third constant current source, and the second input signal is applied between the bases. A voltage is input, and the collector is connected to the fourth and fifth constant current sources.
And a current is supplied from the fourth and fifth constant current sources to a common emitter of the first and second differential pair transistors, respectively. Features a bipolar multiplier. 2. The output of the third differential pair transistor is:
2. The bipolar multiplier according to claim 1 , wherein said bipolar multiplier is connected to a common emitter of said first and second differential pair transistors via a level shift power supply. 3. A first constant current source having emitters commonly connected to each other.
Connected to the ground potential via the first input signal between the bases
Consisting of first and second transistors to which a voltage is input
The first differential pair transistor and the emitter are commonly connected, and the ground current is supplied through a second constant current source.
And the bases are respectively connected to the second and first tows.
Third and fourth transistors connected to the base of the transistor
A second differential pair of transistors, and an emitter connected in common and a ground current via a third constant current source.
And a second input signal voltage is input between the bases.
Connected to the fourth and fifth constant current sources, respectively.
A third differential pair of fifth and sixth transistors
And a transistor, the third Trang the collector of said first transistor
Connected to the collector of the transistor via the first load element
A power supply connected to a collector of the second transistor and the fourth transistor.
Connected to the collector of the transistor via the second load element
A connection point of a collector of the first and third transistors connected to a power supply;
And the collectors of the second and fourth transistors.
An output signal voltage is taken out from the connection point , and the first and the fourth current sources are connected to the fourth and fifth constant current sources.
To the common emitter of the second differential pair transistor, respectively
A bipolar multiplier, which is configured to receive a current .