JP2522068B2 - Signal processing device for charge-coupled device - Google Patents

Description

The present invention relates to a signal processing device for a charge-coupled device.

[Conventional technology]

In recent years, charge coupled devices (hereinafter referred to as CCDs) have been rapidly reduced in chip size and increased in number of bits due to the progress of semiconductor technology.

For example, in the field of consumer television cameras, CCD image pickup devices with 300,000 to 400,000 pixels have been developed, and in the field of high-precision, fine-resolution television cameras, 2 million pixel CCD image pickup devices have been developed.

A problem with the increase in the number of pixels of such a CCD image pickup device is a decrease in signal charge amount, and further noise reduction is indispensable in order to secure the sensitivity and the dynamic range.

The correlated double sampling method (hereinafter referred to as the CDS method) is a noise removal method that has been conventionally used to reduce the noise of the CCD. FIG. 4 shows the configuration of a conventional CCD signal processing device according to the CDS method. In FIG. 4, the output signal of the CCD 101 is passed through the buffer circuit 102 and the clamp capacitor 10
4, input to the clamp circuit 103 composed of the switch circuit 105 and the reference voltage source 106. Then, the clamped CCD output signal is sampled and held by the sample hold circuit 108 including the switch circuit 109 and the hold capacitor 110 via the buffer circuit 107.

Next, the operation of this conventional example will be described with reference to the time chart of FIG. One cycle of the output signal of the CCD 101 includes a reset period 201 in which the reset transistor is turned on by a reset pulse, a feedthrough period 202 in which the floating diffusion layer is kept at a constant potential, and a signal from the charge transfer path to the charge detection unit. It consists of a signal period 203 in which charges are delivered. The effective signal voltage is detected as a difference V _{P1 to} V _P2 between the potential of the feedthrough period 202 and the potential of the signal period 203.
A crank pulse is applied to the clamp circuit 103 in the feed-through period 202 every cycle, and the feed-through level is clamped to the constant potential V _CP . And the signal period 203
The sample and hold pulse is applied to the sample and hold circuit 10
8 is applied to sample and hold the valid signal voltages V _{P1 to} V _P2 . Through the above operation, the feedthrough period is 20
The difference between the potential of 2 and the potential of the signal period 203 can be taken out as an effective signal voltage, and at the same time, the noise component superimposed in both periods can be removed.

[Problems to be Solved by the Invention]

In the conventional DCS method described above, the effective signal voltage is taken out by the clamp operation and the sample hold operation. Applying this method to a CCD with 2 million pixels
Two narrow pulses of about 7 ns, that is, a clamp pulse and a sample hold pulse are required. Therefore, during high speed operation, it is difficult to obtain stable characteristics due to jitter between two pulses or the like. Further, since the signal is sampled by the sample hold, there is a drawback that the high frequency noise component is largely folded back into the band.

FIG. 6 shows a sampling process in the sample hold operation. The CCD 10 whose feedthrough level is clamped to a constant potential V _CP by the clamp circuit 103 in FIG.
The output signal of 1 is sampled and held by the sample and hold pulse, but the potential of the hold capacitor 110 until it is held changes as shown by. That is, when the sample hold is started at time t _A , the potential of the hold capacitor 110 gradually approaches the input signal 3 and coincides with the input signal at time t _B. Then, the potential at the time t _C when the sample hold pulse is turned off is held until the next sample hold pulse is turned on. Therefore, the held potential is determined by the signal voltage at time t _C when the sample-hold pulse is turned off. It is replaced as a frequency fluctuation, that is, a folding noise component.

The present invention has solved the above problems, and an object of the present invention is to provide a noise suppression circuit for a CCD that is stable with respect to high-speed operation and has a small aliasing noise component.

[Means for solving the problem]

A signal processing device of a charge-coupled device according to the present invention includes a first buffer circuit connected to an output end of the charge-coupled device, and the first buffer circuit.
A first resistance element connected to the output terminal of the buffer circuit, a delay line having an output terminal branched to the output terminal of the first resistance element and connected to the ground, and a second buffer circuit; A second resistance element connected to the output terminal of the second buffer circuit, a switch circuit connected to the output terminal of the second resistance element, and a hold capacitor connected to the output terminal of the switch circuit. A signal period of an output signal of the charge coupled device which is directly input to the second buffer circuit from the charge coupled device via the first buffer circuit, and is input to an input end of the delay line and output. The delay time of the delay line is set so that the feed-through period of the delayed signal that has reached the end and totally reflected and returned to the input end overlaps, and the effective signal of the output signal of the second buffer circuit is set. Voltage, said second resistance element is constituted by the switching circuit and the hold capacitor, is that extracted by the sample-and-hold circuit is set large integration time constant than the width of the sampling pulse for controlling the switching circuit.

[Action]

In the present invention, the potential difference between the feedthrough period and the signal period is obtained by utilizing the reflection of the delay line. Therefore, since the clamp operation is not involved, the CCD is stable even if the number of pixels is increased and the speed is increased.

In addition, when sampling, the effective signal voltage is sampled by a sample hold circuit that has an integration characteristic with CR (C: hold capacitor, R: resistance). Therefore, the response to the high-frequency noise component is suppressed by the integral characteristic, and the aliasing component in the band due to sampling becomes extremely small.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of a signal processing device of a charge coupled device according to the present invention. In FIG. 1, the output signal of the CCD image pickup device 1 is delayed by the delay line 13 via the resistor 11.
Input terminal and the buffer circuit 7. Here, the resistance 11 is equal to the characteristic impedance of the delay line 13, and the output terminal of the delay line 13 is grounded. Further, the output signal of the buffer circuit 7 is the resistance 12
The output terminal is input to the switch circuit 9 connected to the hold capacitor 10 via.

Next, the operation of this embodiment will be described with reference to the time chart of FIG. Of the output signals of the buffer circuit 2, one pixel cycle includes a reset period 201 (Trs) and a feedthrough period.
It is divided into 202 (Tft) and signal period 203 (Ts), and the effective signal voltage of one pixel is the feedthrough period 202 and the signal period 203.
It appears as a potential difference V _{P1 to} V _P3 . The output signal of the buffer circuit 2 is input to the delay line 13 via the resistor 11 and, after being delayed by the delay time τ, reaches the grounded output end. It is inverted and reflected at the output end, reaches the input end after being delayed by the delay time τ again. Here, the total delay time 2
τ is set so that the signal period of the output signal and the feed-through period of the signal reflected and reaching the input terminal again overlap (0 <
2τ <(Tft + Ts)) is set. The signal and the signal are mixed at the input end and output as an output signal via the buffer circuit 7. In the output signal, the effective signal voltage of the pixel is amplitude-modulated and appears as voltages V _P1 ′ to V _P3 ′. A sample pulse is applied to the switch circuit 9, and only the effective signal voltages V _P1 ′ to V _P3 ′ are extracted (output signal).

Figure 3 shows the sampling process. A resistor 12 is connected to the input end of the switch circuit 9 and a hold capacitor 10 is connected to the output end of the switch circuit 9 to form an integrating circuit as a whole. Since the integration time constant represented by RC is set larger than the width of the sampling pulse, this sampling process is equivalent to averaging the signal voltage while the sampling pulse is on. . As shown in FIG. 3, the time
When sampling starts at ta, the potential of the hold capacitor 10 gradually approaches the input signal,
When the switch circuit 9 is turned off at time tb before matching the input signal, the potential at that time is held. That is, the held potential is a voltage obtained by integrating the signal voltage during the period ta-tb during which the switch circuit 9 is turned on.

With the above operation, the potential difference between the feedthrough period and the signal period, which is the effective signal voltage of the CCD image pickup device, can be sampled while removing the noise component superimposed in both periods.

Although the CCD image pickup device has been described as an example, it is obvious that the present invention can be applied to charge-coupled devices in general.

〔The invention's effect〕

As described above, according to the present invention, the potential difference between the feedthrough period and the signal period can be obtained by a simple circuit including the delay line and the buffer circuit without the clamp operation. Therefore, even if the CCD clock rate is increased, the noise component superimposed in both periods can be effectively removed and only the effective signal voltage can be accurately sampled.

Further, in the sampling process of the present invention, the effective signal voltage is sampled by the sampling circuit having the integral characteristic. Therefore, the response to the high frequency noise component becomes small, and the aliasing component in the band due to sampling becomes extremely small.

Thus, according to the present invention, the noise component can be effectively suppressed even if the CCD speeds up.

[Brief description of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention, FIG. 2 is a time chart for explaining the operation of this embodiment, and FIG. 3 is a time chart for explaining the sampling process in this embodiment. FIG. 4 is a block diagram showing a conventional noise elimination circuit, FIG. 5 is a time chart for explaining the operation of a conventional example,
FIG. 6 is a time chart for explaining the sampling process in the conventional example. 1,101 …… CCD image sensor, 2,102,7,107 …… buffer circuit, 105,9,109 …… switch circuit, 11,12, …… resistor, 13
... delay line, 10,110 ... hold capacitor,
106 …… Reference voltage source, 201 …… Reset period, 202 …… Feed-through period, 203 …… Signal period.

Claims (1)

(57) [Claims] 1. A first buffer circuit connected to an output terminal of a charge coupled device, a first resistance element connected to an output terminal of the first buffer circuit, and an output of the first resistance element. A delay line having a grounded output terminal branched and connected to the end, a second buffer circuit, a second resistance element connected to the output terminal of the second buffer circuit, and the second resistance element A switch circuit connected to the output terminal of the switch circuit and a hold capacitor connected to the output terminal of the switch circuit, and input from the charge coupled device directly to the second buffer circuit via the first buffer circuit. So that the signal period of the output signal of the charge-coupled device overlaps the feed-through period of the delay signal that is input to the input end of the delay line, reaches the output end, undergoes total reflection, and returns to the input end again. , The di Delay time of Irain is set,
The effective signal voltage of the output signal of the second buffer circuit,
A charge-coupled device comprising a second resistance element, the switch circuit, and the hold capacitor, which is extracted by a sample hold circuit in which an integration time constant is set to be larger than a width of a sampling pulse which controls the switch circuit. Signal processing device.