JPH0255942B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention is directed to a two-phase
Relates to the fat zero input method of CCD charge transfer devices.

Frame transfer surface channel type
CCD solid-state imaging devices can be operated with high transfer efficiency by introducing bias charges called fat zeros to reduce the influence of interface states. However, it is difficult to uniformly insert fat zeros into each bit of the image portion, and if the fat zeros are not uniform, it will appear as linear fixed pattern noise. For this reason, a charge transfer device has been proposed, for example, as shown in FIG. 1, in which a diffusion layer is provided at the input and bias charges are electrically introduced therefrom. Figure 1A is
Taking as an example the image part of a frame transfer type solid-state image sensor using a three-layer CCD, on one surface of the silicon substrate 1 of the first conductivity type, for example, the P type.
A plurality of transfer electrodes 3 are arranged along the charge transfer direction a through a gate insulating film 2 made of SiO ₂ or the like to constitute a transfer section that also serves as a light receiving area, and every third transfer electrode 3 is connected in common. 3-phase transfer clock voltages φ ₁ , φ ₂ and φ ₃ are applied to each of them, and an input section formed by an N ⁺ type diffusion layer 4 is provided on the base body 1, and this input section and the transfer section are connected to each other. An input gate portion with an input gate electrode 5 formed therebetween is provided with a gate insulating film 2 interposed therebetween. In order to introduce a bias charge that becomes a fat zero, first
As shown in Figure A, all the transfer electrodes 3 are turned on, and the input gate is opened by the gate voltage φ _IG to remove unnecessary charges from the diffusion layer 4 to which the input voltage V _IN is applied under all the transfer electrodes 3. Inject Q _A. Next, as shown in FIG. 1C, only the transfer electrode 3 in the region to receive light (in this case, the φ ₂ electrode) is turned on to push up the potential well 6, and at the same time, the other transfer electrodes 3 in the φ ₁ and φ ₃ areas are turned on. Push up the bottom to the acquisition potential. At this time, a charge Q _B corresponding to the difference between the on-level potential and the threshold potential Vth is accumulated under the transfer electrode 3 of φ ₂ , and the excess charge is released into the substrate 1 . Next, as shown in Figure 1D, the potential under the transfer electrode 3 of _φ2 is further deepened to receive light.
Start hv. At this point, the bias charge Q _B accumulated under the transfer electrode 3 of φ ₂ becomes fat zero.

If such a measure is taken, the amount of fat zero is determined by the potential of the electrode of each bit in FIG. Even if there are variations in surface potential, a uniform fat zero is introduced, and no linear fixed pattern noise is introduced. However, although this means is applicable to three-phase drive and four-phase drive CCD charge transfer devices, it cannot be applied to a two-phase drive CCD charge transfer device in which step potentials are formed with the same voltage. This is because, if the above operation is performed when inputting bias charges, the maximum amount of charges to be handled must be once introduced into the register section. That is, as shown in the potential distribution in FIG. 2, the transfer electrodes 3 of φ ₁ and φ ₂
In order to turn on and inject the bias charge Q _A , each bit of the register must once accumulate a charge greater than the maximum amount of charge that can be handled. Even in this way, it is possible to give equal fat zeros to each bit by performing the operations shown in FIG. In the case of the frame transfer method, this large amount of excess charge leaks into the storage section, causing problems such as large noise.

In view of the above-mentioned points, the present invention provides a fat-zero input method for a charge transfer device that can introduce a uniform fat-zero bias charge to each bit of a register, especially in a two-phase CCD. be.

The present invention will be explained below with reference to the embodiment shown in FIG.

FIG. 3A shows an image portion of a frame transfer type surface channel type solid-state imaging device using a two-phase CCD. In the figure, 1 is the first conductivity type, for example P
shaped silicon substrate, on one side of this substrate 1
A plurality of transfer electrodes 3 are arranged in a charge transfer direction a via a gate insulating film 2 made of SiO ₂ or the like, thereby forming a CCD transfer section that also serves as a light receiving section.
Each transfer electrode 3 is commonly connected every other
Phase clock voltages φ ₁ and φ ₂ are applied. In addition,
For example, the gate insulating film 2 of the storage part and the transfer part is formed so that stepped potentials (storage part and transfer part) are formed along the transfer direction under the transfer electrodes given φ ₁ and φ ₂ , respectively. It is possible to adopt a configuration in which the film thicknesses are made different, or the impurity concentrations on the substrate surfaces in the storage section and the transfer section are made equal to each other. on the other hand,
The base body 1 is provided with an input section formed by a second conductivity type, that is, an N ⁺ type diffusion layer 4, and a first input gate electrode 7 and a second input gate electrode are connected to each other with a gate insulating film 2 interposed between the input section and the transfer section. An input gate portion formed by 8 is provided.

In order to introduce fat zero in such a configuration, first, for example, during the frame shift period T _FS (by applying clock voltages φ ₁ and φ ₂ to each transfer electrode 3 in the vertical blanking period shown in FIG. (period in which signal charges are transferred from the image section to the storage section), the first input gate electrode 7 and the second input gate electrode 8 are simultaneously
Applying the first gate voltage G ₁ and the second gate voltage G ₂ to the input voltage V _IN with the timing shown in FIG. 5, and driving each transfer electrode 3 by φ ₁ and φ ₂ , From the applied diffusion layer 4 of the input section, a charge amount slightly larger than the fat zero bias charge amount is sequentially introduced under the next electrode to receive light. To describe this operation in more detail, at time _t1 in FIG. 5, a charge slightly larger than the required bias charge amount is applied from the diffusion layer 4 to the area below the first input gate, as shown in FIG. 3B.
Q _A ' is injected, and at time t ₂ a charge Q _A ' is stored under the first and second input gates as shown in FIG. 3C. At this time, the amount of charge Q _A ' to be injected is arbitrarily controlled depending on the relative potential between the input diffusion layer 4 and the second input gate portion. Next, at time _t3 , the first input gate section is turned off, and the charge _QA ' is transferred to the lower part of the second input gate (Fig. 3D), and then at time _t4 and _t5 , it is transferred to the next electrode to receive light. For example, transfer electrode 3 of φ ₁
A charge Q _A ' is transferred downward (FIG. 3E and F). Thereafter, this charge Q _A ' is sequentially transferred by the clock voltages φ ₁ and φ ₂ , and at the same time, the same amount of charge Q _A ' is sequentially transferred from the input diffusion layer 4 to the transfer electrode 3 of φ ₁ to which each light is to be received. It is injected downward (Fig. 3G). In this state, the amount of charge Q _A ' in each register varies due to variations in the surface potential of the input gate portion. In this way, each bit of the image part is given a predetermined charge.
After implanting Q _A ', that is, during the period Ta after the frame shift period _TFS in FIG. 5, a predetermined voltage is applied to the transfer electrode 3 of φ ₁ as shown in FIG. At the same time, a voltage is applied to the other transfer electrode 3 of φ ₂ to bring the area under the electrode into an accumulation state, and the area under the electrode is pushed up to the accumulation potential. At this time, an amount of charge Q _B corresponding to the difference between the on-level potential and the threshold voltage Vth is accumulated under the transfer electrode 3 of φ ₁ , and the excess charge is released into the substrate 1 . Next, the light reception period T _INT shown in FIG. 5 is entered, and the potential well under the transfer electrode 3 of φ ₁ is further deepened to start light reception hv.
At this point, the bias charge Q _B accumulated under the transfer electrode 3 of φ ₁ becomes a fat zero, and a signal charge Qsig corresponding to the amount of light received is accumulated in each potential well (FIG. 3I).

As described above, according to the present invention, a charge Q _{A '} larger than the bias charge Q B is first injected into the bit of each register by so-called CCD transfer, and then the potential is pushed up to remove the necessary amount of bias charge Q _B. By discharging the excess charge into the substrate and using the remaining bias charge Q _B as a fat zero, the 2-phase CCD charge transfer device also has a It is possible to introduce a uniform fat zero to the bits of the register, and there is no problem such as noise.
Therefore, for example, two-phase frame transfer method
This makes it suitable for application to a CCD solid-state image sensor.

In the above example, the charge Q _A ' was injected during the frame shift period T _FS , but it can also be performed after the frame shift period as long as it is within the vertical blanking period.

[Brief explanation of the drawing]

1A to 1D are potential change diagrams for introducing fat zero, showing an example of a conventional three-phase CCD charge transfer device, and FIG. 2 is a two-phase CCD charge transfer device used to explain the present invention.
Potential diagram of CCD charge transfer device, Figure 3A
~I is a potential change diagram for introducing a fat zero showing an example of a fat zero input method of a two-phase CCD charge transfer device according to the present invention, FIG. 4 is a diagram showing an operation period used to explain the present invention, and FIG. The figure is a drive pulse waveform diagram of the present invention. 1 is a semiconductor substrate, 2 is a gate insulating film, 3 is a transfer electrode, 4 is an input diffusion layer, and 5, 7, and 8 are input gate electrodes.

Claims (1)

[Claims] 1. In a two-phase CCD charge transfer device having an input section and a transfer section, an amount of charge slightly larger than a predetermined amount of bias charge determined by a potential applied to the input section is transferred to the above. The electrode on the transfer section is driven and introduced under the first phase electrode in the electrode, and the transfer section of the first phase electrode becomes in the accumulation state, and the storage section is in the non-accumulation state. By applying a potential to the first phase electrode such that the state is brought into a state, and applying a potential to an electrode other than the first phase electrode such that the area under the electrode becomes an accumulation state,
A fat zero input of a charge transfer device characterized in that a charge other than the predetermined bias charge amount is released from below the first phase electrode into the substrate to introduce a predetermined bias charge below the first phase electrode. method.