JPS63164274A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS63164274A JPS63164274A JP61308280A JP30828086A JPS63164274A JP S63164274 A JPS63164274 A JP S63164274A JP 61308280 A JP61308280 A JP 61308280A JP 30828086 A JP30828086 A JP 30828086A JP S63164274 A JPS63164274 A JP S63164274A
- Authority
- JP
- Japan
- Prior art keywords
- electrode layer
- transfer
- insulating film
- voltage
- transfer electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 7
- 239000002184 metal Substances 0.000 claims abstract description 10
- 239000000758 substrate Substances 0.000 claims abstract description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 6
- 239000012535 impurity Substances 0.000 abstract description 6
- 229910052710 silicon Inorganic materials 0.000 abstract description 6
- 239000010703 silicon Substances 0.000 abstract description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 5
- 238000000034 method Methods 0.000 abstract description 3
- 238000003384 imaging method Methods 0.000 description 6
- 238000010586 diagram Methods 0.000 description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- DDFHBQSCUXNBSA-UHFFFAOYSA-N 5-(5-carboxythiophen-2-yl)thiophene-2-carboxylic acid Chemical compound S1C(C(=O)O)=CC=C1C1=CC=C(C(O)=O)S1 DDFHBQSCUXNBSA-UHFFFAOYSA-N 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000003111 delayed effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
Landscapes
- Solid State Image Pick-Up Elements (AREA)
- Transforming Light Signals Into Electric Signals (AREA)
Abstract
Description
【発明の詳細な説明】 〔発明の目的〕 (産業上の利用分野) この発明は半導体装置の高速駆動に関する。[Detailed description of the invention] [Purpose of the invention] (Industrial application field) The present invention relates to high-speed driving of semiconductor devices.
(従来の技術)
従来技術では固体撮像装置の転送電極は第3図(a)〜
(d)の如く構成されている。まずシリコン基板11上
に第1層目の絶縁膜12−1を形成し、その上に第1層
目の転送1413を形成する。次に転送電極13を含む
絶縁IPJ12−1上に第2層目の絶縁11112−2
を形成する。その後第2転送電極を形成する部分の絶縁
膜12−2を例えばNH,F (弗化アンモン)液等に
よりエツチングし、再度絶縁膜12−3を形成し。(Prior art) In the prior art, the transfer electrode of a solid-state imaging device is as shown in Fig. 3(a).
It is configured as shown in (d). First, a first layer insulating film 12-1 is formed on the silicon substrate 11, and a first layer transfer 1413 is formed thereon. Next, a second layer of insulation 11112-2 is placed on the insulation IPJ 12-1 including the transfer electrode 13.
form. Thereafter, the portion of the insulating film 12-2 where the second transfer electrode is to be formed is etched using, for example, NH, F (ammonium fluoride) solution, and the insulating film 12-3 is again formed.
最後に第2転送電極14を形成する。Finally, the second transfer electrode 14 is formed.
このように構成された転送電極は固体撮像装置において
は第4図の如く4相のパルスで駆動され順次電荷が転送
される。第4図(a)は断面、(b)は転送部のポテン
シャル図を示す。In a solid-state imaging device, the transfer electrode configured as described above is driven by four-phase pulses as shown in FIG. 4, and charges are sequentially transferred. FIG. 4(a) shows a cross section, and FIG. 4(b) shows a potential diagram of the transfer section.
(発明が解決しようとする問題点)
i)現在2層の転送電極はP(リン)等をドープして抵
抗を下げた多結晶シリコンで形成されている。そのため
高速パルスを印加すると転送電極がもつ抵抗のため波形
のなまり、遅延といった問題が生じ、高速転送が困難に
なる。(Problems to be Solved by the Invention) i) Currently, two-layer transfer electrodes are formed of polycrystalline silicon doped with P (phosphorus) or the like to lower resistance. Therefore, when high-speed pulses are applied, problems such as waveform distortion and delay occur due to the resistance of the transfer electrodes, making high-speed transfer difficult.
ji)2相駆動は4相駆動に比べれば転送速度は速いが
、第1W1目の転送電極、第2層目の転送電極に2相の
パルスを印加するためパルスを印加する電極面積が大き
くなり、容量が大きくなるため波形のなまり、遅延とい
った問題が生じ。ji) Two-phase drive has a faster transfer speed than four-phase drive, but since two-phase pulses are applied to the 1st W1 transfer electrode and the 2nd layer transfer electrode, the electrode area to which the pulses are applied becomes larger. , as the capacity increases, problems such as waveform distortion and delay occur.
高速転送が困難になる。また容量が大きいと。High-speed transfer becomes difficult. Also, the capacity is large.
消費電力も大きくなってしまう。Power consumption also increases.
本発明は上記事情に鑑みてなされたもので、固体撮像装
置の転送電極の形成手段、及び駆動方法に起因した高速
駆動の制約、消費電力といった問題が生じるのを阻止し
た半導体装置を提供することを目的とする。The present invention has been made in view of the above circumstances, and it is an object of the present invention to provide a semiconductor device that prevents problems such as high-speed drive restrictions and power consumption caused by a means for forming a transfer electrode of a solid-state imaging device and a drive method. With the goal.
(問題点を解決するための手段) 本発明では、第2転送電極を形成するに先立ち。 (Means for solving problems) In the present invention, prior to forming the second transfer electrode.
第2転送itt極下にくるべきところのシリコン基板の
一部にn型又はP型の不純物層を作り、しかる後第2転
送電極を金属により形成し、第1転送電極にDC電圧を
印加し第2転送電極には1つおきに2相のパルスを印加
することにより、高速駆動を図る。An n-type or p-type impurity layer is formed on a part of the silicon substrate that should be under the second transfer electrode, and then a second transfer electrode is formed of metal, and a DC voltage is applied to the first transfer electrode. High-speed driving is achieved by applying two-phase pulses to every other second transfer electrode.
(作用)
転送電極に金属ffi極を使うことにより、多結晶シリ
コン電極に比べ、電極の抵抗が大幅に下がる。(Function) By using a metal ffi electrode as a transfer electrode, the resistance of the electrode is significantly lowered compared to a polycrystalline silicon electrode.
その結果、印加したパルスがなまったり、遅延したりす
る割合が大幅に減少する。As a result, the rate at which the applied pulses become dull or delayed is significantly reduced.
また2相のパルスをそれぞれ、第1P!1目、第2層目
の伝送電極に印加するのでなく第1層目の転送電極には
DC電圧を印加し、第2層目の転送電極に1つおきに2
相のパルスを印加することにより、パルスを印加する面
積が小さくなり、高速パルスの印加が可能となる。また
これにより消費電力も小さくすることができる。In addition, each of the two-phase pulses is applied to the 1st P! Instead of applying a DC voltage to the first and second layer transfer electrodes, a DC voltage is applied to the first layer transfer electrode, and every second layer is applied to the second layer transfer electrode.
By applying phase pulses, the area to which the pulses are applied becomes smaller, making it possible to apply high-speed pulses. This also allows power consumption to be reduced.
(実施例)
本発明を固体撮像装置に適用した場合について第1図(
a)〜(d)に基づいて説明する。(Example) Fig. 1 (
The explanation will be based on a) to (d).
まずP型シリコン基板21表面を熱酸化し、絶縁膜22
−1000人を形成する。その後公知の方法によりP型
シリコン基板21表面にn型埋込み領域23をイオン注
入形成しく第1図a)、基板21上の絶縁膜22の上に
P(リン)等をドープした多結晶シリコンで第1層目の
転送電極24をRIB、 CDE、又はVetエツチン
グでパターニングして形成する(第1図b)1次に第1
層目の転送電極24以下以外の絶縁膜をエツチング除去
し、その後第1層目の転送電極24と第2層目の転送電
極25の間の絶縁膜22−2>】000人を熱酸化形成
する0次に第2層目の転送電極25が形成されるべきと
ころの基板21の一部にポテンシャルの段差形成の為n
型の不純物領域26を形成しく第1図c)、その後AQ
Mosi等の金属で第2層目の転送電極25を形成した
(第1図d)。First, the surface of the P-type silicon substrate 21 is thermally oxidized, and the insulating film 22 is
- Form 1000 people. Thereafter, an n-type buried region 23 is formed by ion implantation on the surface of the P-type silicon substrate 21 by a known method (FIG. 1a), and polycrystalline silicon doped with P (phosphorus) or the like is placed on the insulating film 22 on the substrate 21. The first layer transfer electrode 24 is patterned and formed by RIB, CDE, or Vet etching (FIG. 1b).
The insulating film other than the transfer electrode 24 in the first layer and below is removed by etching, and then the insulating film 22-2 between the first transfer electrode 24 and the second transfer electrode 25 is formed by thermal oxidation. In order to form a potential step in a part of the substrate 21 where the second layer transfer electrode 25 is to be formed,
A type impurity region 26 is formed (FIG. 1c), and then AQ
A second layer transfer electrode 25 was formed of a metal such as Mosi (FIG. 1d).
以上の構造をもつ固体撮像装置において、第1層目の転
送電極24にある一定のDC電圧を印加し。In the solid-state imaging device having the above structure, a certain DC voltage is applied to the first layer transfer electrode 24.
第2層目の転送電極25に1つおきに逆相をもっ2相の
パルス電圧を印加し1電極おきに電荷を転送した。第2
図(a)は断面図、(b)は基板表面の電荷の転送を示
すポテンシャル図、(c)はパルス波形図である。上記
実施例で第2層目の転送電極下にn型でなくP型の不純
物領域を形成すれば転送方向を逆にすることができる。Two-phase pulse voltages with opposite phases were applied to every other transfer electrode 25 in the second layer to transfer charge to every other electrode. Second
Figure (a) is a cross-sectional view, (b) is a potential diagram showing charge transfer on the substrate surface, and (c) is a pulse waveform diagram. In the above embodiment, the transfer direction can be reversed by forming a p-type impurity region instead of an n-type impurity region under the second layer transfer electrode.
またここではCOD固体撮像装置の場合について述べた
が、これに限らず他の半導体装置にも同様に適用できる
。Further, although the case of a COD solid-state imaging device has been described here, the present invention is not limited to this and can be similarly applied to other semiconductor devices.
以上詳述した如く本発明によれば、なまり、遅延の少な
いパルスを印加でき、転送速度を向上させた固体撮像装
置を提供することができる。As described in detail above, according to the present invention, it is possible to provide a solid-state imaging device that can apply pulses with less rounding and delay and has improved transfer speed.
第1図は本発明を工程順に追った断面図、第2図はその
動作を示す図、第3図は従来構造を示す図、第4図はそ
の動作を示す図である。
図において、
11.21・・・P型シリコン基板、 12.22・
・・絶縁膜、13.24・・・第1電極(多結晶シリコ
ン)。
23・・・n型埋め込み領域、 26・・・n型不純物
相。
25・・・第2電極(金属)。
代理人 弁理士 則 近 憲 佑
同 竹花喜久男
第 2 図
、tvcm−4V
(C)
第 2 図FIG. 1 is a sectional view showing the present invention in the order of steps, FIG. 2 is a view showing its operation, FIG. 3 is a view showing a conventional structure, and FIG. 4 is a view showing its operation. In the figure, 11.21...P-type silicon substrate, 12.22.
...Insulating film, 13.24...First electrode (polycrystalline silicon). 23...n-type buried region, 26...n-type impurity phase. 25... Second electrode (metal). Agent Patent Attorney Noriyuki Ken Yudo Kikuo Takehana Figure 2, tvcm-4V (C) Figure 2
Claims (1)
、第2層目の電極を金属電極とし、第1層目の電極には
DC電圧を印加し、第2層目の金属電極には1つおきに
2相のパルスを印加することを特徴とする半導体装置。In a semiconductor device having two layers of electrodes on a semiconductor substrate, the second layer electrode is a metal electrode, a DC voltage is applied to the first layer electrode, and one layer is applied to the second layer metal electrode. A semiconductor device characterized in that a two-phase pulse is applied every other time.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP61308280A JPS63164274A (en) | 1986-12-26 | 1986-12-26 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP61308280A JPS63164274A (en) | 1986-12-26 | 1986-12-26 | Semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS63164274A true JPS63164274A (en) | 1988-07-07 |
Family
ID=17979130
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP61308280A Pending JPS63164274A (en) | 1986-12-26 | 1986-12-26 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS63164274A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0439353U (en) * | 1990-07-30 | 1992-04-03 | ||
JPH0568140A (en) * | 1991-09-06 | 1993-03-19 | Oki Electric Ind Co Ltd | Charge coupled device, solid state image pickup device and method for driving the charge coupled device |
-
1986
- 1986-12-26 JP JP61308280A patent/JPS63164274A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0439353U (en) * | 1990-07-30 | 1992-04-03 | ||
JPH0568140A (en) * | 1991-09-06 | 1993-03-19 | Oki Electric Ind Co Ltd | Charge coupled device, solid state image pickup device and method for driving the charge coupled device |
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