JP2712424B2 - Method for manufacturing charge transfer device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state imaging device, and more particularly to a method of manufacturing a charge transfer device having a low driving voltage and low power consumption.

[Conventional technology]

2. Description of the Related Art Conventionally, a two-phase drive type charge transfer device having a three-layer superposition structure used for a solid-state imaging device or the like is formed by, for example, a manufacturing method shown in FIGS.

First, as shown in FIG. 4, a first gate oxide film 3 is formed on the surface of a P-type silicon substrate 1 on which an N-type diffusion layer 2 is formed.
To form After a first polycrystalline silicon film is deposited by vapor phase growth, patterning is performed to form a plurality of arranged storage gates 4.

Next, as shown in FIG. 5, after removing the exposed first gate oxide film 3, a second gate oxide film 5 is formed by thermal oxidation. At this time, the surface of storage gate 4 made of a polycrystalline silicon film is also covered with thermal oxide film 5. Next, boron is added into the N-type diffusion layer 2 by ion implantation to form the charge transfer barrier region 6. At this time, immediately below the storage gate 4, the storage gate serves as a mask and boron is not added.

Next, as shown in FIG. 6, a first barrier gate 7 made of a polycrystalline silicon film is formed on the charge transfer barrier region 6.

Next, as shown in FIG. 7, after removing the exposed second gate oxide film 5, a third gate oxide film 9 is formed by thermal oxidation. At this time, the surfaces of the storage gate 4 and the first barrier gate 7 are also covered with the thermal oxide film 9. Subsequently, a second barrier gate 8 made of a polycrystalline silicon film is formed on the charge transfer barrier region 6.

Further, after covering the surface of the second barrier gate 8 with a thermal oxide film, a metal wiring as a clock terminal for applying a clock voltage is formed, though not shown, to complete the device.

The above-described charge transfer region transfers charges by applying “high” and “low” voltages to the clock terminals φ ₁ and φ ₂ .

[Problems to be solved by the invention]

In the charge transfer device manufactured by the method described above, FIG. 8 shows the depth of the channel potential immediately below each gate when a “stop” voltage is applied to the clock terminals φ ₁ and φ ₂ . The channel potentials φ _VS immediately below the storage gate 4 are all the same. However, since the step of forming the third gate oxide film is present before the step of forming the second barrier gate, the channel potential φ just below the first barrier gate 7 is present.
_VB1 and the channel potential φ _VB2 immediately below the second barrier gate 8 are φ
_VB2 is shallower than Va.

Therefore, when transferring charges in the direction of the arrow in FIG. 9, now, OV to the clock terminal phi ₂ as "low" level,
When a voltage of 5V as a "high" level to phi _1, the charge that was directly under phi ₂ of the storage gate are transferred to the phi ₁ of the storage gate immediately below. In this case, equal first and the depth of the second channel potential just below the barrier gate, storage gate are connected to phi ₁ by applying a voltage of 5V to phi ₁ and a second channel of the barrier gate The potential becomes deeper by Vb, and charges can be transferred in the direction of the arrow.

However, as described above, since the channel potential immediately below the second barrier gate 8 is shallower by Va than the depth of the channel potential immediately below the first barrier gate 7, this impedes the transfer of charges, and as shown in FIG. charge to phi ₂ of the storage gate immediately under the left behind. This results in poor transfer efficiency and causes deterioration of device characteristics.

In order to improve this, conventionally, in order to further deepen the channel potential directly below the second barrier gate 8 by Va, the “high” voltage applied to φ ₁ is increased to, for example, about 8 V, and the voltage is accordingly increased. There is a problem that power consumption increases.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a charge transfer device in which power consumption is reduced.

[Means for Solving the Problems] A method of manufacturing a charge transfer device according to the present invention includes a step of arranging a plurality of storage gates at required intervals on a first conductivity type semiconductor layer via a gate oxide film. Ion-implanting a second conductivity type impurity into the semiconductor layer between the plurality of storage gates to form a charge transfer region; and forming a gate on every other charge transfer region of the charge transfer regions. Forming a first barrier gate through an oxide film, ion-implanting a first conductivity type impurity into the charge transfer region not formed in the first barrier gate, and ion-implanting the first conductivity type impurity. Forming a second barrier gate on the injected charge transfer region via a gate oxide film.

[Action]

According to the above-described manufacturing method, the impurity concentration of the charge transfer region immediately below the second barrier gate can be reduced, and its channel potential can be made equal to the channel potential of the charge transfer region immediately below the first barrier gate.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1 is a diagram showing a part of the steps of the method of one embodiment of the present invention, and is a cross-sectional view showing a step that follows the steps shown in FIGS. 4 to 6 in detail.

That is, in this structure method, as shown in FIGS. 4 to 6, a first gate oxide film 3 is formed on a surface of a P-type silicon substrate 1 on which an N-type diffusion layer 2 is formed. After forming the storage gate 4 thereon, the exposed first gate oxide film 3 is removed, and the second gate oxide film 5 is formed by thermal oxidation. Further, after boron is added to the N-type diffusion layer 2 by ion implantation to form the charge transfer barrier region 6, a first barrier gate 7 is formed on the charge transfer barrier region 6.

Then, as shown in FIG. 1, the N-type diffusion layer 2, ie, every other region of the charge transfer barrier region 6,
Phosphorus is added by ion implantation to form a charge transfer barrier region 6 'in this region.

Further, as shown in FIG. 7, the charge transfer barrier region 6 '
A second barrier gate 8 is formed thereon.

Thereafter, metal wiring (not shown) constituting the clock terminal is formed, and the device is completed.

FIG. 2 shows the depth of the channel potential immediately below the storage gate and immediately below the barrier gate when the two-phase clock terminals φ ₁ and φ ₂ are fixed to “low” in the charge transfer device manufactured as described above. . As can be seen, the second barrier gate 8
Of the charge transfer barrier region 6 'immediately below the first barrier gate 7, the channel potential of which is substantially the same as that of the charge transfer barrier region 6 immediately below the first barrier gate 7. It can be as deep as possible.

Accordingly, as shown in FIG. 3, about the clock phi ₁ 5
The charge can be completely transferred in the direction of the arrow only by applying the voltage of V, so that the power consumption can be reduced.

〔The invention's effect〕

As described above, according to the present invention, the impurity of the opposite conductivity type is ion-implanted into the charge transfer region before the formation of the second barrier gate. Therefore, the impurity concentration of the charge transfer region immediately below the second barrier gate is reduced. And the channel potential can be made equal to the channel potential of the charge transfer region immediately below the first barrier gate. As a result, there is an effect that charge transfer at a low clock voltage can be realized, and a charge transfer device that can reduce power consumption can be obtained.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a part of the steps of the manufacturing method of the present invention, FIGS. 2 and 3 are channel potential diagrams of a charge transfer device manufactured by the method of the present invention, and FIGS. 8 and 9 are channel potential diagrams of a charge transfer device manufactured by a conventional method. DESCRIPTION OF SYMBOLS 1 ... P type silicon substrate, 2 ... N type diffusion layer, 3 ... gate oxide film, 4 ... storage gate, 5 ... gate oxide film, 6,6 '... Charge transfer area, 7 ... First barrier gate, 8 ... Second barrier gate.

Claims (1)

(57) [Claims] A step of arranging a plurality of storage gates at required intervals on a first conductivity type semiconductor layer via a gate oxide film; and forming a second storage layer in the semiconductor layer between the plurality of storage gates. Forming a charge transfer region by ion-implanting a conductive type impurity; and forming a first barrier gate on each other charge transfer region of the charge transfer region via a gate oxide film. A step of ion-implanting a first conductivity type impurity into the charge transfer region where the first barrier gate is not formed; and a step of interposing a second gate oxide film on the charge transfer region implanted with the first conductivity type impurity. Forming a barrier gate of the charge transfer device.