JPS61123173A - Solid-state image pickup device and manufacture thereof - Google Patents

Abstract

PURPOSE:To obtain a solid-state image pickup device using an electrostatic induction type transistor with a gate capacitor region having a small area and high capacitance by forming the SIT Tr constituted by a gate region shaped around a groove formed to a semiconductor substrate and a capacitor region buried into the groove through an insulating film. CONSTITUTION:An n<-> epitaxial layer 11 containing an n type impurity is formed onto an n<+> Si substrate 10 shaping a drain in an SIT, a transparent insulating film 12-1 is formed onto the layer 11, and a p<+> gate region 13 is shaped to the layer 11. The upper section of the region 13 is coated with a transparent insulating film 12-1. The film 12-1 is removed selectively through etching, and the layer 11 is etched while using the film 12-1 as a mask to shape a groove 15. A p type impurity is implanted around the groove 15 to form a p<+> gate region 14, an insulating film 16 is shaped onto the inner wall surface of the groove 15, the groove is buried with polycrystalline Si to which an impurity is doped, and a gate capacitor electrode 17 is formed. The surface is coated with a transparent insulating film 12-2, an n<+> source region 18 is shaped into the layer 11, and a source electrode 19 and a gate electrode 20 are formed, thus completing the SIT.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a solid-state imaging device constructed of static induction transistors and a method for manufacturing the same.

[Prior art]

Conventionally, solid-state imaging devices that use charge transfer devices such as COD and BBD, and devices that use MOS transistors have been widely used. A device using an inductive transistor (hereinafter referred to as Sl'l"(!1.4")) has been proposed.

For example, in Japanese Patent Application Laid-open No. 55-15229, SIT
A solid-state imaging device W2 is shown in which the sources are connected to row conductors, the drains are connected to column conductors, and the gates are connected to clear conductors. Figure 1 shows a solid-state imaging device using such an SIT.
A cross-sectional view showing the structure of SIT that constitutes 18It completion,
FIG. 11111 is a partially omitted plan view.

In the figure, l is the n-11 substrate that constitutes the train, and the impurity concentration on the substrate l is 10'! ~1OI
An n-silicon epitaxial layer 2 of l atoms/- is grown, and an n° source region 3 and a p° signal storage gate l region 4 are formed on the surface of this epitaxial layer 2 by thermal diffusion or the like. Usually, this gate region 4 is formed in a ring shape to surround the source region 3, as shown in FIG.
It is formed at a depth shallower than the diffusion depth of .

A source electrode 5 is formed on the source region 3, the surface of the epitaxial layer 2 is covered with a transparent insulating film 6, and a gate electrode 7 is formed on a part of the signal M product gate region 4 via the insulating film 6. There is. A gate capacitor 8 is constituted by the signal storage gate region 4, the insulating film 6 deposited thereon, and the gate electrode 7 further deposited thereon. Also n
- The epitaxial layer 2 constitutes a channel region, and in a steady state with no optical input, that is, even when the gate potential is 0, the channel region is already depleted and the source-drain region is in the forward direction. The structure is such that no current flows between the source trains even when biased.

In the SIT configured in this way, when optical input is applied, hole-electron pairs are generated within the channel region 2 or within the gate depletion layer, and the electrons flow away to the grounded drain 1. , the holes are in the signal storage gate region 4
The voltage is accumulated in the gate capacitor 8 connected to this, and the gate potential is increased. Change only vG. Here, if the capacitance of the gate capacitor 8 is C9, the gate junction capacitance is C4, and the charge generated by optical input and accumulated in the signal storage gate region 4 is QL, then 4■, =QL / (
CG +CJ) After a certain 11 hours have passed,
When the gate read pulse φ4 is applied to the gate terminal 9, the gate potential becomes φ. The potential between the signal storage gate region 4 and the source region 3 decreases, the depletion layer becomes smaller, and a drain current corresponding to the optical input flows between the source and drain. This drain current is due to the amplification effect of SIT. ■. is amplified and magnified, and becomes large. Note that even if the source and drain of the SIT are replaced, the same operation will occur.

By the way, in the solid-state imaging device using SIT as described above, it is an essential requirement to reduce the element area when producing a solid-state imaging device having high resolution.
There is a need to reduce the area of the gate capacitor region. However, in the conventional structure described above, in order to reduce the area of the gate capacitor region and secure the necessary gate capacitor capacity, the gate insulating film must be made extremely thin, which may cause deterioration in breakdown voltage and process control. 6 [Object of the Invention] The present invention was made to solve the problems of the above-mentioned conventional solid-state I imaging device using SIT. The object of the present invention is to provide a solid-state imaging device using an SIT having a gate capacitor region capable of obtaining a capacitance, and a method for manufacturing the same.

[Summary of the invention]

The present invention configures a trench gate capacitor by a gate region formed around a trench formed in a semiconductor substrate and a capacitor electrode embedded in the trench via an insulating film, so that high capacitance can be obtained in a small area. Furthermore, the gate capacitor having the above structure can be easily manufactured using ordinary semiconductor manufacturing technology.

[Embodiments of the invention]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of a solid-state imaging device using 311' and a method of manufacturing the same according to the present invention will be described in detail with reference to the drawings. As mentioned earlier, the SIT operates in the same way even if the source and drain are replaced, so in each of the examples described below, the n-epitaxial A case where a source region and a gate region are formed in a layer will be described.

FIGS. 2A to 2B are diagrams schematically showing cross-sections showing aspects at each manufacturing stage of the SIT constituting an image output element of an embodiment of the SIT solid-state image output device according to the present invention.

In FIG.
An n-epitaxial layer If containing n-type impurities such as phosphorus (P) and antimony (Sb) of Then, a p-game DI region 13 is formed in the n'' epitaaxial layer 11 using conventional photolithography and impurity diffusion methods. At this time, boron (B) is used as an impurity, and the diffusion purity is set to 1 to 4 μm. Then, the surface of the p° game Hff area 13 is made transparent &@marginal film 12-
Cover with 1.

Next, as shown in FIG. A2 (Bl), the transparent insulating film 121
．． The region where the gate capacitor is to be formed is etched and removed by photolithography, and the n-epitaxial layer 11 is etched using the transparent insulating film 12-1 from which the region where the gate capacitor is to be formed is removed as a mask to form a groove 15. Then, in order to form a p° gate region around the trench 15, p
Type impurities, mainly boron (B), are implanted by ion implantation.

Next, as shown in Figure 2 (0), the p-type impurity implanted around the phantom f#15 by the ion injection method is diffused into
A p gate region 14 is formed around the p-gate region 5.

Next, in order to form an insulating film for the gate capacitor, a thermal oxide film is grown on the wall surface of the thin film 15 to form an insulating film 1916 on the inner wall surface of the groove 15. Then, after depositing impurity-doped polycrystalline silicon on the entire surface of the substrate to fill the groove I5, the impurity-doped polycrystalline silicon film deposited on the substrate surface other than the gate capacitor formation region by the photolithography process is removed by etching. A gate capacitor electrode 17 is formed. Through this step, the gate region 14 around the trench 15. Insulating film 16. A groove-shaped gate capacitor, which is a feature of the present invention, is completed, consisting of gate capacitor electrode +7.

Next, as shown in FIG. 2 (01), after covering the substrate surface again with a transparent insulating film 12-2, an n-
An n° source region 18 is formed in the epitaxial layer 11, an AI source electrode 19 is formed in the source region 18, and an A1 gate electrode 20 is formed in the gate capacitor electrode 17 to complete SIT.

In the SIT configured as described above, the gate capacitor is formed using the wall surface of the groove provided in the n-epitaxial layer, so it is possible to significantly reduce the device area while obtaining the desired gate capacitor capacity. can.

In the above embodiment, the gate region 13 disposed to sandwich the source region 18 and the gate region 14 formed around the groove 15 are not shown, but the diffusion formed in the epitaxial layer 11 Combined by layers etc.
The entire gate area formed by them is shown in FIG.
Similar to the conventional SIT shown in FIG. 1, the source region 18 is recessed.

Figures 3-(0) show cross-sections at each manufacturing stage of the SIT constituting the over-chamber element of the second embodiment of the present invention. Identical parts are indicated with the same reference numerals.

In this embodiment, the gate region formed between the source region is provided around the groove formed by digging the n-epitaxial layer, as shown in Fig. 2 (4) to (0). This embodiment is different from the embodiment, and other points are the same as the first embodiment.

That is, as shown in FIG. and this n
- A transparent insulating film 12-I is provided on the epitaxial layer 11, and the transparent insulating film 12-. The two regions where the gate capacitors are to be formed are etched and removed by photolithography, and the n~ epitaxial layer 11 is etched using the transparent insulating film 12° as a mask to form 71115-z.
15-2 is formed. And the lya 15-l+ 15-
In order to form a p° gate region around z, p-type impurities are injected by ion implantation.

Next, as shown in FIG. 3, the ρ-type impurities implanted around the grooves 15-+ and 15-i are diffused by ion implantation to form p-type impurities around the grooves 15-1 and 15-2, respectively. °
In order to form the insulating film of the zero-order straight capacitor forming the gate regions IC, , +4-z, the trenches I5-, . ．．
+5 □ Grow the saccharine on the wall, l thin 15-,,
Insulating films 16-+ and 16- are formed on the inner wall surfaces of 15.2, respectively.

Next, as shown in FIG. 3 fC1, impurity-topped polycrystalline silicon is deposited on the entire surface of the substrate.
After filling in, take a photo! By etching the impurity-doped polycrystalline silicon film deposited on the substrate surface other than the gate capacitor formation region by the Sogerahu etching process, the gate capacitor electrode 17. ,,17-z
form each. Then, the substrate surface is covered again with a transparent insulating film 12-2.

Next, as shown in FIG. 3), both gate regions 14-. ．． An n''Es region 18 is formed in the n-epitaxial layer 11 between 14-z, and a ^l source electrode 19 is formed in the source region 18, and an A! gate electrode 20 is formed in the gate capacitor electrode 17-1, and SIT is performed. complete.

In this embodiment, the gate region +4− sandwiching the source region 18 is
, , 1.4-t are all formed around the trench, and the gate capacitor is formed using the wall surface of the trench. It is possible to further reduce the element area.

In this embodiment as well, both gate regions IC,,14,2
are coupled by a p diffusion layer to the epitaxial Jllll or by trenches 15-. ．． They are coupled by a diffusion layer formed around a thin layer similar to +5-z, and the entire gate region is arranged so as to surround the source region 18.

4 to +Dl shows a third embodiment of the present invention, and the same parts as in the embodiment shown in FIGS.

In this embodiment, a shallow p'' gate region is formed by extending the gate region in the second embodiment shown in FIGS. 3-101 on the side opposite to the side facing the source region. That is, as shown in FIG. 4, first, an n-epitaxial layer 11 is formed on an n-silicon substrate 10, a transparent insulating layer 12-. By law n
- Two shallow p° gate strings MA14-ff spaced apart in epitaxial N11.

14-, and again p3 gate subregion 14-z, 1
The surface of 4-4 is covered with a transparent insulating film 12-1.

Next, as shown in FIG. 4 (Sun), the transparent insulating film 12 is
-1 by photolithography, the shallow p.

The gate capacitor formation area adjacent to the gate 81 areas 14-i and 14-4 is etched and removed, and the n-epitaxial layer 1 is etched using this transparent insulating MIL as a mask.
1 to form grooves 15-. ．． 15-t is formed.

Then, the groove 15-. ．． P-type impurities are implanted by ion implantation in order to form a p gate region around 15-1.

Next, as shown in FIG. 40, the p-type impurity implanted around the grooves 15-+ and l5-t by the ion implantation method is diffused to form the above-mentioned P' gate regions 14-+ and 14-z are formed so as to be coupled to shallow p' gate regions 14-3+ and 14-a, respectively.

Hereinafter, the insulating film 16 for the gate capacitor 16-
+, 16-z, gate capacitor electrode 17-, 174
, the source region 18, etc. are formed, as shown in FIG. As shown in D1, a shallow p
° game) A SIT with a fiJI region is obtained.

Although this embodiment has a slightly larger element area than the second embodiment shown in FIG. Also, deterioration of sensitivity to short wavelength light is not a problem.

〔Effect of the invention〕

As described above in detail based on the embodiments, according to the present invention, the gate capacitor is formed using the wall surface of the groove formed by digging into the semiconductor substrate, so that a high capacitance gate capacitor can be formed. It becomes possible to form the element in an extremely small area, and as a result, the element area can be significantly reduced.

Moreover, an SI equipped with a trench gate capacitor having such a configuration
A solid-state imaging device using T does not require any special manufacturing process and can be easily manufactured using normal semiconductor manufacturing techniques.

[Brief explanation of the drawing]

Figure 1^ is a cross-sectional view of the SIT that constitutes the transient chamber element of a solid-state II imager using a conventional SIT.
The partially omitted plan view and FIGS. 2 to 1 are cross-sectional views showing aspects of each manufacturing step of the SIT constituting an image sensor of the first example of the SIT solid-state imaging device according to the present invention. , Figures 3 to (b) are cross-sectional views showing aspects at each manufacturing stage of the SIT of the second embodiment, and Figures 4 to (b) show aspects a at each manufacturing stage of the SIT of the third embodiment. FIG. In the figure, IO is an n-silicon base layer, 11 is an n-layer insulating layer, Il, 12-□ is a transparent insulating film, and 13
is a deep p° gate region, 14.14-6.14-t is a p° gate region around the trench, 14-i, 14- is a shallow p° gate region, 15.15-5.15-t is a trench, 16.16
-4.16-! is the gate capacitor insulation film, 17.17
-1.17-z indicates a gate capacitor electrode, and 18 indicates an n source region. Patent applicant: Olympus Optical Industry Co., Ltd. Figure 1 (A) (B) East Figure 2 Figure 3

Claims (2)

[Claims] (1) In a solid-state imaging device using a static induction transistor, a gate capacitor consists of a gate region formed around a groove formed in a semiconductor substrate, and a capacitor electrode embedded in the groove with an insulating film interposed therebetween. A solid-state imaging device comprising a static induction transistor. (2) In a solid-state imaging device using a static induction transistor, the gate capacitor of the static induction transistor is formed by digging a groove in the semiconductor substrate, injecting an impurity into the groove by ion implantation, and then diffusing it. After forming a gate region and then growing a thermal oxide film on the wall of the trench,
A method for manufacturing a solid-state imaging device, characterized in that the solid-state imaging device is formed by embedding an impurity-doped polycrystalline silicon film.