JP2000101922A - Charge transfer device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the transfer characteristic of a charge transfer device by transferring charge, even when the exclusive drive pulse that is applied to a transfer electrode of the final stage is set at a reference voltage level (0 V). SOLUTION: A final stage transfer electrode drive circuit is driven by the single power voltage and generates a final stage-only pulse that varies among three value, i.e., the positive negative and reference potential levels. Thus, the potential of an output gate 4 can be transferred to a charge detection part 5 via a place set under the final stage electrode of signal charge through a place set under the gate 4, not only when the output of the final stage transfer electrode drive circuit has the same polarity as that of the signal charge but also when the output is lower than the reference potential level.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a charge transfer device, and more particularly to a charge transfer device in which a set of transfer electrodes is constituted by a plurality of transfer electrodes adjacent to each other in a transfer direction, and a plurality of sets of transfer electrodes are arranged along the transfer direction. The present invention relates to a charge transfer device which is arranged and applies a drive pulse different from other transfer electrodes to a final-stage transfer electrode to reduce the potential at the time of non-accumulation below the final-stage electrode.

[0002]

2. Description of the Related Art A solid-state image pickup device comprising a charge-coupled device is very often used as an image pickup device for a video camera, a still camera or the like. Such a type of solid-state imaging device generally includes a plurality of light receiving elements arranged in a matrix, and a vertical transfer register for vertically transferring a signal charge from the light receiving element corresponding to each light receiving element vertical column. A horizontal transfer register is provided on the transfer destination side of the vertical transfer register to transfer the signal charges transferred vertically in the horizontal direction, and the horizontally transferred signal charges are converted into a voltage at an output section provided on the horizontal transfer destination side. And sends it out of the solid-state imaging device. FIG. 3A is a schematic configuration diagram of a transfer destination side portion and an output section of a horizontal transfer register of the solid-state imaging device.

[0003] 1 is a semiconductor substrate, 2 is a gate insulating film, 3 is a horizontal transfer electrode, is disposed on the gate insulating film 3 along the horizontal transfer direction. Transfer portions and storage portions are alternately arranged along the horizontal transfer direction in a portion of the surface of the semiconductor substrate 1 below the region where the horizontal transfer electrodes 3 are formed.
In this case, the potential is different when the same voltage is received, and the storage portion is formed so as to be appropriately deeper (impurity concentration profile setting). Reference numeral 3t denotes a transfer electrode for driving the transfer section of the horizontal transfer electrodes 3, and 3s denotes a transfer electrode for driving the storage section.

[0004] 3lt is a horizontal transfer electrode 3 at the last stage.
1 is a transfer electrode for driving a transfer unit,
3ls is a transfer electrode that also drives the storage unit. This horizontal transfer register includes two-phase drive pulses φ1,
Driven by φ2. 4 is the last horizontal transfer electrode 3l
An output gate electrode 5 formed adjacent to s is a floating diffusion region formed on the surface of the semiconductor substrate 1 and is formed adjacent to the horizontal transfer destination side of the output gate electrode 4 when viewed from above. . Reference numeral 6 denotes a reset drain region formed as appropriately separated from the floating diffusion region 5, and reference numeral 7 denotes a reset gate electrode formed between the two regions 5 and 6 with the gate insulating film 2 interposed therebetween. A reset MOS transistor is constituted by 5, 6 and the reset gate electrode 7.

FIG. 3 (B) shows a change in potential of each portion shown in FIG. 3 (A). The horizontal transfer is basically performed by alternately changing the two-phase driving pulses φ1 and φ2 to a high level (+5 V) or a low level (0 V). However, the final stage transfer electrode 3l
t, 3ls is driven by a dedicated driving pulse φL2
And changes between −5 V, 0 V (reference potential), and +5 V. When the transfer electrodes 3lt and 3ls at the final stage have a negative level (−5V), the signal charges are transferred to the floating diffusion region 5 via the horizontal gate electrode 4 kept at a constant potential and converted into a voltage. Are output to the outside of the solid-state imaging device via an output circuit (not shown).

The pulse applied to the final-stage transfer electrodes 3lt and 3ls is not φ2, but a special ternary driving pulse φ2L lower than 0 V, that is, a negative potential is set to a non-accumulated time. Of the final stage transfer electrodes 3lt and 3ls (particularly 3ls
This is because the dynamic charge can be sufficiently ensured while the signal charge of (lower) can be completely discharged to the floating diffusion region 5 side under the output gate 4.

In order to generate a driving pulse φ2L (a pulse whose output changes between -3 V, 0 V, and +5 V) dedicated to the final-stage transfer electrode in an IC operating at a power supply voltage of 5 V, FIG. Has a pulse generation circuit (not shown).

FIGS. 3 (C) and 3 (D) show examples of different time charts for φ1, φ2L and reset gate pulse φRG.

[0009]

However, FIG.
In each of the examples shown in (C) and (D), the period t2 during which the drive pulse φ2L dedicated to the transfer electrode in the final stage has a value of 0 V did not sufficiently contribute to the transfer. This is because conventionally, when the driving pulse φ2L is 0 V, the potential of the storage section at the final stage is deeper than the potential under the output gate 4. 3C and 3D, the period indicated by t1 is a storage period in which the dedicated drive pulse φ2L is + 5V, and the period indicated by t2 is a period in which the dedicated drive pulse φ2L is 0V. , T3 is a transfer (transfer) period in which the dedicated drive pulse φ2L is −5V. Then, only t3 [: t3 / (t1 + t2 + t3)] in one pulse period (t1 + t2 + t3) is a period during which transfer is performed.

As described above, the transfer pulse (φ1, φ2) cannot be sufficiently contributed to the transfer of the signal charge during the period t2.
2 and φ2L), there is a problem that it is difficult to completely perform the charge transfer in each period. Of course,
If the 0V period is not generated at all, such a problem does not occur. However, a booster circuit is required to generate a ternary pulse from a single power supply. It is inevitable that this period will occur.

The present invention has been made to solve such a problem, and a plurality of transfer electrodes adjacent to each other in the transfer direction form a set of transfer electrodes. A drive pulse different from the other transfer electrodes, which is arranged so as to be arranged along the third transfer electrode, and is applied with a ternary pulse that changes to a negative voltage, a reference voltage (0 V), and a positive voltage, is applied. In a charge transfer device with a shallow potential at the time of non-accumulation under the step electrode,
It is an object to improve transfer characteristics by enabling transfer even when the drive pulse applied to the final-stage transfer electrode is at a reference voltage (0 V).

[0012]

According to a first aspect of the present invention, there is provided a charge transfer device which is driven by a single power supply voltage and generates a last stage dedicated pulse which changes between three values of plus, minus and a reference potential. It has an electrode drive circuit, and outputs the potential of the output gate from below the last electrode of the signal charge even when the output of the last-stage transfer electrode drive circuit has the same polarity as the polarity of the signal charge and at the reference potential. It is characterized in that it can be transferred to the charge detection section through below the gate.

Therefore, according to the charge transfer device of the first aspect, not only when the pulse dedicated to the final-stage transfer electrode has the same polarity as the signal charge (when the signal charge is an electron, it has a negative potential) but also at the reference potential ( Also at 0 V), the signal charge can be swept out to the charge detection section side under the output gate, so that the transfer characteristics can be further improved.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The charge transfer device of the present invention basically comprises a set of transfer electrodes composed of a transfer portion adjacent to a transfer direction and a plurality of transfer electrodes located on a storage portion. The transfer pulse is arranged so that the transfer electrodes are arranged along the transfer direction, the charge detection unit is adjacent to the last-stage transfer electrode via an output gate, and the transfer pulse that drives the other-stage transfer electrode to the other-stage transfer electrode It is driven by another final stage dedicated pulse, and operates by receiving as a power supply voltage a potential difference between a reference potential and a power supply potential of a polarity (for example, plus) opposite to the polarity (for example, minus) of a signal charge (for example, electrons). A charge transfer device, comprising a CCD
A horizontal transfer register of a solid-state image sensor is a typical example of the application of the present invention. However, the present invention is not limited to this. For example, the present invention can be applied to a CCD type delay device.

The final-stage transfer electrode drive circuit operates with a single power supply (for example, +5 V power supply), and has a ternary pulse [reference potential (: 0 V), a power supply potential (for example, +5 V), and a power supply potential opposite to the power supply potential. Polarity potential (for example, -5 V)], and receives a pulse that changes between the reference potential and the power supply potential and generates a final-stage dedicated pulse that changes between three values of plus, minus, and the reference potential. I do. The power source is a plus power source when the signal charge is an electron (generally an electron), and a minus power source when the signal charge is a hole. When operating with a positive power supply, setting the drive pulse to a negative value means connecting a capacitive element to the drive pulse output point, and setting the non-output point side of the capacitive element to a positive potential when the output point is 0V. When the point at which the value should be negative is reached, the opposite output point side of the capacitive element is set to 0.
V. This specific example is shown in FIG. 2, and the configuration and operation will be described later in detail.

As described above, it is necessary to set the potential under the output gate such that the signal charge can be completely transferred even when the driving pulse for driving the final-stage transfer electrode is 0 V (reference potential). This can be realized by making the impurity concentration profile the same as that of the storage section below the transfer electrode and applying a reference potential to the output gate. By doing so, the impurity concentration profile under the output gate can be made the same as the impurity concentration profile of each storage section, and a step only for forming the output gate section can be eliminated, and the charge of the present invention can be obtained without increasing the number of steps. A transfer device can be obtained.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail with reference to the illustrated embodiments. FIGS. 1A to 1C show a charge transfer device according to the present invention.
FIG. 6A is a schematic diagram showing a transfer destination side portion and an output section of a horizontal transfer register according to an embodiment applied to a horizontal transfer register of a CD-type solid-state imaging device.

In the drawing, 1 is a semiconductor substrate, 2 is a gate insulating film, 3 is a horizontal transfer electrode, which is disposed on the gate insulating film 3 along the horizontal transfer direction. Transfer portions and storage portions are alternately arranged along the horizontal transfer direction in a portion of the surface of the semiconductor substrate 1 below the region where the horizontal transfer electrodes 3 are formed, and the same voltage is applied to the transfer electrodes 3 in the transfer portion and the storage portion. (Impurity concentration profile setting) such that the potential at the time of receiving the storage portion is different, and the storage portion is appropriately deepened. 3
t is a transfer electrode for driving the transfer section of the horizontal transfer electrodes 3, and 3s is a transfer electrode for driving the storage section.

3lt is the last horizontal transfer electrode 3
1 is a transfer electrode for driving a transfer unit,
3ls is a transfer electrode that also drives the storage unit. This horizontal transfer register is driven by two-phase drive pulses φ1 and φ2 except for the final-stage transfer electrode 31. 4
Is an output gate electrode formed adjacent to the horizontal transfer electrode 3ls at the last stage. In this embodiment, 0V (reference potential:
0V) is applied. The portion of the surface of the semiconductor substrate 1 below the output gate 4 has the same impurity concentration profile as the storage portion of each of the horizontal transfer electrodes 3 and 3l.

Reference numeral 5 denotes a floating diffusion region formed on the surface of the semiconductor substrate 1, and is formed adjacent to the horizontal transfer destination of the output gate electrode 4 when viewed from above. 6 is the floating diffusion region 5
A reset drain region 7 is formed at an appropriate distance from the reset drain electrode, and a reset gate electrode 7 is formed between the two regions 5 and 6 with the gate insulating film 2 interposed therebetween. 7 constitute a reset MOS transistor.

FIG. 1B is a diagram showing a change in potential of each portion shown in FIG. 1A, and FIG. 1C is a pulse chart showing horizontal transfer driving pulses φ1 and φ2L and a reset gate pulse φRG. The horizontal transfer is basically performed by alternately changing the two-phase pulses φ1 and φ2 to a high level (+5 V) or a low level (0 V). However, the drive pulse pulse φ2L dedicated to driving the transfer electrodes 3lt and 3ls in the final stage changes between −5V, 0V (reference potential) and + 5V. Of course, when the final-stage transfer electrodes 3lt and 3ls become a minus level (-5V), the signal charges are transferred to the floating diffusion region 5 via the horizontal gate electrode 4 kept at a constant potential and converted into a voltage. Are output to the outside of the solid-state imaging device via an output circuit. In the present charge transfer device, not only that, but also the final-stage transfer electrodes 3lt and 3ls have 0V.
Also contributes sufficiently to the transfer.

This is because the portion under the output gate 4 has the same impurity concentration profile as that of the storage section under the transfer electrode 3ls of the final stage (of course, the storage section may be the transfer electrode of the final stage, Department,
These are the same impurity concentration profiles. Since 0 V is applied to the output gate 4, when the final-stage dedicated drive pulse φ2L becomes 0 V, the potential under the final-stage transfer electrode 3ls and the potential under the output gate 4 become equal, Since the potential under the final-stage transfer electrode 3lt (transfer portion) is naturally shallower than that, the signal charge under the final-stage transfer electrode 3ls is transferred through the output gate 4 to the floating diffusion region 5d.
It can be effectively transferred to

Therefore, the period of the drive pulse φ2L (: t1
+ T2 + t3, of course the same as the period of the pulses φ1 and φ2)
Of the transfer period (t2 + t3) to (t2
+ T3) / (t1 + t2 + t3), and the transfer characteristics can be improved.

FIGS. 2A and 2B are diagrams for explaining a final-stage transfer electrode drive circuit that generates the three-valued final-stage drive pulse φ2L. FIG. 2A is a circuit diagram, and FIG. () Is a time chart for explaining the operation. In FIG.
M1 is a P-channel MOS transistor (enhancement mode), the source of which is connected to the + 5V power supply terminal, the pulse φD is applied to the gate, and the drain is connected to the output terminal of the final stage transfer electrode drive generation circuit. ing. From the output terminal, the drive pulse φ2L dedicated for the final stage
Is output. M2 is a depletion-mode P-channel MOS transistor, the source of which is connected to the output terminal of the final-stage transfer electrode drive circuit, the pulse φA is applied to the gate, and φD2 is applied to the drain. C1 is a capacitor for transmitting a voltage change. One end is connected to the output terminal of the final-stage transfer electrode drive circuit, and the other end is supplied with a pulse φC.

First, when the output φ2L is 0 V (at time t
The state in a) will be described. At this time, φD is + 5V
Therefore, the MOS transistor M1 which receives it at the gate is turned off, and since φA is 0 V, the MOS transistor M2 of the depletion mode which receives it at the gate is turned on.
Since φD2 applied to the drain is 0V, the output terminal of the pulse generation circuit is 0V. That is, φ2L is 0V. At this time, φC applied to the terminal on the side opposite to the output terminal (the other end) of the capacitor C2 is 5V.

Next, at time tb, φA is changed from 5V to 0.
V, whereby the MOS transistor M2 is turned off, the output terminal of the final-stage transfer electrode drive generation circuit becomes floating, and at the same time, φC becomes 5
Since the voltage is inverted from V to 0 V, the potential change is transmitted to the output terminal of the final-stage transfer electrode drive generation circuit through the capacitor C1, and the output terminal is reduced by 5V. That is, from 0V-
It changes to 5V. tc is the output terminal, that is, φ2L is −
This shows the time point when 5 V is maintained.

Next, at time td, φD changes from 5V to 0.
V, and the MOS transistor M1 is turned on. Then, the output terminal of the final stage transfer electrode drive circuit is 5V
Is charged up by the power supply voltage. As a result, φ
2L is boosted from -5V to + 5V. At this time td, φD2 is changed from 0 V to 5 V, and preparations for the next drop in output voltage begin. te is + 5V for φ2L
Indicates the point at which Next, at time tf, φD becomes 0V.
To + 5V, the MOS transistor M1 is turned off, φA is turned off from 5V to 0V, the MOS transistor M2 is turned on, and φD2 is changed from 5V to 0V. become. tg indicates the time when the output terminal maintains 0V.

Thereafter, the above operation is repeated. To summarize such an operation, the output terminal of the final-stage transfer electrode drive circuit is set to 0 V by the pulse φD2 through the MOS transistor M2, and then the MOS transistor M2 is turned off to set it in a floating state.
A voltage drop from V to 0 V is caused, and the voltage drop is transmitted to the output terminal through the capacitor C1, whereby the voltage at the output terminal, which was 0 V, is reduced to -5V. Then, the MOS transistor M1 is turned on, and the output terminal is charged up to +5 V by the power supply voltage. And M
The OS transistor M1 is turned off, the MOS transistor M2 is turned on, and the output terminal is set to 0V by setting φD2 to 0V.

As described above, the operation of the charge transfer device shown in FIG. 1 can be performed by using the final-stage transfer electrode drive circuit capable of outputting ternary values with a single positive power supply. Of course, the circuit shown in FIG. 2 is not limited to the one shown in FIG. 2 as long as it can be changed between, for example, +5 V, 0 V, and -5 V with a single power supply. It's just

[0030]

According to the charge transfer device of the first aspect, not only when the drive pulse dedicated to the final-stage transfer electrode has the same polarity as the signal charge (when the signal charge is an electron, it has a negative potential), but also when the reference pulse has a negative potential. Even at the potential (0 V), the signal charge can be completely swept out to the charge detection unit side through the lower part of the output gate.
Transfer characteristics can be further improved.

According to the charge transfer device of the present invention, the portion under the output gate has the same impurity concentration profile as the storage portion below the transfer electrode, and the reference potential is applied to the output gate. The potential can be set such that the signal charge can be completely transferred even when the driving pulse for driving the final-stage transfer electrode is 0 V (reference potential). Then, since the output gate has the same impurity concentration profile as that of each storage section, it is possible to eliminate a step only for the output gate section and further increase the number of steps without increasing the number of steps. Can be obtained.

[Brief description of the drawings]

1 (A) to 1 (C) show a charge transfer device of the present invention using a CCD.
FIG. 1A shows an embodiment applied to a horizontal transfer register of a solid-state image sensor, in which FIG. 1A is a schematic configuration diagram of a transfer destination portion and an output unit of the horizontal transfer register, and FIG. FIG. 7C is a waveform diagram showing horizontal transfer driving pulses φ1 and φ2L and a reset gate pulse φRG.

FIGS. 2A and 2B are diagrams for explaining a final-stage drive pulse generation circuit that generates the above-described three-valued final-stage drive pulse φ2L, where FIG. 2A is a circuit diagram and FIG. Is a time chart for explaining the operation.

FIGS. 3A to 3D are diagrams for explaining a conventional example, in which FIG. 3A is a schematic configuration diagram of a transfer destination side portion and an output unit of a horizontal transfer register of a solid-state imaging device, and FIG. FIG. 3 (A)
FIGS. 7C and 7D are diagrams showing examples of different time charts for φ1, φ2L, and reset gate pulse φRG, respectively.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Substrate, 2 ... Gate insulating film, 3 ... Transfer electrode, 3lt, 3ls ... Last stage transfer electrode, 4 ... Output gate, 5 ... Charge detection part (floating diffusion area) ), Φ2L... Drive pulse dedicated to the final stage.

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[Procedure amendment]

[Submission date] April 12, 1999 (1999.4.1
2)

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] Claim 1

[Correction method] Change

[Correction contents]

[Procedure amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0003

[Correction method] Change

[Correction contents]

[0003] Reference numeral 1 denotes a semiconductor substrate, 2 denotes a gate insulating film, and 3 denotes a horizontal transfer electrode, which is disposed on the gate insulating film 2 along the horizontal transfer direction. Transfer portions and storage portions are alternately arranged along the horizontal transfer direction in a portion of the surface of the semiconductor substrate 1 below the region where the horizontal transfer electrodes 3 are formed.
In this case, the potential is different when the same voltage is received, and the storage portion is formed so as to be appropriately deeper (impurity concentration profile setting). Reference numeral 3t denotes a transfer electrode for driving the transfer section of the horizontal transfer electrodes 3, and 3s denotes a transfer electrode for driving the storage section.

[Procedure amendment 3]

[Document name to be amended] Statement

[Correction target item name] 0005

[Correction method] Change

[Correction contents]

FIG. 3 (B) shows a change in potential of each portion shown in FIG. 3 (A). The horizontal transfer is basically performed by alternately changing the two-phase driving pulses φ1 and φ2 to a high level (+5 V) or a low level (0 V). However, the final stage transfer electrode 3l
t, 3ls are driven by a dedicated driving pulse φ 2L
And changes between −5 V, 0 V (reference potential), and +5 V. When the transfer electrodes 3lt and 3ls at the final stage have a negative level (−5V), the signal charges are transferred to the floating diffusion region 5 via the horizontal gate electrode 4 kept at a constant potential and converted into a voltage. Are output to the outside of the solid-state imaging device via an output circuit (not shown).

[Procedure amendment 4]

[Document name to be amended] Statement

[Correction target item name] 0012

[Correction method] Change

[Correction contents]

[0012]

According to a first aspect of the present invention, there is provided a charge transfer device which is driven by a single power supply voltage and generates a last stage dedicated pulse which changes between three values of plus, minus and a reference potential. an electrode driving circuit, the potential of the output gate, the output is not a Minara when the same polarity as the signal charge of the final stage transfer electrode driving circuit, the lower the final stage electrode of the even signal charge at the reference potential It is characterized in that it can be transferred to the charge detection section through the lower part of the output gate.

[Procedure amendment 5]

[Document name to be amended] Statement

[Correction target item name] 0016

[Correction method] Change

[Correction contents]

As described above, setting the potential under the output gate to a potential at which signal charges can be transferred even when the drive pulse for driving the final-stage transfer electrode is at 0 V (reference potential) is as follows. This can be realized by making the impurity concentration profile the same as that of the lower storage section and applying a reference potential to the output gate. In this way, the portion under the output gate can have the same impurity concentration profile as each storage section, and a step only for forming the output gate section can be eliminated.
The charge transfer device of the present invention can be obtained without increasing the number of steps.

[Procedure amendment 6]

[Document name to be amended] Statement

[Correction target item name] 0018

[Correction method] Change

[Correction contents]

In the drawings, reference numeral 1 denotes a semiconductor substrate, 2 denotes a gate insulating film, and 3 denotes a horizontal transfer electrode, which is disposed on the gate insulating film 2 along the horizontal transfer direction. Transfer portions and storage portions are alternately arranged along the horizontal transfer direction in a portion of the surface of the semiconductor substrate 1 below the region where the horizontal transfer electrodes 3 are formed, and the same voltage is applied to the transfer electrodes 3 in the transfer portion and the storage portion. (Impurity concentration profile setting) such that the potential at the time of receiving the storage portion is different, and the storage portion is appropriately deepened. 3
t is a transfer electrode for driving the transfer section of the horizontal transfer electrodes 3, and 3s is a transfer electrode for driving the storage section.

[Procedure amendment 7]

[Document name to be amended] Statement

[Correction target item name] 0026

[Correction method] Change

[Correction contents]

Next, at time tb, φA is changed from 5V to 0.
V, whereby the MOS transistor M2 is turned off, the output terminal of the final-stage transfer electrode drive generation circuit becomes floating, and at the same time, φC becomes 5
Since the voltage is inverted from V to 0 V, the potential change is transmitted to the output terminal of the final-stage transfer electrode drive generation circuit through the capacitor C1, and the output terminal is lowered by 5V. That is, from 0V-
It changes to 5V. tc is the output terminal, that is, φ2L is −
This shows the time point when 5 V is maintained.

[Procedure amendment 8]

[Document name to be amended] Statement

[Correction target item name] 0030

[Correction method] Change

[Correction contents]

[0030]

According to the charge transfer device of the first aspect, not only when the drive pulse dedicated to the final-stage transfer electrode has the same polarity as the signal charge (when the signal charge is an electron, it has a negative potential), but also when the reference pulse has a negative potential. Also at the time of the potential (0 V), the signal charge can be swept out to the charge detection unit side through the lower part of the output gate, so that the transfer characteristics can be further improved.

[Procedure amendment 9]

[Document name to be amended] Statement

[Correction target item name] 0031

[Correction method] Change

[Correction contents]

According to the charge transfer device of the present invention, the portion under the output gate has the same impurity concentration profile as the storage portion below the transfer electrode, and the reference potential is applied to the output gate. The potential can be set to a potential at which signal charges can be transferred even when a driving pulse for driving the final-stage transfer electrode is 0 V (reference potential). Then, since the output gate has the same impurity concentration profile as that of each storage section, it is possible to eliminate a step only for the output gate section and further increase the number of steps without increasing the number of steps. Can be obtained.

[Procedure amendment 10]

[Document name to be amended] Statement

[Correction target item name] Figure 3

[Correction method] Change

[Correction contents]

FIGS. 3A to 3D are diagrams for explaining a conventional example, in which FIG. 3A is a schematic configuration diagram of a transfer destination side portion and an output unit of a horizontal transfer register of a solid-state imaging device, and FIG. FIG. 3 (A)
(C), (D) is a diagram showing another example of a time chart for φ1, φ2L, and reset gate pulse φRG, respectively.

[Procedure amendment 11]

[Document name to be amended] Drawing

[Correction target item name] Fig. 1

[Correction method] Change

[Correction contents]

FIG.

Claims (2)

[Claims] 1. A set of transfer electrodes is constituted by a transfer section adjacent to a transfer direction and a plurality of transfer electrodes located on a storage section, and a plurality of sets of transfer electrodes are arranged so as to be arranged in the transfer direction. The charge detection unit is adjacent to the final-stage transfer electrode via the output gate, and the final-stage transfer electrode is driven by a final-stage-dedicated drive pulse different from the transfer pulse that drives the other transfer electrodes. Potential and
A charge transfer device that operates by receiving, as a power supply voltage, a potential difference between a power supply potential of a polarity (for example, negative) and a polarity (for example, negative) of a signal charge (for example, electrons), and the reference potential or the power supply potential, A final-stage transfer electrode driving circuit that generates a final-stage dedicated pulse that changes between three values of plus, minus, and the reference potential in response to the pulse that changes between the reference potential and the power supply potential; The potential is apparent when the output of the last-stage transfer electrode drive circuit has the same polarity as the polarity of the signal charge, and also transfers the signal charge from below the last-stage transfer electrode to below the output gate to the charge detection unit even at the reference potential. A charge transfer device characterized by being able to perform. 2. The charge transfer device according to claim 1, wherein the portion under the output gate has the same impurity concentration profile as the storage portion under the transfer electrode, and the reference potential is applied to the output gate. .