JPS6041375A - Solid-state image pickup element - Google Patents
Solid-state image pickup elementInfo
- Publication number
- JPS6041375A JPS6041375A JP59135290A JP13529084A JPS6041375A JP S6041375 A JPS6041375 A JP S6041375A JP 59135290 A JP59135290 A JP 59135290A JP 13529084 A JP13529084 A JP 13529084A JP S6041375 A JPS6041375 A JP S6041375A
- Authority
- JP
- Japan
- Prior art keywords
- charge
- potential
- capacity
- transistor
- signal line
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000003990 capacitor Substances 0.000 claims description 29
- 238000003384 imaging method Methods 0.000 claims description 13
- 239000000758 substrate Substances 0.000 claims description 6
- 239000011159 matrix material Substances 0.000 claims description 3
- 239000004065 semiconductor Substances 0.000 claims description 3
- 101150079361 fet5 gene Proteins 0.000 abstract 1
- XEBWQGVWTUSTLN-UHFFFAOYSA-M phenylmercury acetate Chemical compound CC(=O)O[Hg]C1=CC=CC=C1 XEBWQGVWTUSTLN-UHFFFAOYSA-M 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 14
- 230000008878 coupling Effects 0.000 description 3
- 238000010168 coupling process Methods 0.000 description 3
- 238000005859 coupling reaction Methods 0.000 description 3
- AMHIJMKZPBMCKI-PKLGAXGESA-N ctds Chemical compound O[C@@H]1[C@@H](OS(O)(=O)=O)[C@@H]2O[C@H](COS(O)(=O)=O)[C@H]1O[C@H]([C@@H]([C@H]1OS(O)(=O)=O)OS(O)(=O)=O)O[C@H](CO)[C@H]1O[C@@H](O[C@@H]1CO)[C@H](OS(O)(=O)=O)[C@@H](OS(O)(=O)=O)[C@@H]1O[C@@H](O[C@@H]1CO)[C@H](OS(O)(=O)=O)[C@@H](OS(O)(=O)=O)[C@@H]1O[C@@H](O[C@@H]1CO)[C@H](OS(O)(=O)=O)[C@@H](OS(O)(=O)=O)[C@@H]1O[C@@H](O[C@@H]1CO)[C@H](OS(O)(=O)=O)[C@@H](OS(O)(=O)=O)[C@@H]1O[C@@H](O[C@@H]1CO)[C@H](OS(O)(=O)=O)[C@@H](OS(O)(=O)=O)[C@@H]1O2 AMHIJMKZPBMCKI-PKLGAXGESA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 101710116852 Molybdenum cofactor sulfurase 1 Proteins 0.000 description 1
- 210000000436 anus Anatomy 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000013256 coordination polymer Substances 0.000 description 1
- 230000001808 coupling effect Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- KRTSDMXIXPKRQR-AATRIKPKSA-N monocrotophos Chemical compound CNC(=O)\C=C(/C)OP(=O)(OC)OC KRTSDMXIXPKRQR-AATRIKPKSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/60—Noise processing, e.g. detecting, correcting, reducing or removing noise
- H04N25/67—Noise processing, e.g. detecting, correcting, reducing or removing noise applied to fixed-pattern noise, e.g. non-uniformity of response
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/60—Noise processing, e.g. detecting, correcting, reducing or removing noise
- H04N25/62—Detection or reduction of noise due to excess charges produced by the exposure, e.g. smear, blooming, ghost image, crosstalk or leakage between pixels
- H04N25/621—Detection or reduction of noise due to excess charges produced by the exposure, e.g. smear, blooming, ghost image, crosstalk or leakage between pixels for the control of blooming
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/60—Noise processing, e.g. detecting, correcting, reducing or removing noise
- H04N25/62—Detection or reduction of noise due to excess charges produced by the exposure, e.g. smear, blooming, ghost image, crosstalk or leakage between pixels
- H04N25/625—Detection or reduction of noise due to excess charges produced by the exposure, e.g. smear, blooming, ghost image, crosstalk or leakage between pixels for the control of smear
Landscapes
- Engineering & Computer Science (AREA)
- Multimedia (AREA)
- Signal Processing (AREA)
- Solid State Image Pick-Up Elements (AREA)
- Transforming Light Signals Into Electric Signals (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の利用分野〕
本発明は、半導体基板上に形成された、受光部にホトダ
イオードとスイッチ用MOSトランジスタ(以下本明細
書においてはMO8Tと略称する。DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention provides a photodiode and a switching MOS transistor (hereinafter abbreviated as MO8T in this specification) formed on a semiconductor substrate.
)とからなる画素をマトリックス状に並べたセンサを配
し、読出し用電荷移送素子(以下本明細書においてはC
T D (Charge Transfer Devi
ce)と略称する。)を有し、センサ部の信号出力線と
CTD入力端子の間に水平スイッチ用MO8T(以下本
明細書においては5M08Tと略称する。)、転送用M
O8T、および水平スイッチ用MO8′Fと転送用MO
8Tの結合点に接続された蓄積容量を有する固体撮像素
子に関する。) is arranged in a matrix, and a readout charge transfer element (hereinafter referred to as C
T D (Charge Transfer Devi
ce). ), and an MO8T for horizontal switch (hereinafter abbreviated as 5M08T in this specification) and an M for transfer between the signal output line of the sensor section and the CTD input terminal.
O8T, horizontal switch MO8'F and transfer MO
The present invention relates to a solid-state image sensor having a storage capacitor connected to an 8T coupling point.
第1図は従来の固体撮像装置の構成を示す(実願昭54
−157030号)。図中、■はp−n接合がら成るホ
トダイオード、2は垂直スイッチ用MO3T(以下本明
細書においてはVMO8Tと略称する。)、3はこのM
O8TをクロックφVで順次スイッチングするスキャナ
、4は垂直の信号線、5は水平スイッチ用MO8T (
以下本明細書においては5M08Tと略称する。)、6
は水平読出し用CTD、7はCTD6に接続された前置
増幅器、8は転送用MO8T、9は蓄積容量、10はリ
セット用MO8Tである。第2図は、横軸に時間を、縦
軸に電位をとって、第1図に示す固体撮像装置の駆動パ
ルスのタイミングの一例を示す図で縦軸の電位は図の上
に向って高く、例えばφ×に示すパルスが印加されたと
きに5M03Tは導通状態になることを意、味する。以
下、第2図のタイミング・チャートを用いて第」1図に
示す装置の動作を説明する。Figure 1 shows the configuration of a conventional solid-state imaging device (Jet No. 54
-157030). In the figure, ■ is a photodiode consisting of a p-n junction, 2 is a vertical switch MO3T (hereinafter abbreviated as VMO8T in this specification), and 3 is this M
A scanner that sequentially switches O8T with clock φV, 4 is a vertical signal line, 5 is MO8T for horizontal switch (
Hereinafter, it will be abbreviated as 5M08T in this specification. ), 6
7 is a preamplifier connected to the CTD 6, 8 is a transfer MO8T, 9 is a storage capacitor, and 10 is a reset MO8T. Figure 2 is a diagram showing an example of the drive pulse timing of the solid-state imaging device shown in Figure 1, with time on the horizontal axis and potential on the vertical axis.The potential on the vertical axis increases toward the top of the diagram. , for example, means that 5M03T becomes conductive when a pulse indicated by φ× is applied. The operation of the apparatus shown in FIG. 1 will be explained below using the timing chart of FIG.
まず、ホ1ヘダイオード1に蓄積した信号を読み出す前
にφt、φS、φRをパルス波形12.13.14に示
すように順次オン状態にして、水平走査期間(〜53μ
5)tI119に垂直信号線4に蓄積した暗電流などに
よる擬似信号をリセット用MO8TIOから取り出す。First, before reading out the signal accumulated in diode 1, φt, φS, and φR are sequentially turned on as shown in pulse waveform 12.13.14, and the horizontal scanning period (~53μ
5) At tI119, a pseudo signal caused by dark current accumulated in the vertical signal line 4 is taken out from the reset MO8TIO.
この時、蓄積容量9の一端に接続し、かつMO8T8お
よび10間を接続する基板表面領域(以下本明細書にお
いては蓄積容量9下と略称する。)の電位をVRにリセ
ットする。つぎに、φV、φt、φS、φXをパルス波
形15.16.17.18に示すように順次オン状態に
して、信号をCTDG内の蓄積ゲートへ移送する。ここ
で、φ1がオン状態になったとき、蓄積容量9下をソー
スとして、ここから電荷が垂直信号線4側へ流入するよ
うにVRを設定しておけば、垂直信号線4の電位を下げ
ることができ、転送MO8Tは十分な導通状態になる。At this time, the potential of the substrate surface region connected to one end of the storage capacitor 9 and between MO8T8 and 10 (hereinafter abbreviated as "under the storage capacitor 9" in this specification) is reset to VR. Next, φV, φt, φS, and φX are sequentially turned on as shown in pulse waveforms 15, 16, 17, and 18, and the signals are transferred to the storage gate in the CTDG. Here, if VR is set so that when φ1 is turned on, the charge flows from below the storage capacitor 9 to the vertical signal line 4 side, the potential of the vertical signal line 4 is lowered. The transfer MO8T becomes fully conductive.
このため、続いてφSがオン状態になって、蓄積容量9
下が逆に、ドレイン側になったとき、垂直信号線4側か
ら、さきに流入した電荷と信号電荷とを短かい時間に蓄
積容量9下側へ移すことができる。すなわち、一定量の
電荷を蓄積容量9下から垂直信号線4へ送り込み、これ
をホ1−ダイオード1側から送られてきた信号電荷とと
もに蓄積容量9側へ逆流させ、さらにCTDへ移すこと
により、短時間の内に大部分の信号電荷をCTDへ送り
込むことが可能になる。なお、以上の転送動作は水平帰
線期間tB(第2図の11)内にすべてが行なわれる。Therefore, φS is subsequently turned on, and the storage capacitor 9
Conversely, when the bottom side becomes the drain side, the charge and signal charge that previously flowed in from the vertical signal line 4 side can be transferred to the bottom side of the storage capacitor 9 in a short time. That is, by sending a certain amount of charge from below the storage capacitor 9 to the vertical signal line 4, making it flow back to the storage capacitor 9 side together with the signal charge sent from the H1-diode 1 side, and further transferring it to the CTD, It becomes possible to send most of the signal charges to the CTD within a short time. All of the above transfer operations are performed during the horizontal retrace period tB (11 in FIG. 2).
以上述べた従来の方式においては、ブルーミングや垂直
スミアは抑制することができるけれども、各列の蓄積容
量9のばらつきが各列毎の信号電荷のばらつきとなり、
この固体撮像装置で撮したモニタ画面には薄い縦縞の、
いわゆる固定パターン雑音が見られるという欠点があり
、この雑音の対策が必要であった。φRの閾電圧をV、
(φR)、φXの閾電圧をvt (φX)と書き、φR
Vt(φR)=φx−vt(φ×)であれば、固定パタ
ーンは発生しないが、閾電圧のばらつきによってこの条
件を満足することは不可能であり、そのため、蓄積容量
をCとすれば、電荷 Q = C(Vt (φR) −
Vt(φx) )の各列のばらつきが固定パターン雑音
の原因となる。In the conventional method described above, blooming and vertical smear can be suppressed, but variations in the storage capacitance 9 of each column lead to variations in signal charge for each column.
The monitor screen taken with this solid-state imaging device has thin vertical stripes.
It has the disadvantage that so-called fixed pattern noise can be seen, and countermeasures have been needed to deal with this noise. The threshold voltage of φR is V,
(φR), the threshold voltage of φX is written as vt (φX), and φR
If Vt(φR)=φx−vt(φ×), a fixed pattern will not occur, but it is impossible to satisfy this condition due to variations in threshold voltage.Therefore, if the storage capacitance is C, then Charge Q = C(Vt (φR) −
Variations in each column of Vt(φx) cause fixed pattern noise.
本発明の目的は、したがって、このような固定パターン
雑音が少ない、高画質を得ることを可能にする、冒頭に
述べた種類の固体撮像素子を提供することである。The object of the invention is therefore to provide a solid-state image sensor of the type mentioned at the beginning, which makes it possible to obtain high image quality with less fixed pattern noise.
」二記目的を達成するために、本発明による固体撮像素
子は、擬似信号電荷を吸い出す時も信号電荷をCTDに
読み込む時も、蓄積容量下の電位を5M08Tのゲート
・パルスの高レベル電圧と5M05Tの閾電圧の差に等
しい基準電位に設定することを要旨とする。In order to achieve the second object, the solid-state imaging device according to the present invention changes the potential under the storage capacitor to the high level voltage of the gate pulse of 5M08T both when sucking out pseudo signal charges and when reading signal charges into the CTD. The gist is to set the reference potential equal to the difference in threshold voltage of 5M05T.
第3図は本発明の一実施の態様による固体撮像素子の回
路図で、第4図は駆動パルスのタイミングの一例を示す
。第3図の1〜10および第4図のll、19はそれぞ
れ第1図の1〜10および第2図の11.19と同じも
のを意味する。第5図は第3図に示す装置の動作を説明
する回路模式図、第6図は第5図と対応させたポテンシ
ャル図である。第6図はnチャネル・1〜ランジスタの
場合を示し、縦軸に沿って下に向う方向が電子に対し高
ポテンシャルになる方向を意味し、矢印20は電荷の移
動方向を表わし、斜線部は高不純物濃度層の過剰電子を
示す。第3図および第5図においてMO8T5とMO8
T8を接続するノードには、MO8T5およびMO8T
8のソースあるいはドレインの役をする高不純物濃度層
が存在しているが、MO8T5とMO8TIOの間には
CTD6があり、5.6および10は3ゲ一トMO8T
のようになっぞいる。すなわち、M OS T5、CT
D6およびMO8T10は第8図に示すように3個のト
ランジスタの直列接続ではなく、第7図に断面図で示す
ようになっており、三つの素子はM OS ’rの反転
層によって電気的に接続さ肛ている。図中、φCPはC
TDの蓄積ゲー1−に印加される電圧を意味する。FIG. 3 is a circuit diagram of a solid-state imaging device according to an embodiment of the present invention, and FIG. 4 shows an example of timing of drive pulses. 1 to 10 in FIG. 3 and ll and 19 in FIG. 4 mean the same as 1 to 10 in FIG. 1 and 11.19 in FIG. 2, respectively. FIG. 5 is a schematic circuit diagram explaining the operation of the device shown in FIG. 3, and FIG. 6 is a potential diagram corresponding to FIG. 5. Figure 6 shows the case of an n-channel 1~ transistor, where the downward direction along the vertical axis means the direction of high potential for electrons, the arrow 20 represents the direction of charge movement, and the shaded area is Shows excess electrons in a high impurity concentration layer. In Figures 3 and 5, MO8T5 and MO8
MO8T5 and MO8T are connected to the node that connects T8.
There is a high impurity concentration layer that acts as the source or drain of 8, but there is a CTD6 between MO8T5 and MO8TIO, and 5.6 and 10 are 3-gate MO8T.
It looks like this. That is, M OS T5, CT
D6 and MO8T10 are not three transistors connected in series as shown in Fig. 8, but are shown in cross-section in Fig. 7, and the three elements are electrically connected by an inversion layer of MOS'r. The anus is connected. In the figure, φCP is C
It means the voltage applied to the storage gate 1- of the TD.
第4図から第6図までを用いて第3図に示す固体撮像装
置の動作をt工からtllまで時間の経過にしたがって
説明する。The operation of the solid-state imaging device shown in FIG. 3 will be explained in accordance with the passage of time from t to tll using FIGS. 4 to 6.
(1)t= し。(1) t = shi.
ホトダイオード1の蓄積容量CPに信号電荷Qsが蓄積
され、垂直信号線4の容量Cvにブルーミング、スミア
による擬似信号電荷Qsが蓄積されている。A signal charge Qs is accumulated in the storage capacitor CP of the photodiode 1, and a pseudo signal charge Qs due to blooming and smear is accumulated in the capacitor Cv of the vertical signal line 4.
(2) t = t2
φ、が高レベルとなり、蓄積容量9下の過剰電字が垂直
信号線に流入し、Qeと一緒になる。(2) t=t2φ becomes a high level, and the excess current under the storage capacitor 9 flows into the vertical signal line and becomes together with Qe.
(3) t = t3
φSが高レベルとなると、容量カップリング効果により
、蓄積容量9下の電位が高くなり、垂直(コ号線4に蓄
積されていた電荷が蓄積容量9下に流入する。この時、
垂直信号線の電位は転送用MO5T18のゲート・パル
スの高レベル電圧φtHと転送用M OS 1’の閾電
圧Vt(φ、)の差に等しい電位にクランプされる。(3) When t = t3 φS becomes a high level, the potential under the storage capacitor 9 becomes high due to the capacitive coupling effect, and the electric charge stored in the vertical (C) line 4 flows into the bottom of the storage capacitor 9. Time,
The potential of the vertical signal line is clamped to a potential equal to the difference between the high level voltage φtH of the gate pulse of the transfer MO5T18 and the threshold voltage Vt(φ,) of the transfer MOS 1'.
(4)t、=144
φt、φSが順次低レベルとなり、蓄積容量9にQBが
蓄積される。(4) t,=144 φt and φS sequentially become low level, and QB is stored in the storage capacitor 9.
(5)t=t5
φX、φRが高レベルとなり、QBはMO8T5、CT
D6、MO8TIOを介して外部VRに吸収される。こ
の時、蓄積容量9下の電位は5M08T5のゲート・パ
ルスの高レベル電圧φ×■と5M08T5の閾電圧V、
(φX)の差に等しい電位にクランプされる。一方φV
は高レベルとなり、信号電荷Qsが垂直信号線に移され
る。Cv > > Cpであるから、Qsは殆んど垂直
信号線の容量Cvに蓄積される。(5) t=t5 φX, φR become high level, QB is MO8T5, CT
It is absorbed into the external VR via D6 and MO8TIO. At this time, the potential under the storage capacitor 9 is the high level voltage φ×■ of the gate pulse of 5M08T5 and the threshold voltage V of 5M08T5,
It is clamped to a potential equal to the difference between (φX). On the other hand, φV
becomes high level, and the signal charge Qs is transferred to the vertical signal line. Since Cv>>Cp, most of Qs is accumulated in the capacitance Cv of the vertical signal line.
(6)t=tG
φX、φVが高レベルとなり、Qsは垂直信号線に移さ
れた状態となる。(6) t=tG φX and φV are at high level, and Qs is moved to the vertical signal line.
(7)t=t7〜t。(7) t=t7-t.
1=12〜t4におけるのと同様の動作をし、Qsは蓄
積容量9に転送された状態となる。The same operation as in 1=12 to t4 is performed, and Qs is transferred to the storage capacitor 9.
(8)t=t、。(8) t=t.
φXが高レベルとなり、QsがCTD6に転送される。φX becomes high level and Qs is transferred to CTD6.
(9)t=t□1
φ×が低レベルとなり、QsがCTD内に読み込まれた
状態となる。その後CTDを駆動する。(9) t=t□1 φ× becomes low level, and Qs is read into CTD. After that, drive the CTD.
QsはCT D内を転送され、前置増幅器7を介して外
部に読み出される。Qs is transferred within the CT D and read out via the preamplifier 7.
以上の動作において、短かい時間内に電荷を垂直信号線
容量CVから蓄積容量9下に転送するには、つぎの条件
が満足されればよい。In the above operation, in order to transfer charges from the vertical signal line capacitance CV to below the storage capacitor 9 within a short time, the following conditions need to be satisfied.
φto Vt(φ、)〉φXH−Vt(φ×)以上のよ
うに、本発明によれば、擬似信号電荷を外部に吸い出す
時も、信号電荷をCTDに読み込む時も、蓄積容量9下
の電位を同電位(φ×1(−Vゎ(φx))とするため
、蓄積容量9のばらつきによる固定パターン雑音を除去
することができる。φto Vt(φ,)〉φXH−Vt(φ×) As described above, according to the present invention, the potential below the storage capacitor 9 is Since they are set to the same potential (φ×1 (−Vゎ(φx)), fixed pattern noise caused by variations in the storage capacitance 9 can be removed.
第9図は第3図に示す装置を駆動するための他の一つの
駆動パルス・タイミングを示す。CTD6によって信号
を外部に読出し中、すなわち水平走査期間to中、φt
およびφSが高レベルとなっており、垂直信号線4に混
入する擬似信号を蓄積容量9に転送している。そのため
、垂直信号線4から蓄積容量9への読出し時間、すなわ
ち水平帰線期間tB中の信号読出し時間を長くとれる利
点がある。FIG. 9 shows another drive pulse timing for driving the device shown in FIG. While reading the signal to the outside by CTD6, that is, during the horizontal scanning period to, φt
and φS are at high level, and the pseudo signal mixed into the vertical signal line 4 is transferred to the storage capacitor 9. Therefore, there is an advantage that the reading time from the vertical signal line 4 to the storage capacitor 9, that is, the signal reading time during the horizontal retrace period tB can be increased.
第1O図は本発明の第2の実施の態様による固体撮像装
置の回路図で、蓄積容量9下の電位を。FIG. 1O is a circuit diagram of a solid-state imaging device according to a second embodiment of the present invention, and shows the potential below the storage capacitor 9.
φx211をφx2の高レベル、Vt(φ×2)をφx
2の閾電圧としてφX211−Vt(φX2)なる基準
電位に設定するためのMO8’r21が備えられている
。MO8T21.10.5MO8,T5およびCTD6
の間の接続は、第7図で説明したように、ゲートを介し
て行なわれる。第11図は第10図に示す装置の駆動パ
ルス・タイミングを示す。φx211 is the high level of φx2, Vt (φ×2) is φx
MO8'r21 is provided for setting a reference potential of φX211-Vt (φX2) as the threshold voltage of φX2. MO8T21.10.5MO8, T5 and CTD6
The connection between them is made through the gate as explained in FIG. FIG. 11 shows the drive pulse timing for the device shown in FIG.
第12図は第10図に示す装置を駆動するための他の一
つの駆動パルス・タイミングを示す。水平走査期間to
中に擬似信号が蓄積容量9に転送されており、その効果
は第9図について述べたものと同じである。FIG. 12 shows another drive pulse timing for driving the device shown in FIG. Horizontal scanning period to
Inside, a pseudo signal is transferred to the storage capacitor 9, the effect of which is the same as that described with respect to FIG.
第13図は本発明の第3の実施の態様による固体撮像装
置の回路図で、2本の垂直ゲーl〜線に対応する2行分
の信号を」二下のCTDに各々、1行分の信号を振り分
けることによって2行分の信号を同時に外部に読み出す
ことができる。ホ1−ダイオ−1〜・アレーの上下に第
3図に示す結合部、読出し部を配置し、水平帰線期間の
前半にA側のCTDに」。行分の信号を読み込み、後半
にB側のCTI〕に次の行の信号を読み込む。その後、
水平走査期間にA、B側のCT Dを同時に駆動する事
により、2行の信号を外部に同時に読出すことができる
。FIG. 13 is a circuit diagram of a solid-state imaging device according to a third embodiment of the present invention, in which signals for two lines corresponding to two vertical gate lines are sent to the lower two CTDs for one line each. By distributing the signals, signals for two rows can be read out to the outside at the same time. The coupling section and readout section shown in Fig. 3 are arranged above and below the array, and are connected to the CTD on the A side during the first half of the horizontal retrace period. The signals for the rows are read, and in the second half, the signals for the next row are read into the CTI on the B side. after that,
By driving the A and B side CTDs simultaneously during the horizontal scanning period, the signals of two rows can be read out to the outside at the same time.
第14図は本発明の第4の実施の態様による固体撮像装
置の回路図で、ホトダイオード・アレーの上下に第10
図に示す結合部、読出し部が配置されており、この実施
の態様によれば第13図の場合と同様に2行分の信号を
外部に読出す事ができる。FIG. 14 is a circuit diagram of a solid-state imaging device according to a fourth embodiment of the present invention.
The coupling section and readout section shown in the figure are arranged, and according to this embodiment, signals for two rows can be read out to the outside as in the case of FIG. 13.
以上、本発明をnチャネル素子の場合について説明した
けれども、本発明がPチャネル素子にも同様に適用でき
ることは勿論である。また、CT■つはバルク型の電荷
結合素子(c c D)でも表面型のCODやバケツ1
〜・ブリゲート・デバイス(B B D)でもよく、電
極構造や材料などには、本発明は限定さibない。Although the present invention has been described above in the case of an n-channel device, it goes without saying that the present invention can be similarly applied to a p-channel device. In addition, CT■ is a bulk type charge-coupled device (c c D), a surface type COD, and a bucket 1.
It may be a brigade device (BBD), and the present invention is not limited to the electrode structure or material.
上記のように本発明による固体撮像素子は、半導体基板
上に形成された、受光部にホトダイオードとスイッチ用
MOSトランジスタとからなる画素をマトリックス状に
並べたセンサを配し、読出し用電荷移送素子を有し、セ
ンサ部の信号出力線と電荷移送素子入力端子の間に、水
平スイッチ用MO8I−ランジスタ、転送用MOSトラ
ンジスタ。As described above, the solid-state image sensor according to the present invention includes a sensor formed on a semiconductor substrate in which pixels each including a photodiode and a switching MOS transistor are arranged in a matrix in a light receiving section, and a readout charge transfer element. A horizontal switch MO8I-transistor and a transfer MOS transistor are provided between the signal output line of the sensor section and the charge transfer element input terminal.
および水平スイッチ用MOSトランジスタと転送11J
MO8+−ランジスタの結合点に接続された蓄積容量を
有する固体撮像素子において、擬似信号電荷を吸い出す
時も信号電荷を電荷移送索子に読み込む時も蓄積容量を
形成している基板表面の電位を水平スイッチ用MO3I
−ランジスタのゲート・パルスの高レベル電圧と水平ス
イッチ用MO81〜ランジスタの閾電圧の差に等しい基
準電位に設定することにより、固定パターン雑音が少な
い、高画質を得ることを可能にする固体撮像装置を実現
することができる。and horizontal switch MOS transistor and transfer 11J
In a solid-state image sensor that has a storage capacitor connected to the connection point of the MO8+- transistor, the potential on the surface of the substrate forming the storage capacitor is kept horizontal both when sucking out pseudo signal charges and when reading signal charges into the charge transfer wire. MO3I for switch
- A solid-state imaging device that makes it possible to obtain high image quality with less fixed pattern noise by setting a reference potential equal to the difference between the high-level voltage of the gate pulse of the transistor and the threshold voltage of the MO81 for horizontal switch ~ transistor. can be realized.
第1図は従来の固体撮像装置の構成を示す回路図、第2
図は第1図に示す装置の駆動パルスのタイミングを示す
図、第3図、第10図、第13図および第14図は本発
明の四つの異なる実施の態様による固体撮像装置の構成
を示す回路図、第4図および第9図は第3図に示す装置
を駆動するための2種類の駆動パルスのタイミングを示
す図、第5図は第3図に示す装置の動作を説明するため
の回路模式図、第6図は第5図と対応させたポテンシャ
ル図、第7図は本発明による装置の中で使用される3ゲ
ート・トランジスタを説明するための断面図、第8図は
通常の3ゲート・トランジスタの断面図、第11図およ
び第12図は第10図に示す装置を駆動するための2種
類の駆動パルスのタイミングを示す図である。
]、・・・ポ1〜ダイオード
2・・・垂直スイッチ用MOSトランジスタ3・・スキ
ャナ 4・・垂直信号線
5・・水平スイッチ用MO3I−ランジスタロ・・・水
平読出し用電荷移送装置
7・・前置増幅器
8・・・転送用MOSトランジスタ
9・・・蓄積容量
10・・・リセット用MO81〜ランジスタ11・・水
平帰線期間 12〜18 パルス波形19・水平走査期
間
20・・・電子の移動方向を示す矢印
21・・・MOSトランジスタ
十 1 (川
千2図
第4図
9 18 9
9 匂 慴
?
W彊
Qつ
礪・
ン量戸 8 121
φ、 φcp ψR
十〇 図
第10図
〕(戸 11 r4 シ(戸 12 r1杢−1L−一
−キ句 r# fB i
十14図Figure 1 is a circuit diagram showing the configuration of a conventional solid-state imaging device;
The figure shows the timing of drive pulses of the device shown in FIG. 1, and FIGS. 3, 10, 13, and 14 show the configurations of solid-state imaging devices according to four different embodiments of the present invention. The circuit diagrams, FIGS. 4 and 9 are diagrams showing the timing of two types of drive pulses for driving the device shown in FIG. 3, and FIG. 5 is a diagram for explaining the operation of the device shown in FIG. 3. FIG. 6 is a potential diagram corresponding to FIG. 5, FIG. 7 is a cross-sectional view for explaining the three-gate transistor used in the device according to the invention, and FIG. 8 is a typical circuit diagram. A cross-sectional view of a three-gate transistor, FIGS. 11 and 12, illustrate the timing of two types of drive pulses for driving the device shown in FIG. 10. ],...Po1 to diode 2...Vertical switch MOS transistor 3...Scanner 4...Vertical signal line 5...Horizontal switch MO3I-Landistaro...Horizontal readout charge transfer device 7...Front Positional amplifier 8...Transfer MOS transistor 9...Storage capacitor 10...Reset MO81 - transistor 11...Horizontal retrace period 12-18 Pulse waveform 19/Horizontal scanning period 20...Electron movement direction Arrow 21 showing MOS transistor 1 (Fig. 4) 11 r4 し(door 12 r1 杢-1L-1-ki phrase r# fB i 114th figure
Claims (1)
スイッチ用MO8+−ランジスタとから成る画素をマト
リックス状に並べたセンサを配し、読出し用電荷移送素
子を有し、センサ部の信号出力線と電荷移送素子入力端
子の間に、水平スイッチ用MO8+−ランジスタ、転送
用MO5+−ランジスタ、および水平スイッチ用MO3
I−ランジスタと転送用MO8+−ランジスタの結合点
に接続された蓄積容量を有する固体撮像素子において、
擬似信号電荷を吸い出す時も信号電荷を電荷移送素子に
読み込む時も蓄積容量を形成している基板表面の電位を
水平スイッチ用MOSトランジスタのゲート・パルスの
高レベル電圧と水平スイッチ用MO81〜ランジスタの
閾電圧、の差に等しい基準電位に設定することを特徴と
する固体撮像素子。A sensor is formed on a semiconductor substrate, and has a sensor in which pixels consisting of a photodiode and an MO8+- transistor for switching are arranged in a matrix in a light receiving part, and has a charge transfer element for readout, and a signal output line of the sensor part and a charge transfer element. Between the transfer element input terminals, MO8+- transistor for horizontal switch, MO5+- transistor for transfer, and MO3 for horizontal switch.
In a solid-state image sensor having a storage capacitor connected to the connection point of the I-transistor and the transfer MO8+- transistor,
Both when sucking out the pseudo signal charge and when reading the signal charge into the charge transfer element, the potential on the surface of the substrate forming the storage capacitor is connected to the high level voltage of the gate pulse of the horizontal switch MOS transistor and the horizontal switch MO81 to transistor. A solid-state imaging device characterized in that a reference potential is set equal to a difference between threshold voltages.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP59135290A JPS6041375A (en) | 1984-07-02 | 1984-07-02 | Solid-state image pickup element |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP59135290A JPS6041375A (en) | 1984-07-02 | 1984-07-02 | Solid-state image pickup element |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6041375A true JPS6041375A (en) | 1985-03-05 |
Family
ID=15148238
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP59135290A Pending JPS6041375A (en) | 1984-07-02 | 1984-07-02 | Solid-state image pickup element |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6041375A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS642354A (en) * | 1987-04-10 | 1989-01-06 | Texas Instr Inc <Ti> | Transistor image sensor array and method for detecting voltage signal |
-
1984
- 1984-07-02 JP JP59135290A patent/JPS6041375A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS642354A (en) * | 1987-04-10 | 1989-01-06 | Texas Instr Inc <Ti> | Transistor image sensor array and method for detecting voltage signal |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US7362366B2 (en) | High-speed solid-state imaging device capable of suppressing image noise | |
US6747699B2 (en) | Solid state image pickup apparatus | |
US5019702A (en) | Photoelectric transducer apparatus having a plurality of transducer elements and a plurality of capacitor elements | |
JPS6161586B2 (en) | ||
US4366503A (en) | Solid state image pick-up device and its charge transfer method | |
US4301477A (en) | Solid-state imaging device | |
JP2003224777A (en) | Amplification type solid-state imaging apparatus | |
US4443818A (en) | Solid-state imaging device | |
JPH0754973B2 (en) | Driving method for solid-state imaging device | |
US5796432A (en) | Method of and apparatus for solid state imaging device | |
US4621291A (en) | Solid-state imaging device | |
JPS6041375A (en) | Solid-state image pickup element | |
JP2000152090A (en) | Solid-state image pickup device | |
JPS58157262A (en) | Solid-state image pickup device | |
KR850000366B1 (en) | Solid-state device | |
JP2928562B2 (en) | Solid-state imaging device | |
JPH05227486A (en) | Solid state image pickup device | |
JPS60219876A (en) | Solid-state image pickup device | |
JPS63308373A (en) | Charge transfer device | |
JPH09163234A (en) | Drive method for amplifier type solid-state image pickup element | |
JPH07114469B2 (en) | Driving method for solid-state imaging device | |
JPS628670A (en) | Solid state image pickup device | |
JPH08214177A (en) | Photoelectric converter | |
JPH08172580A (en) | Solid-state image pickup device | |
JPS60198773A (en) | Solid-state image pickup device |