JPS6041375A - Solid-state image pickup element - Google Patents

Abstract

PURPOSE:To eliminate fixed pattern noise due to the variance of storage capacity by setting the potential of the storage capacity to a specific reference potential when not only the electric charge of a false signal is pulled to the external but also the electric charge of the signal is read into a charge transfer element. CONSTITUTION:A signal charge Qs is stored in the storage capacity of a photodiode 1, and a false signal charge QB is stored in the capacity CV of a vertical signal line 4. Excess electrons under the capacity 9 are flowed to the signal line 4 and are joined with the charge QB. The charge stored in the signal line 4 is flowed under the capacity 9. The charge QB is absorbed by an external VR. At this time, the potential under the capacity 9 is clipped with a potential equal to a difference between a high-level voltage phixH of the gate pulse of a horizontal switching MOSFET5 and a threshold voltage Vt(phix) of the FET5. Meanwhile, the charge Qs is transferred to the signal line 4 and is transferred next to the capacity 9. Next, the charge Qs is transferred to a horizontal reading charge transfer device 6 and is read out to the external. Thus, the potential under the capacity is set to the same potential when not only the charge QB is pulled out to the external VR but also the charge Qs is read in.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention provides a photodiode and a switching MOS transistor (hereinafter abbreviated as MO8T in this specification) formed on a semiconductor substrate.

) is arranged in a matrix, and a readout charge transfer element (hereinafter referred to as C
T D (Charge Transfer Devi
ce). ), and an MO8T for horizontal switch (hereinafter abbreviated as 5M08T in this specification) and an M for transfer between the signal output line of the sensor section and the CTD input terminal.
O8T, horizontal switch MO8'F and transfer MO
The present invention relates to a solid-state image sensor having a storage capacitor connected to an 8T coupling point.

[Background of the invention]

Figure 1 shows the configuration of a conventional solid-state imaging device (Jet No. 54
-157030). In the figure, ■ is a photodiode consisting of a p-n junction, 2 is a vertical switch MO3T (hereinafter abbreviated as VMO8T in this specification), and 3 is this M
A scanner that sequentially switches O8T with clock φV, 4 is a vertical signal line, 5 is MO8T for horizontal switch (
Hereinafter, it will be abbreviated as 5M08T in this specification. ), 6
7 is a preamplifier connected to the CTD 6, 8 is a transfer MO8T, 9 is a storage capacitor, and 10 is a reset MO8T. Figure 2 is a diagram showing an example of the drive pulse timing of the solid-state imaging device shown in Figure 1, with time on the horizontal axis and potential on the vertical axis.The potential on the vertical axis increases toward the top of the diagram. , for example, means that 5M03T becomes conductive when a pulse indicated by φ× is applied. The operation of the apparatus shown in FIG. 1 will be explained below using the timing chart of FIG.

First, before reading out the signal accumulated in diode 1, φt, φS, and φR are sequentially turned on as shown in pulse waveform 12.13.14, and the horizontal scanning period (~53μ
5) At tI119, a pseudo signal caused by dark current accumulated in the vertical signal line 4 is taken out from the reset MO8TIO.

At this time, the potential of the substrate surface region connected to one end of the storage capacitor 9 and between MO8T8 and 10 (hereinafter abbreviated as "under the storage capacitor 9" in this specification) is reset to VR. Next, φV, φt, φS, and φX are sequentially turned on as shown in pulse waveforms 15, 16, 17, and 18, and the signals are transferred to the storage gate in the CTDG. Here, if VR is set so that when φ1 is turned on, the charge flows from below the storage capacitor 9 to the vertical signal line 4 side, the potential of the vertical signal line 4 is lowered. The transfer MO8T becomes fully conductive.

Therefore, φS is subsequently turned on, and the storage capacitor 9
Conversely, when the bottom side becomes the drain side, the charge and signal charge that previously flowed in from the vertical signal line 4 side can be transferred to the bottom side of the storage capacitor 9 in a short time. That is, by sending a certain amount of charge from below the storage capacitor 9 to the vertical signal line 4, making it flow back to the storage capacitor 9 side together with the signal charge sent from the H1-diode 1 side, and further transferring it to the CTD, It becomes possible to send most of the signal charges to the CTD within a short time. All of the above transfer operations are performed during the horizontal retrace period tB (11 in FIG. 2).

In the conventional method described above, blooming and vertical smear can be suppressed, but variations in the storage capacitance 9 of each column lead to variations in signal charge for each column.
The monitor screen taken with this solid-state imaging device has thin vertical stripes.
It has the disadvantage that so-called fixed pattern noise can be seen, and countermeasures have been needed to deal with this noise. The threshold voltage of φR is V,
(φR), the threshold voltage of φX is written as vt (φX), and φR
If Vt(φR)=φx−vt(φ×), a fixed pattern will not occur, but it is impossible to satisfy this condition due to variations in threshold voltage.Therefore, if the storage capacitance is C, then Charge Q = C(Vt (φR) −
Variations in each column of Vt(φx) cause fixed pattern noise.

[Purpose of the invention]

The object of the invention is therefore to provide a solid-state image sensor of the type mentioned at the beginning, which makes it possible to obtain high image quality with less fixed pattern noise.

[Summary of the invention]

In order to achieve the second object, the solid-state imaging device according to the present invention changes the potential under the storage capacitor to the high level voltage of the gate pulse of 5M08T both when sucking out pseudo signal charges and when reading signal charges into the CTD. The gist is to set the reference potential equal to the difference in threshold voltage of 5M05T.

[Embodiments of the invention]

FIG. 3 is a circuit diagram of a solid-state imaging device according to an embodiment of the present invention, and FIG. 4 shows an example of timing of drive pulses. 1 to 10 in FIG. 3 and ll and 19 in FIG. 4 mean the same as 1 to 10 in FIG. 1 and 11.19 in FIG. 2, respectively. FIG. 5 is a schematic circuit diagram explaining the operation of the device shown in FIG. 3, and FIG. 6 is a potential diagram corresponding to FIG. 5. Figure 6 shows the case of an n-channel 1~ transistor, where the downward direction along the vertical axis means the direction of high potential for electrons, the arrow 20 represents the direction of charge movement, and the shaded area is Shows excess electrons in a high impurity concentration layer. In Figures 3 and 5, MO8T5 and MO8
MO8T5 and MO8T are connected to the node that connects T8.
There is a high impurity concentration layer that acts as the source or drain of 8, but there is a CTD6 between MO8T5 and MO8TIO, and 5.6 and 10 are 3-gate MO8T.
It looks like this. That is, M OS T5, CT
D6 and MO8T10 are not three transistors connected in series as shown in Fig. 8, but are shown in cross-section in Fig. 7, and the three elements are electrically connected by an inversion layer of MOS'r. The anus is connected. In the figure, φCP is C
It means the voltage applied to the storage gate 1- of the TD.

The operation of the solid-state imaging device shown in FIG. 3 will be explained in accordance with the passage of time from t to tll using FIGS. 4 to 6.

(1) t = shi.

A signal charge Qs is accumulated in the storage capacitor CP of the photodiode 1, and a pseudo signal charge Qs due to blooming and smear is accumulated in the capacitor Cv of the vertical signal line 4.

(2) t=t2φ becomes a high level, and the excess current under the storage capacitor 9 flows into the vertical signal line and becomes together with Qe.

(3) When t = t3 φS becomes a high level, the potential under the storage capacitor 9 becomes high due to the capacitive coupling effect, and the electric charge stored in the vertical (C) line 4 flows into the bottom of the storage capacitor 9. Time,
The potential of the vertical signal line is clamped to a potential equal to the difference between the high level voltage φtH of the gate pulse of the transfer MO5T18 and the threshold voltage Vt(φ,) of the transfer MOS 1'.

(4) t,=144 φt and φS sequentially become low level, and QB is stored in the storage capacitor 9.

(5) t=t5 φX, φR become high level, QB is MO8T5, CT
It is absorbed into the external VR via D6 and MO8TIO. At this time, the potential under the storage capacitor 9 is the high level voltage φ×■ of the gate pulse of 5M08T5 and the threshold voltage V of 5M08T5,
It is clamped to a potential equal to the difference between (φX). On the other hand, φV
becomes high level, and the signal charge Qs is transferred to the vertical signal line. Since Cv>>Cp, most of Qs is accumulated in the capacitance Cv of the vertical signal line.

(6) t=tG φX and φV are at high level, and Qs is moved to the vertical signal line.

(7) t=t7-t.

The same operation as in 1=12 to t4 is performed, and Qs is transferred to the storage capacitor 9.

(8) t=t.

φX becomes high level and Qs is transferred to CTD6.

(9) t=t□1 φ× becomes low level, and Qs is read into CTD. After that, drive the CTD.

Qs is transferred within the CT D and read out via the preamplifier 7.

In the above operation, in order to transfer charges from the vertical signal line capacitance CV to below the storage capacitor 9 within a short time, the following conditions need to be satisfied.

φto Vt(φ,)〉φXH−Vt(φ×) As described above, according to the present invention, the potential below the storage capacitor 9 is Since they are set to the same potential (φ×1 (−Vゎ(φx)), fixed pattern noise caused by variations in the storage capacitance 9 can be removed.

FIG. 9 shows another drive pulse timing for driving the device shown in FIG. While reading the signal to the outside by CTD6, that is, during the horizontal scanning period to, φt
and φS are at high level, and the pseudo signal mixed into the vertical signal line 4 is transferred to the storage capacitor 9. Therefore, there is an advantage that the reading time from the vertical signal line 4 to the storage capacitor 9, that is, the signal reading time during the horizontal retrace period tB can be increased.

FIG. 1O is a circuit diagram of a solid-state imaging device according to a second embodiment of the present invention, and shows the potential below the storage capacitor 9.

φx211 is the high level of φx2, Vt (φ×2) is φx
MO8'r21 is provided for setting a reference potential of φX211-Vt (φX2) as the threshold voltage of φX2. MO8T21.10.5MO8, T5 and CTD6
The connection between them is made through the gate as explained in FIG. FIG. 11 shows the drive pulse timing for the device shown in FIG.

FIG. 12 shows another drive pulse timing for driving the device shown in FIG. Horizontal scanning period to
Inside, a pseudo signal is transferred to the storage capacitor 9, the effect of which is the same as that described with respect to FIG.

FIG. 13 is a circuit diagram of a solid-state imaging device according to a third embodiment of the present invention, in which signals for two lines corresponding to two vertical gate lines are sent to the lower two CTDs for one line each. By distributing the signals, signals for two rows can be read out to the outside at the same time. The coupling section and readout section shown in Fig. 3 are arranged above and below the array, and are connected to the CTD on the A side during the first half of the horizontal retrace period. The signals for the rows are read, and in the second half, the signals for the next row are read into the CTI on the B side. after that,
By driving the A and B side CTDs simultaneously during the horizontal scanning period, the signals of two rows can be read out to the outside at the same time.

FIG. 14 is a circuit diagram of a solid-state imaging device according to a fourth embodiment of the present invention.
The coupling section and readout section shown in the figure are arranged, and according to this embodiment, signals for two rows can be read out to the outside as in the case of FIG. 13.

Although the present invention has been described above in the case of an n-channel device, it goes without saying that the present invention can be similarly applied to a p-channel device. In addition, CT■ is a bulk type charge-coupled device (c c D), a surface type COD, and a bucket 1.
It may be a brigade device (BBD), and the present invention is not limited to the electrode structure or material.

〔Effect of the invention〕

As described above, the solid-state image sensor according to the present invention includes a sensor formed on a semiconductor substrate in which pixels each including a photodiode and a switching MOS transistor are arranged in a matrix in a light receiving section, and a readout charge transfer element. A horizontal switch MO8I-transistor and a transfer MOS transistor are provided between the signal output line of the sensor section and the charge transfer element input terminal.

and horizontal switch MOS transistor and transfer 11J
In a solid-state image sensor that has a storage capacitor connected to the connection point of the MO8+- transistor, the potential on the surface of the substrate forming the storage capacitor is kept horizontal both when sucking out pseudo signal charges and when reading signal charges into the charge transfer wire. MO3I for switch
- A solid-state imaging device that makes it possible to obtain high image quality with less fixed pattern noise by setting a reference potential equal to the difference between the high-level voltage of the gate pulse of the transistor and the threshold voltage of the MO81 for horizontal switch ~ transistor. can be realized.

[Brief explanation of the drawing]

Figure 1 is a circuit diagram showing the configuration of a conventional solid-state imaging device;
The figure shows the timing of drive pulses of the device shown in FIG. 1, and FIGS. 3, 10, 13, and 14 show the configurations of solid-state imaging devices according to four different embodiments of the present invention. The circuit diagrams, FIGS. 4 and 9 are diagrams showing the timing of two types of drive pulses for driving the device shown in FIG. 3, and FIG. 5 is a diagram for explaining the operation of the device shown in FIG. 3. FIG. 6 is a potential diagram corresponding to FIG. 5, FIG. 7 is a cross-sectional view for explaining the three-gate transistor used in the device according to the invention, and FIG. 8 is a typical circuit diagram. A cross-sectional view of a three-gate transistor, FIGS. 11 and 12, illustrate the timing of two types of drive pulses for driving the device shown in FIG. 10. ],...Po1 to diode 2...Vertical switch MOS transistor 3...Scanner 4...Vertical signal line 5...Horizontal switch MO3I-Landistaro...Horizontal readout charge transfer device 7...Front Positional amplifier 8...Transfer MOS transistor 9...Storage capacitor 10...Reset MO81 - transistor 11...Horizontal retrace period 12-18 Pulse waveform 19/Horizontal scanning period 20...Electron movement direction Arrow 21 showing MOS transistor 1 (Fig. 4) 11 r4 し(door 12 r1 杢-1L-1-ki phrase r# fB i 114th figure

Claims (1)

[Claims] A sensor is formed on a semiconductor substrate, and has a sensor in which pixels consisting of a photodiode and an MO8+- transistor for switching are arranged in a matrix in a light receiving part, and has a charge transfer element for readout, and a signal output line of the sensor part and a charge transfer element. Between the transfer element input terminals, MO8+- transistor for horizontal switch, MO5+- transistor for transfer, and MO3 for horizontal switch.
In a solid-state image sensor having a storage capacitor connected to the connection point of the I-transistor and the transfer MO8+- transistor,
Both when sucking out the pseudo signal charge and when reading the signal charge into the charge transfer element, the potential on the surface of the substrate forming the storage capacitor is connected to the high level voltage of the gate pulse of the horizontal switch MOS transistor and the horizontal switch MO81 to transistor. A solid-state imaging device characterized in that a reference potential is set equal to a difference between threshold voltages.