JPH06217205A - Solid state image pickup device - Google Patents

Abstract

PURPOSE:To prevent an operation defective state accompanying an increase in output rate, to remove the high-frequency component of a high-frequency random noise generated by pixels, and to improve the S/N of an image pickup signal by reading a signal out of a pixel at a slow speed even by a high-vision system. CONSTITUTION:The solid state image pickup element in which an image pickup area 2 where many pixels 1 are arrayed in matrix, a vertical scanning circuit 3 for selecting pixels 1, 1..., row by row, and a horizontal selecting circuit 4 for selecting the pixels 1, 2..., column by column, are incorporated is constituted by connecting CDS circuits 5 as many as horizontal pixels to a video line L. Then the CDS circuits 5 each consist of a clamp circuit which holds the signal level of pixels 1, 2... of an (n)th row selected by the vertical scanning circuit 3 at a specific potential VCL and a sample and hold circuit which samples and holds the level of the pixels 1, 2... of the selected (n)th row after resetting.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state image sensor,
In particular, the present invention relates to an internal amplification type solid-state imaging device in which optical signal charges are amplified for each pixel.

[0002]

2. Description of the Related Art Recently, in response to a demand for higher resolution of a solid-state image pickup device, research and development of an internal amplification type solid-state image pickup device for amplifying an optical signal charge for each pixel has been advanced.

The main components of the internal amplification type solid-state image pickup device are a static induction transistor (SIT) and an amplification type MI.
S imager (AMI), charge modulation device (CMD)
Various image pickup device structures such as are known.

In these internal amplification type solid-state image pickup devices, the output stage thereof has an FPN (fixed pattern noise).
A correlated double sampling circuit (hereinafter simply referred to as a CDS circuit) for the purpose of suppressing 1 / f noise is connected.

FIG. 7 shows a C as an internal amplification type solid-state image pickup device.
A conventional configuration using an MD as an example is shown. In this solid-state image sensor, one transistor / pixel CMD (pixel) 1
Imaging area 10 configured by arranging 01 in a matrix
2, and a vertical scanning circuit 103 for selecting pixels 101, 101 ...
, And a horizontal scanning circuit 104 for selecting the pixels 101, 101 ...

Then, the pixels 101, 101 ...
The vertical signal lines VS1, VS2, ... VSn, which are common with respect to each other and are arranged in the column direction, are connected to the sources of the pixels (CMD) 101, 101. Of the horizontal selection lines VL which are common to the pixels 101, 101 ...
The gates of the pixels (CMD) 101, 101 ... Of the corresponding rows are connected to 1, VL2 ... VLn. Further, the drains of the respective pixels 101, 101 ... Are made common to each other, and the structure is such that the power supply voltage Vdd is applied.

The vertical scanning circuit 103 has, for example, a shift register which outputs a binary logical output, and a ternary voltage output (Va, Vb, V) based on the logical output and clock timing.
It is composed of a level mix circuit for generating c).

Further, each vertical signal line VS1, VS2 ...
VSn is connected to the video line L leading to the output terminal φ via the switching transistor Tr, and the column selection lines HL1, HL2, ... HLn corresponding to the number of horizontal pixels extending from the horizontal scanning circuit 104 respectively correspond. It is connected to the gate of the switching transistor Tr.

In this conventional solid-state image pickup device, each pixel 101, 101 is provided on the output side of the video line L.
A load resistance RL for converting a signal current associated with the optical signal charge into a voltage signal is connected, and one CDS circuit 105 is connected between the load resistance RL and the output terminal φ.

The operation of this solid-state image pickup device will be described with reference to the timing chart of FIG. 8. First, at the time of charge accumulation (exposure), each pixel (CM
D) Low voltage V that cuts off 101, 101 ...
a is output and applied to the gates of the pixels 101, 101. When light-generated holes are accumulated in the gate portion of each pixel 101, 101 ... With the incidence of light from the subject, the light-generating holes are accumulated in the surface potential of each pixel 101, 101. It rises according to the holes.

In the prior art, during the effective horizontal scanning period Ha after the horizontal blanking period HB, for example, the pixels 101, 101 ... In the first row from the vertical scanning circuit 103.
Is supplied with a read voltage Vb higher than the above voltage Va. Thereby, the pixels 101, 101 in the first row
... has been selected.

Further, in the effective horizontal scanning period Ha, the horizontal scanning circuit 104 sequentially selects pulses P1 and P2.
By outputting ..., the corresponding switching transistors Tr, Tr, ... are sequentially turned on. As a result, the row selected by the vertical scanning circuit 103,
The pixels 101 in the columns in which the switching transistors Tr are turned on are sequentially selected, and the signals of the selected pixels 101 are output via the CDS circuit 105 to the output terminal φ.
Taken out.

Actually, during the output period of one selection pulse from the horizontal scanning circuit 103, signal reading, pixel reset, and pixel level after reset (black level)
Is read. That is, the read voltage Vb is applied to the gates of the pixels 101, 101 ... Of one row selected by the vertical scanning circuit 103, and one pixel is selected by the selection pulse from the horizontal scanning circuit 104. 1
When the source of 01 and the video line L on the output side are connected, a signal current corresponding to the gate potential in the pixel 101 and the surface potential accompanying the photogenerated holes accumulated in the pixel flows in the video line L. .

This signal current flows through the load resistance RL, and the resulting voltage change (signal voltage) V (S) is the CDS circuit 10.
Input to 5. Then, from the vertical scanning circuit 103 to the selected one row of pixels 101, 101 ...
A reset voltage Vc higher than the read voltage Vb is supplied. At this time, only one pixel 101 selected by the horizontal scanning circuit 104 is reset. That is, the photo-generated holes accumulated in the pixel 101 are swept away to the substrate side.

Then, again from the vertical scanning circuit 103, to the pixels 101, 101 ... Of the selected one row,
The voltage Vb for reading is supplied. At this time, since the photogenerated holes do not exist in the selected one pixel 101, the surface potential thereof changes depending on the potential applied to the gate, which is lower than the surface potential at the time of reading. Indicates. Therefore, during this period, the CDS circuit 105
The voltage level input to is higher than the signal voltage level V (S) and indicates a level dependent only on the characteristics of the CMD forming the pixel 101, that is, the black level V (B) of the pixel 101. Become. And this black level V
The signal amount V of the pixel can be obtained from (B) and the signal voltage level V (S).

By performing this series of operations for each pixel 101, an image pickup signal can be obtained in time series from the output terminal φ.

Further, conventionally, an internal amplification type solid-state image pickup device of an all-pixel readout system compatible with interlaced scanning has been proposed. As shown in FIG. 9, in this solid-state image pickup device, two CDS circuits 105A and 105B are connected to the vertical signal lines VS1, VS2, ... VSn, respectively, and the outputs thereof are respectively switching transistors Tr.
It has a configuration in which it is connected to two video lines L1 and L2 via 1 and Tr2 (for this configuration,
See, for example, JP-A-64-14959).

Here, the CDS circuit 1 shown in FIG. 7 and FIG.
05, 105A and 105B are each composed of one clamp circuit and one sample and hold circuit.

[0019]

However, in the conventional solid-state image pickup device shown in FIG. 7, as shown in FIG. 8, a series of operations (read operation trd, reset operation trs, after reset, for one pixel 101) is performed. It is necessary to perform the black level read operation trb) for the number of horizontal pixels during one effective horizontal scanning period Ha. In this case, assuming that the pixel signal output rate is 1 / T [MHz], the vertical signal line (VS1
, VS2 ... VSn) and the signal processing operation on the video line L performs the above series of operations (read operation trd, reset operation trs, black level read operation trb after reset) during T seconds, Vertical signal line (VS1,
VS2 ... VSn) and the signal processing on the video line L are operated at a speed of 2 to 3 times the output rate.

The current solid-state image pickup device of, for example, the NTSC system can be operated by the above system, but especially in the high-definition system, the vertical signal lines (VS1, VS2 ... V) are used.
Sn) and the video line L do not catch up with the speed of signal processing, resulting in inoperability.

Specifically, in the case of a solid-state image pickup device having 2 million pixels, the output rate is 74.25 [MHz]. In this case, as shown in FIG.
= The signal processing speed in the vertical signal lines (VS1, VS2 ... VSn) and the video line L is 150 [MHz because it is necessary to perform three operations of the signal read trd, the reset trs, and the black level read trb within the period T seconds. ] Very high speed operation is required.

On the other hand, since the solid-state image sensor shown in FIG. 9 connects two CDS circuits 105A and 105B corresponding to the vertical signal lines (VS1, VS2 ... VSn), the solid-state image sensor is, for example, When supporting the high-definition system, the number of clamp circuits that make up the CDS circuit is 4
You also need 000. As a result, there is a problem that the circuit configuration of the solid-state image sensor becomes very complicated, leading to an increase in size of the solid-state image sensor and an increase in manufacturing cost.

The present invention has been made in view of the above problems, and an object of the present invention is to enable signals from pixels to be read out at a low speed even for a high-definition system, thereby increasing the output rate. An object of the present invention is to provide a solid-state image sensor capable of preventing the inoperable state associated therewith.

Further, according to the present invention, the high frequency component of the high frequency random noise generated from the pixel due to the increase in the output rate can be removed, and the S / N of the image pickup signal can be improved. It is to provide an element.

Further, according to the present invention, when the solid-state image pickup device is applied to the interlaced scanning system, the number of CDS circuits connected corresponding to the vertical signal lines, particularly the number of clamp circuits constituting the CDS circuit can be reduced, It is an object of the present invention to provide a solid-state image sensor that can realize a reduction in size of the image sensor itself and a reduction in manufacturing cost.

[0026]

SUMMARY OF THE INVENTION The present invention provides a large number of pixels 1.
Are arranged in a matrix, a vertical scanning circuit 3 for selecting pixels 1, 1 ... In row units, and a horizontal scanning circuit 4 for selecting pixels 1, 1. In the built-in solid-state image pickup device, the output line L arranged between the image pickup area 2 and the horizontal scanning circuit 4 is connected with the correlated double sampling circuits 5 for the number of horizontal pixels.

In this case, when the solid-state image pickup device is applied to the non-interlaced scanning system, the correlated double sampling circuit 5 is used for the n rows selected by the vertical scanning circuit 3 during the horizontal blanking period HB. Eye pixel 1,1 ...
A clamp circuit 11 for holding the signal level at a predetermined potential VCL, and the pixels 1, 1 ...
The sample-and-hold circuit 12 for sample-holding the level after resetting in.

When the solid-state image pickup device is applied to the interlaced scanning method, the correlated double sampling circuit 5 is selected in time series by the vertical scanning circuit 3 during the horizontal blanking period HB. The one clamp circuit 11 holds the signal levels of the pixels 1, 1 ... In the row 1 and the row n + 1, respectively, and the reset in the pixels 1, 1. A first sample-and-hold circuit 12A that samples and holds the subsequent level and a sampled level after resetting in the pixels n1, 1 ... Of the selected n + 1th row.
The second sample-hold circuit 12B for holding is used.

[0029]

In the solid-state image pickup device according to the present invention, for example, when the solid-state image pickup device is applied to the non-interlaced scanning system, first, during the horizontal blanking period HB, the pixel 1 of the nth row in the vertical scanning circuit 3 , 1 ... is selected. At this time, signals corresponding to the accumulated charges of the selected pixels 1, 1, ... Of the nth row are input to the corresponding CDS circuits 5, respectively. The CDS circuit 5 holds the input signal at the predetermined potential VCL by the clamp circuit 11. Thereafter, the pixels 1, 1, ... Of the selected nth row are reset to sweep out the accumulated charges.

After the reset operation for this pixel, C
A signal (black level) when there is no accumulated charge is input to the DS circuit 5. Since the CDS circuit 5 samples and holds the input signal (black level) in the sample and hold circuit 12, the sample and hold circuit 11 determines the difference between the signal accompanying the accumulated charge and the signal (black level). That is, the actual signal amount associated with the accumulated charge is held. That is, on the output side of each CDS circuit 5, among the pixels 1, 1, ... Of the n-th row, the corresponding pixels 1, 1, ...
・ The signal amount of will be retained.

Then, in the effective horizontal scanning period Ha after the horizontal blanking period HB, by sequentially reading the signal amount from each CDS circuit 5, the pixels 1, 1 of the nth row are read.
It is possible to take out the image pickup signal regarding.

As described above, since the series of operations of the signal read operation, the reset operation, and the black level read operation after the reset need to be performed only once during the horizontal blanking period HB, the above series of operations is extremely necessary. Can be performed at a low speed, and during the effective horizontal scanning period Ha,
Since the series of operations described above is not performed and only the operation of reading the signal amount from the CDS circuit 5 is performed, the signal processing of the output line L can be performed at a speed substantially equal to the output rate. Therefore, even when the solid-state imaging device is applied to the high-definition system, the signals from the pixels 1, 1 ... Can be read at a low speed, and the inoperable state due to the increase in the output rate can be prevented. .

Moreover, as described above, since the bandwidth of the signal processing speed of the output line L can be narrowed, the high range of the high range random noise generated from the pixels 1, 1 ... With the increase in the output rate. The component can be removed, and the S / N of the image pickup signal can be improved.

Next, when the solid-state image pickup device is applied to the non-interlaced scanning system, first, during the horizontal blanking period HB, the vertical scanning circuit 3 causes the pixels 1, 1 ...
・ Select. At this time, the signals corresponding to the respective accumulated charges of the selected n-th row pixels 1, 1, ...
It is input to each of the DS circuits 5. Each CDS circuit 5
The input signal is held at the predetermined potential VCL by the clamp circuit 11. After that, the selected pixels n, 1 of the nth row
... is reset and the accumulated charge is swept out.

After the reset operation for the pixels 1, 1, ..., A signal (black level) when there is no accumulated charge is input to each CDS circuit 5. Each CDS circuit 5 receives the input signal (black level) from the first sample
Since the sample is held by the hold circuit 12A,
The first sample-and-hold circuit 12A holds the difference between the signal associated with the accumulated charge and the black level (the actual signal amount associated with the accumulated charge). That is, the first sample-and-hold circuit 12A has pixels 1, 1 of the nth row.
.., the signal amount of the corresponding pixel 1 is held.

Thereafter, during the same horizontal blanking period HB, the vertical scanning circuit 3 causes the pixels 1 and 1 of the (n + 1) th row.
... is selected. At this time, signals corresponding to the respective accumulated charges of the pixels n1, 1 ... Of the selected n + 1th row are input to the corresponding CDS circuits 5, respectively. Each CDS circuit 5
Input the input signal to the clamp circuit 11 at a predetermined potential V
Hold in CL. After that, the selected pixels n1, 1 ... Of the n + 1th row are reset to sweep out the accumulated charges.

After the reset operation for the pixels 1, 1, ..., A signal (black level) when there is no accumulated charge is input to each CDS circuit 5. Since each CDS circuit 5 samples and holds the input signal (black level) this time by the second sample and hold circuit 12B, the accumulated charge is stored in the second sample and hold circuit 12B. The difference between the accompanying signal and the black level (the actual signal amount due to the accumulated charge) is held. That is, the second
The sample-and-hold circuit 12B holds the signal amounts of the pixels 1 corresponding to the pixels 1, 1 ... Of the (n + 1) th row.

Then, in the effective horizontal scanning period Ha after the horizontal blanking period HB, by sequentially reading the signal amount from each CDS circuit 5, the image pickup for the pixels 1, 1 ... Of the nth row and the n + 1th row is performed. The signal can be retrieved.

As described above, in the solid-state image pickup device, each signal level in the pixels 1, 1 ... Of the nth row and the n + 1th row selected in time series by the vertical scanning circuit 3 is clamped by one clamp. Each of the circuits 11 has a predetermined potential VCL
Therefore, it is not necessary to connect two CDS circuits, especially two clamp circuits to one vertical signal line VS as in the conventional case, so that one vertical signal line V
It is only necessary to connect one clamp circuit 11 to S. Therefore, when the solid-state image pickup device is applied to the interlaced scanning system, the number of the CDS circuits 5 connected corresponding to the vertical signal lines VS, particularly the clamp circuit 11 constituting the CDS circuit 5, can be reduced, and the solid-state image pickup device itself. It is possible to realize a smaller size and a lower manufacturing cost.

[0040]

EXAMPLES Two examples in which the solid-state image sensor according to the present invention is applied to an internal amplification type solid-state image sensor by CMD (hereinafter, the solid-state image sensor according to the first example and the solid-state image sensor according to the second example) will be described. Element) will be described with reference to FIGS.

The solid-state image pickup device according to the first embodiment is applied to the non-interlaced scanning system, and as shown in FIG. 1, CMDs (pixels) 1 of 1 transistor / pixel are arranged in a matrix. .. is provided in the periphery of the imaging area 2, and a vertical scanning circuit 3 for selecting the pixels 1, 1, ... In row units and a horizontal scanning circuit for selecting the pixels 1, 1 .. A circuit 4 is provided.

The vertical signal line VS1 that is common to the pixels 1, 1 ... In one column and is arranged in the column direction.
, VS2 ... VSn are connected to sources of pixels (CMD) 1, 1 ...
Horizontal selection lines VL1, VL2, ... VLn that are common to the pixels 1, 1 ... In one row and are arranged in the row direction.
, The pixel (CMD) 1 for the corresponding row,
The gates of 1 ... Are connected. In addition, each pixel 1,
The drains of 1 ... Are made common, and the power supply voltage Vdd is applied.

The vertical scanning circuit 3 is composed of, for example, a shift register which outputs a binary logical output, and a level mix circuit which generates a ternary voltage output (Va, Vb, Vc) from the logical output and clock timing. ing.

Further, each vertical signal line VS1, VS2 ...
On the VSn horizontal scanning circuit 3 side, the signal currents associated with the optical signal charges in the respective pixels 1, 1 ...
The load resistance RL for converting to Vn is connected, and the CDS circuit 5 is connected to the subsequent stage of each load resistance RL. Each CDS circuit 5 is connected to a video line L connected to the output terminal φ via a switching transistor Tr, and column selection lines HL1, HL2 ... HLn for the number of horizontal pixels extending from the horizontal scanning circuit 4 are Each is connected to the gate of the corresponding switching transistor Tr.

Each CDS circuit 5 comprises, for example, as shown in FIG. 2, one clamp circuit 11 and one sample and hold circuit (hereinafter, simply referred to as S / H circuit) 12. The clamp circuit 11 includes a coupling capacitor C for removing a DC component of an input signal, a switching transistor TCL connected to a signal line VS via a node a, a drive transistor Qa having a gate connected to a signal line VS, and a constant current. The source follower circuit 13 is composed of a load transistor QL constituting a source. The switching transistor TCL has a source connected to the signal line VS and a drain fixed to the clamp potential VCL. Therefore, in the clamp circuit 11, by applying the control pulse Pc to the gate, the ON operation is performed and the potential of the signal line VS is held at the clamp potential VCL.

On the other hand, the S / H circuit 12 is the clamp circuit 1
A switching transistor TSH whose drain is a common source contact b of the source follower circuit 13 in FIG.
A capacitor Cs connected between the node c of the signal line S extending from the source of the switching transistor TSH and the ground;
The source follower circuit 14 includes a drive transistor QaS having a gate connected to the signal line S and a load transistor QLS forming a constant current source. Then, by supplying the sampling pulse Ps to the gate of the switching transistor TSH, the clamp circuit 1
The charge corresponding to the signal current from 1 is accumulated in the capacitor Cs,
A potential corresponding to the accumulated charge appears at the common source contact d of the source follower circuit 14. In addition, this source contact d
Is supplied to the drain of the switching transistor Tr shown in FIG.

Next, the operation of the solid-state image pickup device according to the first embodiment will be described with reference to the timing chart of FIG. For simplification of description, the gain of each of the source follower circuits 13 and 14 of the clamp circuit 11 and the S / H circuit 12 in the CDS circuit 5 will be described as 1.

First, during charge accumulation (exposure), the vertical scanning circuit 3 outputs a low voltage Va that cuts off each pixel (CMD) 1, 1, ...
・ Applied to the gate of. When the photo-generated holes are accumulated in the gate portion of each pixel 1, 1 ... With the incidence of light from the subject, the photo-generated holes are accumulated in the surface potential of each pixel 1, 1. It rises according to the holes.

Then, during the horizontal blanking period HB,
The vertical scanning circuit 3 supplies a read voltage Vb higher than the above voltage Va to, for example, the pixels 1, 1 ... In the first row. As a result, the pixels 1, 1, ... Of the first row are selected, and the pixels 1, 1, ...
A signal current corresponding to each accumulated charge of 1 flows into the load resistor RL, and a voltage change (signal voltage) V1 due to the signal current V1
(S1), V2 (S1) ... Corresponding CDS circuit 5
Are input respectively. At this time, the switching transistor TCL of the clamp circuit 11 in each CDS circuit 5
A control pulse is applied to the gate of. As a result, the signals V1 (S1) and V2 (S1) supplied to each CDS circuit 5
... are held at the clamp potential VCL. At the same time,
Switching transistor TSH in the S / H circuit 12
A sampling pulse Ps is applied to the gate of the capacitor C, whereby charges corresponding to the clamp potential VCL are charged to the capacitance C.
stored in s.

After that, the vertical scanning circuit 3 supplies a reset voltage Vc higher than the read voltage Vb to the pixels 1, 1, ... Of the selected first row. By applying the reset potential Vc, the pixels 1, 1, ...
..All are reset. That is, the pixels 1, 1 in the first row
The photo-generated holes accumulated in ... Are swept away to the substrate side.

After that, the reading voltage Vb is again supplied from the vertical scanning circuit 3 to the pixels 1, 1, ... Of the selected first row. At this time, since the photogenerated holes do not exist in the selected pixels 1, 1 ... Of the first row, the surface potential thereof changes depending on the potential applied to the gate. The value is lower than the surface potential of. Therefore, the voltage levels V1, V2, ... Input to each CDS circuit 5 during this period are higher than the signal voltage levels V1 (S1), V2 (S1). The level depends only on the characteristic, that is, the black levels V1 (B1), V2 (B1) ... Of the pixel.

These black levels V1 (B1), V2 (B1) ...
When reading, the sampling pulse Ps is applied to the gate of the switching transistor TSH of the S / H circuit 12. At this time, the black level V1 (B1),
The difference between the charge amount corresponding to V2 (B1) ... and the charge amount corresponding to the clamp potential (signal level) VCL, that is, the actual signal voltage V1 accompanying the accumulated charge generated by the incident light.
Electric charges corresponding to 1, V21 ... Are accumulated. Therefore, the S / H circuit 12 of each CDS circuit 5 has 1
With respect to the pixels 1, 1, ... Of the row, the signal amounts V11, V21, ... Of the corresponding pixels 1, 1 ,.

Then, in the effective horizontal scanning period Ha after the horizontal blanking period HB, the horizontal scanning circuit 4 sequentially outputs the selection pulses P1, P2, ...
・ Turn on sequentially. As a result, the CDS circuits 5 are sequentially selected, and the signals V11, V21, ... According to the charges held in the S / H circuits 12 appear on the video line L in time series. This is equivalent to sequentially selecting the pixel 1 in the column in which the switching transistor Tr is turned on among the pixels 1, 1 ... In the first row selected by the vertical scanning circuit 3. The signal of the selected pixel 1 is taken out from the output terminal φ via the video line L. That is, in the effective horizontal scanning period Ha after the horizontal blanking period HB, the signals V11, V21, ... Are read sequentially from each CDS circuit 5 to relate to the pixels 1, 1 ,. The image pickup signal can be taken out.

Then, in the next horizontal blanking period HB, the pixels 1, 1, ... Of the second row are selected this time,
Similarly to the above, during the horizontal blanking period HB, 2
Signal amount V12, V22 ...
Are held in the S / H circuit 12 respectively. Then, similarly to the above, in the effective horizontal scanning period Ha after the horizontal blanking period HB, the signal V1 is sequentially output from each CDS circuit 5.
By reading out 2, V22 ..., It is possible to take out the image pickup signal for the pixels 1, 1, ...

Generally speaking, in the horizontal blanking period HB, the pixels 1, 1, ... Of the nth row are selected, and during the horizontal blanking period HB, the pixels 1, 1 of the nth row are selected.
.. are stored in the S / H circuit 12, and the effective horizontal scanning period H after the horizontal blanking period HB is held.
In a, by sequentially reading the signals from the CDS circuits 5, it is possible to take out the image pickup signal for the pixels 1, 1 ... Of the nth row from the output terminal φ.

As described above, according to the solid-state image sensor according to the first embodiment, a series of operations of the signal read operation, the reset operation, and the black level read operation after the reset are performed during the horizontal blanking period HB. Since the series of operations need only be performed once, it becomes possible to perform the series of operations at a very low speed. Further, during the effective horizontal scanning period Ha, the series of operations are not performed, and the signal amount from each CDS circuit 5 is simply used. Read out the video line L
Signal processing can be performed at a speed almost equal to the output rate. Therefore, even when the solid-state image sensor is applied to the high-definition system, the horizontal blanking period (2.6
.mu.s), signals from the respective pixels 1, 1 ... Can be read out at a low speed, and an inoperable state due to an increase in output rate can be prevented.

Moreover, as described above, since the bandwidth of the signal processing speed of the video line L can be narrowed, the high range of the high range random noise generated from the pixels 1, 1 ... With the increase in the output rate. The component can be removed, and the S / N of the image pickup signal can be improved.

Next, the solid-state image sensor according to the second embodiment will be described with reference to FIGS. 1 to
Components corresponding to those in FIG. 3 are designated by the same reference numerals.

The solid-state image pickup device according to the second embodiment is applied to the interlaced scanning system, and as shown in FIG. 4, it has almost the same structure as that of the first embodiment, but is different in the following points. That is, 2 corresponding to the interlace system
The video lines L1 and L2 of the book are wired. C connected to each vertical signal line VS1, VS2, ... VSn
The DS circuit 5 includes one clamp circuit 11 and two S / H circuits (first S / H circuit 12A and second S / H circuit 12).
Be configured in B). That is, two switching transistors (Tr1 and Tr2) are provided for each of the first and second S / H circuits 12A and 12B for selecting the CDS circuit 5.

Here, one of the components of the CDS circuit 5 is
As shown in FIG. 5, the clamp circuit 11, which is the third one, is composed of a coupling capacitor C, a switching transistor TCL, and a source follower circuit 13, as in the case of the first embodiment. The H circuit 12A includes a first switching transistor TSH1, a first capacitor Cs1, and a first source follower circuit 14A, and a second switching transistor TSH1 and a second source follower circuit 14A.
The S / H circuit 12B includes a second switching transistor TSH2, a second capacitor Cs2, and a second source follower circuit 14B. The drain of the first switching transistor TSH1 and the drain of the second switching transistor TSH2 are clamp circuits 1 respectively.
1 is connected to the common source contact b of the source follower circuit 13. The potentials of the common source contacts d1 and d2 in the first and second source follower circuits 14A and 14B are supplied to the drains of the corresponding switching transistors Tr1 and Tr2.

Next, the operation of the solid-state image pickup device according to the second embodiment will be described with reference to the timing chart of FIG.

First, at the time of charge storage (exposure), each pixel (C
A low voltage Va that cuts off MD) 1, 1 ... Is output and applied to the gates of the pixels 1, 1. With the incidence of light from the subject, light-generated holes are generated in each pixel 1,
When accumulated in the gate part of 1 ...
・ The surface potential of the cell rises according to the accumulated photogenerated holes.

Then, in the first half of the horizontal blanking period HB, for example, the pixels 1, 1, ...
・ Read voltage Vb higher than the above voltage Va
To supply. As a result, the pixels 1, 1, ...
Has been selected, and a signal current corresponding to each accumulated charge of the pixels 1, 1 ... Of the selected first row flows into the load resistance RL, and a voltage change (signal voltage) due to the signal current
V1 (S1), V2 (S1) ... Are input to the corresponding CDS circuits 5, respectively. At this time, the switching transistor T of the clamp circuit 11 in each CDS circuit 5
The control pulse Pc is applied to the gate of CL. As a result, the signals V1 (S1), V2 supplied to each CDS circuit 5
(S1) ... Is held at the clamp potential VCL. At the same time, the sampling pulse Ps1 is applied to the gate of the first switching transistor TSH1 in the first S / H circuit 12A, whereby charges corresponding to the clamp potential VCL are stored in the first capacitor Cs1.

After that, the vertical scanning circuit 3 supplies a reset voltage Vc higher than the read voltage Vb to the pixels 1, 1, ... Of the selected first row. By applying the reset potential Vc, the pixels 1, 1, ...
..All are reset. That is, each pixel 1, 1 ...
The photogenerated holes accumulated in the substrate are swept away to the substrate side.

Thereafter, the read voltage Vb is supplied again from the vertical scanning circuit 3 to the selected pixels 1, 1, ... In the first row, and the pixels 1, 1 ,. The black levels V1 (B1), V2 (B1), ... Are input to the corresponding CDS circuits 5. At this time, the sampling pulse Ps1 is applied to the gate of the first switching transistor TSH1 in the first S / H circuit 12A, and the black level V1 (B1),
The difference between the charge amount corresponding to V2 (B1) ... and the charge amount corresponding to the clamp potential (signal level) VCL, that is, the actual signal voltage V1 accompanying the accumulated charge generated by the incident light.
Electric charges corresponding to 1, V21 ... Are accumulated. That is, in the first S / H circuit 12A of each CDS circuit 5, the signal amounts V11, V21 ... Of the pixels 1, 1, ... Will be retained.

Thereafter, in the latter half of the same horizontal blanking period HB, the vertical scanning circuit 3 causes the pixels 1, 1, ...
Is supplied with a read voltage Vb. As a result, the pixels 1, 1, ... Of the second row are selected, and the signal currents corresponding to the respective accumulated charges of the pixels 1, 1 ,. Flow to RL,
Voltage change (signal voltage) V1 (S2), V2 (S
2) are input to the corresponding CDS circuits 5, respectively. At this time, the control pulse Pc is applied to the gate of the switching transistor TCL of the clamp circuit 11 in each CDS circuit 5. As a result, each CDS circuit 5
The signals V1 (S2), V2 (S2), ... At the same time, the second S / H
Second switching transistor T in circuit 12B
Sampling pulse Ps2 is applied to the gate of SH2,
As a result, charges corresponding to the clamp potential VCL are stored in the second capacitor Cs2.

Thereafter, the reset voltage V is applied from the vertical scanning circuit 3 to the pixels 1, 1, ...
c is supplied. By applying the reset potential Vc, all the pixels 1, 1 ... In the second row are reset.

After that, the read voltage Vb is supplied again from the vertical scanning circuit 3 to the pixels 1, 1, ... Of the selected second row, and the pixels 1, 1, ... Of the second row are supplied. The black levels V1 (B2), V2 (B2), ... In are input to the corresponding CDS circuits 5, respectively. At this time, the sampling pulse Ps2 is applied to the gate of the second switching transistor TSH2 in the second S / H circuit 12B, and each second capacitance Cs2 receives an actual signal accompanying the accumulated charge generated by the incident light. Electric charges corresponding to the voltages V12, V22 ... Are accumulated. Therefore, in the second S / H circuit 12B of each CDS circuit 5, the pixels 1, 1, ...
.., the signal amounts V12 and V22 of the corresponding pixel 1
... will be retained.

Then, in the effective horizontal scanning period Ha after the horizontal blanking period HB, the horizontal scanning circuit 4 sequentially outputs the selection pulses P1, P2, ... By corresponding switching transistors Tr1, Tr2.
Turn on sequentially. As a result, the CDS circuits 5 are sequentially selected, the signals V11, V21, ... According to the charges held in the first S / H circuits 12A appear on the video line L1 in time series, and the respective second , Corresponding to the charges held in the S / H circuit 12B, appear on the video line L2 in time series. This is the pixels 1 and 1 of the first and second rows selected by the vertical scanning circuit 3.
... is equivalent to sequentially selecting the pixels 1 in the columns in which the corresponding switching transistors Tr1 and Tr2 are turned on, and the signals of the selected pixels 1 are transmitted via the video lines L1 and L2, respectively. It is taken out from the output terminals φ1 and φ2, respectively. That is, in the effective horizontal scanning period Ha after the horizontal blanking period HB, the signals are sequentially read from the CDS circuits 5, so that the output terminals L1 and L2 output the first row and the second row, respectively.
It is possible to take out the image pickup signal for the pixels 1, 1, ...

Then, in the next horizontal blanking period HB, the pixels 1, 1, ... Of the third and fourth rows are selected, and the horizontal blanking period H is set in the same manner as described above.
In B, the signal amounts V13, V23 ... And V14, V24 ... For the pixels 1, 1 ... In the third and fourth rows are the first capacitances in the first S / H circuit 12A. Cs1 and the second capacitor Cs2 in the second S / H circuit 12B are respectively stored. Then, similarly to the above, in the effective horizontal scanning period Ha after the horizontal blanking period HB,
The signals V13, V23, ... And V1 are sequentially output from each CDS circuit 5.
By reading 4, V24 ..., each output terminal φ1
, And .phi..sub.2, the image pickup signals for the pixels 1, 1, ... In the third and fourth rows can be taken out.

Generally speaking, in the horizontal blanking period HB, the pixels 1, 1, ...
Are selected, and the signal amounts relating to the pixels 1, 1 ... Of the n-th row and the n + 1-th row are selected during the horizontal blanking period HB, respectively, in the first capacitance C in the first S / H circuit 12A.
s1 and the second capacitance C in the second S / H circuit 12B
In the effective horizontal scanning period Ha after the horizontal blanking period HB, the signals are sequentially read out from the CDS circuits 5, so that the pixels 1, 1 of the nth row and the n + 1th row from the output terminals φ1 and φ2 are stored. It is possible to take out the image pickup signal regarding.

As described above, according to the solid-state image pickup device of the second embodiment, the signals from the pixels 1, 1 ... Can be read out, and the inoperable state due to the increase in the output rate can be prevented.

Moreover, as described above, the video line L1
Since the bandwidth of the signal processing speed of L2 and L2 can be narrowed, it is possible to remove the high frequency component of the high frequency random noise generated from the pixels 1, 1 ... The S / N can be improved.

Particularly, in the second embodiment, the signal levels in the pixels 1, 1, ... Of the nth row and the n + 1th row selected in time series by the vertical scanning circuit 3 are set to one clamp circuit 11. Since each of them is held at the clamp potential VCL, it is not necessary to connect two CDS circuits, especially two clamp circuits to one vertical signal line as in the conventional case, and one vertical signal line is not required. Only one clamp circuit 11 needs to be connected to VS. Therefore, when the solid-state imaging device is applied to the interlaced scanning method, the number of the CDS circuits 5 connected corresponding to the vertical signal lines VS, particularly the number of the clamp circuits 11 constituting the CDS circuit 5, can be reduced, and the solid-state imaging device itself. It is possible to realize a smaller size and a lower manufacturing cost.

In the solid-state image pickup device according to the first and second embodiments, the CM is used as the internal amplification type solid-state image pickup device.
Although the example applied to the solid-state image pickup device by D is shown, it is also applicable to the internal amplification type solid-state image pickup device such as AMI and SIT.

[0076]

As described above, according to the solid-state image pickup device of the present invention, an image pickup region in which a large number of pixels are arranged in a matrix, a vertical scanning circuit for selecting pixels in row units, and a column unit in column units. In a solid-state image sensor including a horizontal scanning circuit for selecting pixels, a correlated double sampling circuit for the number of horizontal pixels is connected to an output line arranged between the image capturing area and the horizontal scanning circuit. When the element is applied to the non-interlaced scanning method, the correlated double sampling circuit holds the signal level in the pixel of the nth row selected by the vertical scanning circuit at a predetermined potential during the horizontal blanking period. Since the circuit and the sample and hold circuit that samples and holds the level after reset in the selected n-th row pixel are configured, Can also be read signals from pixels at a low speed relative to the system, the inoperative state due to the speed of the output rate can be prevented. In addition, it is possible to remove the high frequency component of the high frequency random noise generated from the pixels as the output rate is increased, and it is possible to improve the S / N of the image pickup signal.

Further, when the solid-state image pickup device is applied to the interlaced scanning system, the above-mentioned correlated double sampling circuit is used for the nth row and the n + 1th row which are selected in time series by the vertical scanning circuit during the horizontal blanking period. One clamp circuit that holds each signal level in the pixel of the eye at a predetermined potential, a first sample-hold circuit that samples and holds the level of the selected pixel in the n-th row after reset, and the selection Since the second sample-hold circuit that samples and holds the level after resetting in the pixel of the (n + 1) th row is performed, the above-described effect is exhibited and the CDS connected corresponding to the vertical signal line is provided. It is possible to reduce the number of circuits, particularly the number of clamp circuits that make up the CDS circuit, reduce the size of the solid-state imaging device itself, and reduce the manufacturing cost. It is possible to realize the cost reduction of the bets.

[Brief description of drawings]

FIG. 1 is an equivalent circuit diagram showing a configuration of a first embodiment (hereinafter, referred to as a solid-state image sensor according to the first embodiment) in which a solid-state image sensor according to the present invention is applied to an internal amplification type solid-state image sensor by CMD. Is.

FIG. 2 is a circuit diagram showing a configuration of a correlated double sampling circuit (hereinafter, simply referred to as a CDS circuit) connected to the solid-state image sensor according to the first embodiment.

FIG. 3 is a timing chart showing a signal processing operation of the solid-state image sensor according to the first example.

FIG. 4 is an equivalent circuit diagram showing a configuration of a second embodiment (hereinafter, referred to as a solid-state image sensor according to the second embodiment) in which the solid-state image sensor according to the present invention is applied to an internal amplification type solid-state image sensor by CMD. Is.

FIG. 5 is a C connected to the solid-state image sensor according to the second embodiment.
It is a circuit diagram which shows the structure of a DS circuit.

FIG. 6 is a timing chart showing a signal processing operation of the solid-state image sensor according to the second example.

FIG. 7 is an equivalent circuit diagram showing a configuration of a solid-state image sensor according to a conventional example.

FIG. 8 is a timing chart showing a signal processing operation of a solid-state image sensor according to a conventional example.

FIG. 9 is an equivalent circuit diagram showing a configuration of a solid-state imaging device according to another conventional example.

[Explanation of symbols]

 1 pixel (CMD) 2 imaging area 3 vertical scanning circuit 4 horizontal scanning circuit 5 CDS circuit 11 clamp circuit 12, 12A, 12B S / H circuit

Claims (3)

[Claims] 1. An imaging area in which a large number of pixels are arranged in a matrix, and a vertical scanning circuit for selecting pixels in units of rows,
In a solid-state imaging device having a built-in horizontal scanning circuit for selecting pixels on a column-by-column basis, a correlated double sampling circuit for the number of horizontal pixels is connected to an output line arranged between the imaging area and the horizontal scanning circuit. A solid-state image sensor characterized in that. 2. The correlated double sampling circuit includes a clamp circuit that holds a signal level of a pixel in the nth row selected by the vertical scanning circuit at a predetermined potential during a horizontal blanking period, and the selected circuit. The solid-state imaging device according to claim 1, wherein the solid-state imaging device comprises a sample and hold circuit that samples and holds the level of the pixel in the n-th row after reset. 3. The correlated double sampling circuit sets, during a horizontal blanking period, each signal level in pixels of the nth row and the n + 1th row selected in time series by the vertical scanning circuit to predetermined potentials. One clamp circuit for holding, a first sample-hold circuit for sampling and holding the level after reset in the selected n-th row pixel, and a level after reset in the selected n + 1-th row pixel 2. The solid-state image sensor according to claim 1, wherein the solid-state image sensor comprises a second sample-and-hold circuit for sampling and holding.