WO2001001674A1

WO2001001674A1 - Pixel reading electronic device in particular for matrix image sensor with active cmos pixels

Info

Publication number: WO2001001674A1
Application number: PCT/FR2000/001757
Authority: WO
Inventors: Yavuz Degerli; Jean Farre; Francis Lavernhe; Pierre Magnan
Original assignee: Ecole Nationale Superieure De L'aeronautique Et De L'espace (Supaero)
Priority date: 1999-06-23
Filing date: 2000-06-23
Publication date: 2001-01-04
Also published as: FR2795586A1; FR2795586B1; AU5990600A

Abstract

The invention concerns an electronic device for reading pixels of a matrix image sensor, in particular for a sensor with active CMOS-type pixels, said sensor comprising N lines and M columns of active pixels (1). The invention is characterised in that it comprises signal acquisition means, adapted to send directly, for each pixel (1) of each column, on an output bus (18) a signal representing the potential difference between a reference signal Vref and a light level signal Vsig of said pixel (1).

Description

"Electronic pixel reading device, in particular for a CMOS active pixel matrix image sensor"

The invention is in the field of electronic image acquisition devices. It relates more particularly to a device for reading the variation in electrical potential of each pixel receiving a light signal.

The invention lies in the field of light signal acquisition by photosensitive pixel. It can be used for many types of signal sensors, for example image signal in the visible, UV, infrared, X range, as well as pressure sensors or fingerprint reading, etc.

In the following description, the term imager is used to denote an image sensor formed from a matrix of photosensitive pixels, which consist of a photosensitive detector alone or associated with transistors.

An imager usually has several thousand to several million pixels, the states of which under the effect of a light signal are transformed by a signal processing device into a final image which can be used, for example in a computer system before visualization and / or storage and printing.

For these devices, one of the natural objectives is to improve the performance of the pixel signal acquisition chain, that is to say the electronic device which reads for each pixel the variation in potential at the output of the pixel, which results reception by said pixel of a certain number of photons (light signal).

One of the image noises, known as spatial noise or FPN (Fixed Pattern Noise), is currently one of the major problems of image sensors, in particular active CMOS pixels.

Correlated Double Sampling (CDS) double sampling methods are conventionally used to: - remove the kT / C type noise from the node performing the charge voltage conversion in the pixel or at the output of the imager (often called "floating scattering"),

- suppress FPN noise due to non-uniformities of the transistors of the internal amplifiers to the pixels,

- and reduce the low frequency noise generated by the MOS transistors used for reading or transferring the electrical signal.

The CDS correlated double sampling method consists in first sampling the reference level Vref of the pixel to be read, then the signal level Vsig representative of the number of incident photons received by the pixel.

After this operation, a difference operation is carried out on these two signals, by hardware or software method known to those skilled in the art, which provides an electrical voltage proportional to the number of incident photons.

The classic reading architecture in the CDS process, as used in most active pixel image sensors, is illustrated in Figure 1.

It comprises, for each column, two main blocks [switch - capacity - follower] 10R, 10S, intended to sample and store the reference signals Vref and light level Vsig. More precisely, in a conventional architecture with double correlated sampling CDS of pixel reading, as illustrated in FIG. 1 for a single column, we observe initially, just after having closed then opened a controlled switch (switch) 13 controlled by a signal RST, at the output of an active pixel 1 of CMOS type a voltage Vref at point A (the pixel being supplied by a voltage V _DD ).

In this initial state, a first capacitor 2 (Cref) is preloaded, by means of a transistor forming a switch 4 (the term "switch" will be used interchangeably for such switches controlled in the rest of the description) controlled by an SHR signal. This capacity 2 therefore serves to "memorize" the initial voltage value of the pixel Vref.

When pixel 1 has been subjected to a light signal, switch 13 (controlled by an RST signal), being then open, the charge-voltage conversion is carried out by a capacitor 3, the output voltage at point A changes to Vsig, and the difference Vref - Vsig is characteristic of the signal intensity received.

This potential is in turn stored in a second capacitance 5 Csig, by means of a second transistor forming a switch 6 controlled by a signal SHS.

The purpose of the reading chain is then to measure a potential difference ΔV which is a function of the difference between the reference signal Vref and the light level signal Vsig. It is desirable, as we understand, that this measurement be carried out in the least noisy possible, and as quickly as possible.

In the devices currently used (FIG. 1), the measurement of this potential difference is carried out "outside" the device which has just been described, after passing the signals Vref and Vsig in controlled amplifiers 7, 8, thus forming the signals denoted Voutl and Vout2 respectively.

Adding followers (Figure 2: amplifiers M1, M'1, switches M2, M'2) to blocks 10R, 10S for each column naturally introduces asymmetries and is therefore a source of measurement errors on the difference of potential ΔV of each pixel. The noise thus generated on the finally usable signal contributes to the noise known to a person skilled in the art under the name of column spatial noise or FPN column (from the English Fixed Pattern Noise), not eliminated by CDS reading.

Furthermore, due to the reading process which is conventionally carried out column by column in a pixel matrix comprising N rows x M columns (for example 512 × 512), such an arrangement must be arranged at the output of each column of pixels (FIG. 2), and involves a large number of components, consuming space, which is obviously very limited on a pixel matrix. Such an arrangement is represented in FIG. 2 (in which the columns numbered from 1 to M are illustrated by the diagonal lines dotted). In this arrangement, it is understood that, for each column of active pixels, and for example for the first column, all the outputs of active pixels 1 terminate by a bus adapted to point A. When column 1 is "read", the switches controlled by signal X1 (column 1 selection signal) are closed simultaneously, while they are open when any of the other columns are being read.

In this way, only one column at a time provides the output values Voutl and Vout2, and, the pixels being read one after the other, each pixel is read in turn. In this illustration, the components M1, M2, M'1, M'2 are PMOS transistors

Polarization transistors Mb and Mb '(charge of the amplifiers M1, M'1) are conventionally introduced into such output architectures of these PMOS follower blocks. They are common to all columns, and VLP is the voltage used to polarize them.

The disadvantages of this architecture are as follows. 1 / The first drawback is that the non-uniformities of the threshold voltages of the transistors M1, M'1, Mb, M'b P channel of the follower blocks cause FPN noise. This column FPN noise is dominant in the total FPN noise of the imager.

A technique to deal with this column FPN noise problem has been proposed. This technique called DDS (from the English Delta-Difference Sampling or Delta-Double Sampling: double sampling), and described for example by the American author Mendis, uses a technique called "crow-bar" (materialized by block 9 figure 2: block surrounded by dotted lines) introduced in parallel with the Cref and Csig capacities (between the signal outputs Vref and Vsig).

In this device, the most precise determination of the potential difference ΔV requires two successive measurements because the signals

Voutl and Vout2 must be sampled twice for each pixel. We can refer on this point to the document by S.K. Mendis, H.E.

Kemeny & al. ("CMOS active Pixel image sensors for highly integrated imaging Systems ", IEEE Journal of Solid-State Circuits, Vol 32, n ° 2, 1997, pp 187-197).

In the case of large matrices, the number of measurements becomes considerable, and therefore penalizes the maximum reading speed of the pixels. It is clear that the FPN noise due to the asymmetry is eliminated (since it is measured successively by the two chains). On the other hand, the contribution of the temporal noise of the chain itself is doubled, due to the double measurement.

A reading method of this type can further reduce the pixel reading frequency by a factor of two.

In addition, the temporal noise powers generated by these follower circuits or amplifiers are not correlated, which doubles their total contribution to the noise power.

Finally, this solution still introduces a large number of components onto the matrix, which constitutes a significant drawback while the trend today is to reduce the size of the sensor matrices.

2 / Furthermore, the presence of M blocks of the type M1, M2, M'1, M'2 which are not active in parallel on the outputs Voutl and Vout2 gives rise to a large parasitic capacity. This prevents fast reading of large matrices.

Many CDS correlated double sampling architectures have been proposed in the literature for CCD (Charge Coupled Device) type sensors and infrared imagers.

However, CDS correlated double sampling architectures with multiple buffers (buffers) and amplifiers are not applicable for CMOS active pixel imagers.

CMOS active pixel imagers require one CDS circuit per column, and such circuits still create FPN noise.

Other architectures have been used for CMOS imagers of the photodiodes type. We can cite for example in this area: "A single chip CMOS 306 x 244 pixel NTSC video camera and a descending coprocessor device ", by Smith, Hurwitz, Torrie, Baxter, Murray, Likoudis, Holmes, Panaghiston, Henderson, Anderson, Denyer and Renshaw, published in IEEE Journal of Solid State circuits Vol 33 no.12 of 1998. Likewise, the article "Off-set free correction for active pixel sensors" Dierickx, Meynants and Scheffer, published in Proc. IEEE 1997 Workshop on CCD's and advanced image sensors (1997).

The object of the present invention is therefore to propose a new measurement chain for the pixel potential difference (a new correlated double sampling circuit for CMOS active pixel image acquisition matrix), which overcomes the preceding drawbacks, and in particular which reduces the measurement noise and the number of components required.

Advantageously, this device allows a much faster measurement of the pixels, and this speed gain is preferably even more significant in the case of matrices comprising a high number of pixels. In the present invention, a new circuit of CDS type is proposed, which can be used for a CMOS active pixel imager. This device minimizes FPN noise sources and the number of active components necessary for reading pixels.

To this end, the invention provides an electronic device for reading pixels from an image matrix sensor, in particular for a CMOS type active pixel sensor, said sensor comprising N rows and M columns of active pixels, characterized in that it comprises signal acquisition means, adapted to send directly, for each pixel of each column, to an output bus a signal representative of the potential difference between a reference signal Vref and a light level signal Vsig of this pixel the signal acquisition means being constituted by switches and capacitors. This potential difference is proportional to the light energy incident on the pixel.

This arrangement makes it possible to reduce the measurement noise, and in particular the noise due to an asymmetry of the measurement chains of the reference and light level signals. According to a preferred embodiment of the invention, the signal acquisition means comprise for each column at the output of the column bus according to FIG. 3:

- a first switch controlled by a SHR signal, making it possible to charge a Cref capacity connected to ground,

- a second switch controlled by a SHS signal, making it possible to charge a floating capacity Csig,

- a third switch controlled by a signal Xi for selecting the column read, disposed between the terminals of the Cref, Csig capacities, - a fourth switch controlled by the SHS signal, inserted downstream between the Csig capacity and the ground,

- And a fifth switch, controlled by the column selection signal Xi read, mounted downstream between the floating capacity Csig and a signal output bus. According to the preferred embodiment, the device comprises a single output buffer / amplifier, common to all the columns of the sensor.

These provisions are favorable to a very significant saving of resources in the practical realization of the device.

The invention relates in another aspect to a method of reading pixels from an image matrix sensor, in particular for a CMOS type active pixel sensor, said sensor comprising N rows and M columns of active pixels, characterized in that it involves the following steps:

1 / in each column, for the pixel whose signal is selected on an input bus, a reference value Vref is sampled first and stored in a capacity Cref of each corresponding column,

2 / then a value of the signal Vsig is sampled, for each same pixel, and stored in a floating capacity Csig of each corresponding column,

3 / then, column by column, Cref and Csig are connected in series thanks to a switch so as to obtain by their simultaneous discharge on the output bus via a switch a signal representative of the difference (Vref-Vsig) which is then amplified in a buffer / amplifier.

It is understood that this method allows a reading of each pixel in only three steps.

The description below and the appended drawing of a preferred embodiment of the invention will make it possible to better understand the aims and advantages of the invention. It is clear that this description is given by way of example, and is not limiting.

FIG. 1 is a simplified diagram of a conventional acquisition chain for measuring the voltage at the output of an active pixel of the prior art, FIG. 2 is a more complete diagram of this same circuit of the prior art,

FIG. 3 schematically represents an assembly in accordance with the invention,

FIG. 4 represents the mounting of an output buffer / amplifier, and

- Figure 5 is an example of a timing diagram of the levels of the different control and output signals of a circuit as a function of time, according to the invention.

FIG. 3 shows a circuit according to the invention comprising a single output buffer / amplifier 14, common to all the columns of an imager. The assembly has two capacities 2 Cref and 5 Csig which are chosen of equal value, Cs being the common value of Cref and Csig.

More precisely, for each column, there is, in a manner analogous to the conventional CDS architecture, a first switch 4 (also denoted sw1) controlled by a signal SHR, making it possible to charge the capacity 2 Cref mounted between a point B and the ground, and in parallel, a second switch 6 (also denoted sw2), controlled by a SHS signal, making it possible to charge the capacity 5 Csig (floating capacity) mounted between points C and D.

In the assembly described here by way of nonlimiting example, a third switch 15 for selecting the column read Xi (also noted sw3) is disposed between the terminals B, C of the capacitors 2 Cref, 5 Csig. In addition, a fourth switch 16 (also noted sw4) controlled by the SHS signal is inserted at point D between the capacity 2 Csig and the ground, and in parallel with this fourth switch 16, a fifth switch 17

(also noted sw5), controlled by a column selection signal Xi, is introduced between point D and a signal output bus 18.

In an example described here for purely indicative and in no way limitative, the circuit is produced by a process known as SLP / DLM in 0.7 CM CMOS technology.

The circuit is very sensitive to the influence of the capacity of the output bus 18, if a voltage amplifier is used for the output amplifier 14.

Indeed, the switches used for the realization of the circuit are MOS transistors of channel-N type. In this case, CMOS technology does not allow the substrate of channel-N MOS transistors to be connected to their source. As a result, the substrates of the transistors 17 sw5 are connected to ground, which creates a non-zero capacity C _BS (source substrate).

The total stray capacitance Cp of the columns is represented in FIG. 3 by a stray capacitance 19, illustrated inserted upstream of the output amplifier 14. The value of this stray capacitance 19 Cp being able to reach several picofarads, it is likely to reduce the circuit performance.

To solve this problem, a charge amplifier, as illustrated in FIG. 4, serves as an output buffer / amplifier 14.

In this case, the output bus 18 is maintained at a reference voltage Vbus. As a result, the stray capacitance 19 Cp is always charged at the voltage Vbus, whatever the value of the stray capacitance Cp. A capacity C 20 is mounted in parallel with an output amplifier 22, and with a switch 21 controlled by an RST signal. To have a gain greater than unity, the value of the capacitance C is chosen such that C <Cs / 2. Note that in this arrangement, the circuit is compatible with existing imagers with regard to the control signals used: SHR, SHS, X1 ... XM, RST etc.

The operating mode of the circuit is then substantially similar to that of a conventional CDS correlated double sampling type imager. It is illustrated by FIG. 5. According to FIG. 3, in each column, for a pixel whose signal is selected on the input bus at point A, the reference value Vref is sampled first by closing the switches 4 controlled by the signal SHR and stored in capacity 2 Cref of each corresponding column. After this operation, the switches 4 are open. Then the value of the signal Vsig is sampled, for all these pixels, and stored in the capacity 5 Csig of each corresponding column, by closing the switches 6 and 16 controlled by the signal SHS. This is illustrated by the fourth line in Figure 5.

Then, for column 1 (the column selection signal X1 then being the only active, all the other column selection signals Xi being inactive), the switches 15 and 17 controlled by the signal X1 being closed, the difference Vref - Vsig corresponding to the selected pixel is sent in a single output (by the simultaneous discharge of Cref and Csig storing the reference levels Vref and light signal Vsig respectively) in the output bus 18 and amplified by the amplifier 22.

In the case of using the amplifier of FIG. 4, the charge from the 2 Cref and 5 Csig capacities is transferred to the 20 C capacity. Reading continues column by column from the first to the M-th, by modifying the values of the column selection signals read X1, ... Xi, ... XM. This is illustrated by the fifth line in Figure 5.

The 20 C capacity is short-circuited before each transfer by closing the switch 21 controlled by the RST signal. This is illustrated by the sixth line in Figure 5.

We then have for the output voltage Vout the value: Vout = (-Cs / 2C) * (Vref- Vsig) +2 ^* Vbus

We note that the choice of C (<Cs / 2) makes it possible to obtain a gain higher e 1.

This is illustrated by the seventh line in FIG. 5. We therefore have for each line (2 + 2 x M) measurement steps, and for an imager of dimensions N rows and M columns N x (2 + 2 x M) steps of reading.

Thus in an original manner according to the invention, the capacitors Cref and Csig are first charged independently for the signals Vreg and Vsig respectively, then said consensors are then put in series so as to obtain a signal representative of the difference (Vref-Vsig ). The device according to the invention then provides several advantages.

In particular, the proposed CDS correlated double sampling circuit is simple. It only has two capacities (Cref, Csig) and five switches (sw1 to sw5) per column, a single output, and a single output buffer / amplifier block 14, common to all the columns. As there is only one buffer / amplifier common to all the columns, no column FPN spatial noise is created in the previous devices by the P-channel MOS trackers

In addition, the elimination of the PMOS type column trackers makes it possible to significantly reduce the area occupied by the components and therefore of the matrix image sensor.

The response time and the gain of the circuit are not very sensitive to the number of columns of the imager, and it is therefore particularly suitable for large imagers. Clearly, the larger the size of the matrix sensor, the more device of the invention provides a significant advantage. Only one sample is required to read each signal from each pixel, which compares very favorably to the prior DDS technique, which requires an output subtractor.

The response time is therefore essentially limited by the output amplifier. Since this is unique, it can be chosen to be optimized to provide good performance, without unduly penalizing the manufacturing cost of the circuit. We finally obtained here both a reduction of the spatial noise FPN (asymmetry of the reading chains), and of the temporal noise of measurement.

The invention also applies to circuits for reading matrix sensors of all kinds, and not only to matrix imagers with active pixels (APS sensors), which widens its field of use.

In variants not shown, high value capacities, or different switch structures ("dummy switches", transmission doors, etc.) can be used to further reduce FPN noise.

The amplifier shown in FIG. 4 can be replaced by other charge amplifiers, which fix the voltage of bus 18.

In another variant, a non-inverting configuration of the circuit can be obtained by permuting the sampling signals SHS and SHR (FIG. 3).

The scope of the present invention is not limited to the details of the embodiments above considered by way of example, but on the contrary extends to modifications within the reach of ordinary skill in the art, in the context of claims below.

Claims

1. Electronic pixel reading device of a matrix image sensor, in particular for a CMOS type active pixel sensor, said sensor comprising N rows and M columns of active pixels (1), characterized in that it comprises signal acquisition means, adapted to send directly, for each pixel (1) of each column, to an output bus (18) a signal representative of the potential difference between a reference signal Vref and a light level signal Vsig of this pixel (1), the signal acquisition means being constituted by switches and capacitors.

2. Device according to claim 1, characterized in that the signal acquisition means comprise for each column at the output A of the column bus:

- a first switch (4) mounted between the output point A and a point B, controlled by a SHR signal, making it possible to charge a capacity (2) Cref mounted between the point B and the ground,

- a second switch (6) mounted between point A and a point C, controlled by a SHS signal, making it possible to charge a floating capacity (5) Csig mounted between point C and a point D, - a third switch (15) mounted between points B and C, controlled by a signal Xi for selecting the column read, disposed between the terminals of the capacitors (2) Cref, (5) Csig,

- a fourth switch (16), controlled by the SHS signal, inserted downstream between the capacity (5) Csig (point D) and the earth, - and a fifth switch (17), controlled by the selection signal (Xi) column read, mounted downstream between the floating capacitance Csig (point D) and a signal output bus (18).

3. Device according to claim 2, characterized in that the capacities (2) Cref and (5) Csig are chosen with equal value Cs.

4. Device according to any one of claims 1 to 3, characterized in that it comprises a single output buffer / amplifier (14), common to all columns of the sensor.

5. Device according to any one of claims 1 to 4, characterized in that:

- the output bus (18) is maintained at a reference voltage Vbus, - a capacitor C (20) is mounted in parallel with an output amplifier (22), and with a switch (21) controlled by the signal RST.

6. Device according to any one of claims 1 to 5, characterized in that the switches used for the realization of the circuit are MOS transistors of the N-channel type.

7. Method for reading pixels from a matrix image sensor, in particular for a CMOS type active pixel sensor, said sensor comprising N rows and M columns of active pixels, characterized in that it comprises at least the following steps :

1 / in each column, for the pixel whose signal is selected on an input bus (18), a reference value Vref is sampled first and stored in a capacity (2) Cref of each corresponding column,

2 / then a value of the signal Vsig is sampled, for each same pixel, and stored in a floating capacity (5) Csig of each corresponding column,

3 / then, column by column, Cref and Csig are connected in series using a switch (15) so as to obtain, by their simultaneous discharge on the output bus (18) via a switch (17), a signal representative of the difference (Vref-Vsig) which is then amplified in a buffer / amplifier (14).