JP2005348040A - Amplification type imaging apparatus and imaging system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a solid state imaging apparatus which enables high speed pixel average reading operation and corresponds to both of progressive reading and interlace reading. <P>SOLUTION: In the solid state imaging apparatus in which a plurality of pixels having photoelectric conversion parts are arranged, two systems of signal output lines provided to one column of pixel groups are connected to one end of each of input capacitance 412o and input capacitance 412e of an operational amplifier 211, respectively, the other ends of the capacitance 412o and the capacitance 412e are short-circuited and connected to the input terminal of the operational amplifier 211. The pixel signals are reversely amplified with ratio between the input capacitance 412o and the input capacitance 412e and feedback capacitance 213 of an amplifier circuit 410. At the time of an all column reading operation, a signal from one signal output line 406o is reversely amplified by inputting it in the input capacitance 412o and the input capacitance 412e. At the time of a pixel average reading operation, signals from the respective signal output lines 406o, 406e are inputted in each of the input capacitance 412o and the input capacitance 412e, and equalization is performed in the input terminal of the operational amplifier 211. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a solid-state imaging device and an imaging system in which a plurality of pixels each including a photoelectric conversion unit are arranged, and particularly suitable for an imaging device and an imaging system that support both progressive readout and interlace readout. It is.

  In recent years, commercial and home video cameras using solid-state imaging devices have become widespread. These conventional commercial and home video cameras are also referred to as interlaced readout (field readout or interlaced scanning readout) in which horizontal signal lines are scanned every other line in order to be compatible with television systems (for example, NTSC system and PAL system). Was adopted). On the other hand, recently, image input cameras for personal computers have been actively developed, but this type of camera horizontal scanning method is used to obtain high-resolution still images and to facilitate output to computer displays. From the viewpoint, simultaneous readout of all pixels is adopted. This method is also called non-interlaced reading or progressive reading. A solid-state imaging device used in a camera that reads all pixels simultaneously is required to read signal charges of all pixels independently.

  First, an outline of a solid-state imaging device called a general amplification type MOS sensor will be described. An amplifying MOS sensor has a plurality of unit pixels arranged one-dimensionally or two-dimensionally, and the unit pixels are used to transfer signal charges generated from photoelectric conversion elements formed on a semiconductor substrate. It has a gate, a floating diffusion for converting signal charges into voltage, and a source follower input MOS transistor for signal amplification. An example of an equivalent circuit diagram of a unit pixel of the MOS type imaging device is shown in FIG.

  In FIG. 9, the photoelectric conversion element 101 is connected to the gate of the pixel source follower input MOS transistor 102 via the transfer MOS transistor 103, and the source of the pixel source follower input MOS transistor is connected to the pixel output line 106 via the selection MOS transistor 105. Connected with. Further, a reset MOS transistor 104 that resets the gate of the pixel source follower input MOS transistor 102 to a predetermined potential is provided.

  FIG. 10 is a circuit diagram showing a configuration of a MOS type imaging apparatus. The operation of the imaging apparatus will be described with reference to the equivalent circuit diagram of FIG. 9, the configuration diagram of the imaging apparatus of FIG. 10, and the timing chart of FIG.

  In FIG. 10, unit pixels 208o and 208e are shown in the equivalent circuit diagram of FIG. Further, in FIG. 10, the connection between the unit pixel and GND is omitted. The unit pixels 208o and 208e indicate two pixels in the pixel column of the pixel unit 207 in which the pixels are arranged in a two-dimensional shape, and a row of pixel rows (n rows) is selected by the vertical scanning circuit 220. First, the reset signal φRES (n) becomes low, and the reset MOS transistor 104 serving as a reset switch is turned off. Next, when the selection signal φSEL (n) becomes high and the selection MOS transistor 105 serving as a selection switch is turned on, the source of the amplification MOS transistor 102 becomes conductive with the signal output line 106 (206), and the selected pixel is determined. A source follower circuit is formed by the current load 209, and an output corresponding to the pixel reset state is read out to the signal output line 206. In this example, an amplifier circuit 210 is configured for each column (hereinafter referred to as a column amplifier). The column amplifier is composed of, for example, an operational amplifier 211 using a differential amplifier circuit, an input capacitor 212, a feedback capacitor 213, and a clamp control switch 214. In this example, the column amplifier is inverted at a ratio of the input capacitor 212 and the feedback capacitor 213. Gain is obtained. When the output corresponding to the pixel reset state is read to the signal output line 206, the signal φCLMP becomes high, the inverting input terminal and the output terminal of the column amplifier are short-circuited, and the output corresponding to the pixel reset state is clamped to the predetermined voltage Vref. Is done. At this time, the output of the column amplifier is read as N output corresponding to the reset state of the pixel, and is read out to the line memory 216n via the column amplifier output transfer switch 215n by setting the signal φTN to high. Thereafter, the transfer MOS transistor 103 serving as a transfer switch is turned on for a certain period by the transfer pulse φTX (n), and a voltage corresponding to the voltage change state due to the optical signal generated in the photoelectric conversion element 101 is transferred to the gate of the amplification MOS transistor 102. And read out to the signal output line 106 (206). The signal φCLMP is low, and the column amplifier generates an S output in which a voltage component obtained by applying an inversion gain to the voltage change component of the signal output line due to the optical signal is superimposed on the N output. Since the output corresponding to the reset state of the pixel is read out to the signal output line 206, the amount of potential change on the signal output line 206 side of the input capacitor 212 is the output component (reset variation from the signal) corresponding to the pixel reset state. (Component) is removed.

  Subsequently, the signal φTS goes high, and the S output corresponding to the optical signal is read out to the line memory 216s via the column amplifier output transfer switch 215s. Next, the N signal and S signal of the column selected by the horizontal scanning circuit 219 are sequentially read out, and the difference between the correlated N signal and S signal is executed by the difference amplifier 218, thereby outputting the optical response. Is obtained.

As described in Patent Document 1, in progressive readout, signal charges of even-numbered and odd-numbered pixels are read independently by performing separation between adjacent pixels in the vertical CCD, and two adjacent pixels are read by the vertical CCD. Interlaced readout is possible by mixing signal charges
JP 2000-111971 A

  The MOS type imaging device described above is generally superior to the CCD in terms of single power supply driving and low power consumption. On the other hand, regarding the readout operation, the CCD is compatible with both progressive readout and interlaced readout, whereas the MOS type imaging device is disadvantageous in that interlace readout is difficult. This point will be described below. In the CCD, the signal charge generated by photoelectric conversion in the pixel is transferred to the vertical CCD in the state of charge. As described in the above-mentioned Patent Document 1, in progressive reading, signal charges of pixels in even and odd rows are read independently by separating adjacent pixels in the vertical CCD, and signals of two adjacent pixels are read by the vertical CCD. Interlaced reading can be performed by mixing charges.

  However, as described above, in the case of a MOS type imaging device, since the signal charge is converted into a voltage after the source follower of the pixel, addition or averaging is performed with one signal output line. It is difficult. From the result of reading all rows, for example, addition or averaging can be performed using analog memory inside the chip or memory means outside the chip. However, in this case, the amount of data is half that of all-line reading, but the reading time is equal to that of all-line reading, so that interlaced reading that requires a frame rate twice that of progressive reading is enabled. At the same time, it conflicts with the demand for higher speed and higher frame rate.

  An object of the present invention is to provide an amplification type imaging apparatus that is compatible with progressive reading and interlaced reading, which has been difficult in the past.

The present invention has been made to solve the above problems, and the solid-state imaging device of the present invention is a solid-state imaging device in which a plurality of pixels including a photoelectric conversion unit are arranged,
Having a plurality of signal output lines for outputting signals from different pixels,
Each of the plurality of signal output lines is connected to an electrode at one end of a plurality of capacitors, and an electrode at the other end of the plurality of capacitors is short-circuited.

In the solid-state imaging device of the present invention, the pixels are arranged one-dimensionally or two-dimensionally,
It is preferable that a plurality of pixels belonging to one pixel column are distributed and connected to the plurality of signal output lines. In the solid-state imaging device of the present invention, the pixels are two-dimensionally arranged,
Preferably, a plurality of signal output lines are provided for a plurality of pixel columns, and a plurality of pixels belonging to one pixel row are respectively connected to the plurality of signal output lines.

  In the present invention, since average pixels can be read and averaged simultaneously, high-speed pixel average reading operation can be performed. In addition, it is possible to provide a solid-state imaging device that supports both progressive reading and interlaced reading.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

(Embodiment 1)
FIG. 1 is a circuit diagram showing the configuration of the first embodiment of the solid-state imaging device of the present invention. In FIG. 1, the same components as those in FIG. The difference between the amplifier circuit 210 of FIG. 10 and the amplifier circuit 410 of this embodiment is that two capacitive elements 412o and 412e are connected to the inverting input terminal (−) of the operational amplifier 211.

  The configuration of the unit pixel is the same as that shown in FIG. In this embodiment, there are two signal output lines 406o and 406e per column. Among the pixels belonging to the pixel array of one column, the odd-numbered pixels 408o are the signal output lines 406o, and the even-numbered pixels 408e are the signals. Each is connected to an output line 406e. The odd-numbered pixel columns are scanned by the vertical scanning circuit 420o, and the even-numbered pixel columns are scanned by the vertical scanning circuit 420e. The unit pixels 408o and 408e indicate two pixels in the pixel column of the pixel portion 407 in which the pixels are two-dimensionally arranged. The vertical scanning circuit 420o includes a certain pixel row including the pixel 408o (n rows). ) Is first selected, the reset signal φRES (n) goes low, and the reset MOS transistor 104 serving as a reset switch is turned off. Next, when the selection signal φSEL (n) becomes high and the selection MOS transistor 105 serving as a selection switch is turned on, the source of the amplification MOS transistor 102 is electrically connected to the signal output line 406o, and the selected pixel 408o and the constant current load 409o are connected. Thus, a source follower circuit is formed, and an output corresponding to the pixel reset state is read out to the signal output line 406o. Similarly, when a row of pixel rows including the pixel 408e (referred to as n rows) is selected by the vertical scanning circuit 420e, first, the reset signal φRES (n) goes low, and the reset MOS transistor 104 serving as a reset switch Turn off. Next, when the selection signal φSEL (n) becomes high and the selection MOS transistor 105 serving as a selection switch is turned on, the source of the amplification MOS transistor 102 becomes conductive with the signal output line 406e, and the selected pixel 408e and the constant current load 409e. Thus, a source follower circuit is formed, and an output corresponding to the pixel reset state is read out to the signal output line 406e.

  In a row of a pixel row including the pixel 408 o, the transfer MOS transistor 103 serving as a transfer switch is turned on for a certain period by the transfer pulse φTX (n) from the vertical scanning circuit 420 o, and the voltage due to the optical signal generated in the photoelectric conversion element 101 The voltage corresponding to the change state is transferred to the gate of the amplification MOS transistor 102 and read out to the signal output line 106o. Similarly, in a row of a pixel row including the pixel 408e, the transfer MOS transistor 103 serving as a transfer switch is turned on for a certain period by the transfer pulse φTX (n) from the vertical scanning circuit 420e, and the optical signal generated in the photoelectric conversion element 101 The voltage corresponding to the voltage change state due to is transferred to the gate of the amplification MOS transistor 102 and read out to the signal output line 106e.

  The signal output lines 406o and 406e are connected to the capacitive elements 412o and 412e via the MOS switches 421o and 421e, respectively, and the electrodes on the opposite side of the electrodes connected to the signal output lines of the capacitive elements 412o and 412e are short-circuited. The shorted electrode of the capacitive element is connected to the inverting input terminal (+) of the operational amplifier 411. The capacitive element 412o and the signal output line 406o, and the capacitive element 412e and the signal output line 406e can be switched between electrical connection and non-connection by the MOS switches 421o and 421e, respectively, and the signal output lines of the capacitive elements 412o and 412e can be switched. The electrodes on the 406o, 406e side can be switched between electrical connection and non-connection between the electrodes by the MOS switch 422.

  The entire row read operation in this embodiment will be described with reference to the timing chart of FIG. In the present embodiment, an odd-numbered vertical scanning circuit 420o and an even-numbered vertical scanning circuit 420e are used. The operation of the vertical scanning circuit is omitted. During the all-row reading operation, the even and odd rows are alternately selected by the vertical scanning circuits 420o and 420e sequentially, and the optical signals at the respective pixels are read out. In FIG. 2, the n-th line corresponds to the odd-numbered line, and the (n + 1) -th line corresponds to the even-numbered line. The pixel operation in the selected row is the same as that described in the timing chart of FIG. The reading operation of the N signal and the S signal is the same as that described with reference to FIGS. When all rows are read, φOE is high and the MOS switch 422 is in an on state, and the pixel output read to the odd-numbered signal output line 406o is high when φEVEN is high and the MOS switch 421e is on, and φODD is low and the MOS switch By turning 421o off, the pixel output that is input to the two capacitors 412o and 412e, while the pixel output read to the even-numbered signal output line 406e is low, φEVEN is low, MOS switch 421e is off, and φODD is high. By turning on the MOS switch 421o, the input to the two capacitors 412o and 412e increases the gain at the column amplifier as compared with the case where only one capacitor is used, thereby increasing the S / N ratio. Improvements can be made.

  The vertical addition read operation in this embodiment will be described with reference to the timing chart of FIG. In this operation, the odd-numbered and even-numbered rows are simultaneously selected by the odd-numbered vertical scanning circuit 420o and the even-numbered vertical scanning circuit 420e, and a noise signal or an optical signal in each pixel is output to each pixel output line 406o, It is input to the capacitors 412o and 412e connected to 406e. During the vertical addition read operation, φOE is low and φEVEN and φODD are high, and the optical signals input to the capacitors 412o and 412e are averaged at the inverting input terminal (−) of the column amplifier. This is a vertical addition read operation, and the field read time is half of the read of all rows. By alternately reading out the odd-numbered field and the even-numbered field, the interlace operation can be realized. In this embodiment, the reading of the odd-numbered field and the even-numbered field can be selected according to the scanning start timing of the vertical scanning circuit.

  The pixel configuration and readout circuit configuration shown in this embodiment are merely examples of the present invention, and can be applied to other pixel configurations and readout configurations.

In the present embodiment, an odd-row signal output line and an even-row signal output line are provided for a pixel group in one column, and all row read operations are performed by sequentially reading signals from the respective output lines, and each signal output The vertical pixel average readout operation is performed by averaging the signal from the line with the input capacitance of the column amplifier. As a result, it is possible to provide an amplification type imaging apparatus that supports progressive reading and interlaced reading. The gain obtained by the column amplifier is determined by the ratio between the input capacitance and the feedback capacitance, and the signal from either the odd-numbered row or the even-numbered row is used as the input capacitance for both the odd-numbered and even-numbered rows during the all-row read operation. Input substantially increases the input capacitance, and a high gain similar to that in the vertical pixel average readout operation can be obtained.
In this embodiment, the solid-state imaging device can be provided on the same semiconductor substrate, but the difference amplifier 218 may be provided outside the substrate so that noise generated by the difference amplifier 218 does not affect other circuit members.

  In the present embodiment, an odd-row signal output line and an even-row signal output line are provided for a pixel group in one column, and all row read operations are performed by sequentially reading signals from the respective output lines, and each signal output The embodiment in the case where the vertical pixel average readout operation is performed by averaging the signal from the line with the input capacitance of the column amplifier has been described, but a plurality of signal output lines are provided for a plurality of pixel columns, and one pixel row Are connected to a plurality of signal output lines (for example, two signal output lines are provided for two pixel columns) to perform an all-row readout operation and a horizontal pixel average readout operation ( For example, the present invention can also be applied to a case where two signal output lines are provided for two pixel columns to perform an all-row reading operation and a horizontal pixel average reading operation.

(Embodiment 2)
The pixel shown in FIG. 9 used in the present embodiment is called a CMOS sensor. However, the pixel is not particularly limited to a CMOS sensor, and is not limited to a CMOS sensor. Also, LBCAST (Lateral Buried Charge Accumulator and Sensing Transistor Array) is applicable. In particular, BCAST and LBCAST can be realized without substantial change by replacing the amplification MOS transistor with a JFET transistor. In addition, a sensor of a type that guides signal charges accumulated in the photoelectric conversion unit to a control electrode of a transistor provided in the pixel and outputs an amplified signal from the main electrode can be used for the pixel of this embodiment. SIT type image sensor using SIT as an amplifying transistor (A. Yusa, J. Nishizawa et al., “SIT image sensor: Design consideration and characteristics,” IEEE trans. Vol. ED-33, pp.735-742, June 1986), BASIS using bipolar transistors (N. Tanaka et al., “A 310K pixel bipolar imager (BASIS),” IEEE Trans. Electron Devices, vol. 35, pp. 646-652, may 1990), CMD (Nakamura et al. “Gate Storage Type MOS Phototransistor Image Sensor”, TV Society Journal, 41, 11, pp.1075-1082 Nov., 1987) using JFET with depleted control electrode.

  In this embodiment, an example of a pixel having another structure to which the present invention can be applied will be described. The unit pixel shown in FIG. 4 includes a transfer MOS transistor 708 as a transfer gate for transferring a signal charge generated from a photoelectric conversion element 701 formed on a semiconductor substrate, a floating diffusion part for converting the signal charge into a voltage, a signal A source follower input MOS transistor 702 for amplification, a reset JFET 723 for resetting the floating diffusion portion, a selection control line 724 for selecting a pixel, and a selection capacitor 725 are provided. Pixel selection is performed by raising the potential of the selection control line 724. When the potential of the selection control line rises, the potential of the floating diffusion portion rises due to capacitive coupling between the selection control line and the floating diffusion portion. As a result, the connection between the power source by the JFET and the floating diffusion portion is disconnected, and the floating diffusion portion enters a floating state. The subsequent output in the pixel reset state and the output in the voltage change state due to the optical signal generated by the photoelectric conversion element are the same as those in the pixel shown in FIG. For example, the present invention can also be applied to an imaging device configured by the unit pixels described above.

(Embodiment 3)
In the present invention, the all-pixel readout operation and the vertical pixel average readout operation are controlled by MOS transistors 421o, 421e, and 422 serving as control switches driven by the vertical drive circuit and φODD, φEVEN, and φOE. In order to reduce the number of input pads, the following configuration is possible. That is, by generating the signal φOE by the logic circuit shown in FIG. 5, when either one of the signals φODD and φEVEN is in the high state, the read operation is for all rows, and φOE is in the high state, and both the signals φODD and φEVEN are In the high state, the vertical average read operation is performed, and φOE can be controlled to be in the low state. In FIG. 5, the signal φEVEN is input to the first NOT circuit 801 and the second NAND circuit 804, and the signal φODD is input to the second NOT circuit 802 and the first NAND circuit 803. The output of the first NOT circuit 801 is input to the first NAND circuit 803, and the output of the second NOT circuit 802 is input to the second NAND circuit 804. The outputs of the first and second NAND circuits 803 and 804 are connected to the third NAND circuit 805, and the output of the third NAND circuit 805 becomes the signal φOE.

(Embodiment 4)
FIG. 6 is a circuit diagram showing a partial configuration of the solid-state imaging device according to the fourth embodiment of the present invention. The same components as those in FIG. 1 are denoted by the same reference numerals, and description thereof is omitted. In the present embodiment, a memory unit that holds an averaged signal is provided. Although only one memory cell is shown here, it is provided corresponding to the number of pixels. Here, since two pixels are averaged, the number of memory cells may be half of the number of pixels.

  In FIG. 6, the signal amplified by the amplifier circuit 410 is written into the memory cell 501. The memory cell 501 includes an amplifying transistor 502, a memory selection transistor 503, a writing transistor 500, and a memory cell capacitor 504. The current supply transistor 505 supplies current so that the amplification transistor 502 functions as a source follower. In this embodiment, an amplification type frame memory is used, but a DRAM type memory including a write (reading) transistor 500 and a memory cell capacitor 504 may be used. By using an amplifying memory, in reading from the memory to the storage capacitor, the signal voltage is not lowered due to the amplifying action of the memory cell 501.

  Signal reading from the memory cell 501 is performed by turning on the memory selection transistor 503. The output of the selected memory cell is sampled by the line memory 216s by turning on the transfer switch 215S by the pulse φTS. Next, the inverting input terminal and the output terminal of the operational amplifier 211 are short-circuited by turning on the clamp control switch 214, and the offset of the operational amplifier 211 is written into the memory cell 501. Reading and sampling the offset written in the memory cell is the same as reading and sampling the signal written in the memory cell. Sampling of the offset output from the memory cell to the line memory 216n is performed by applying a pulse φTN to the transfer switch 215n. The voltage on the line memory 216 s includes the offset of the amplification transistor 502 in addition to the amplified pixel signal and the offset of the operational amplifier 211. On the other hand, the voltage on the line memory 216n includes the offset of the amplification transistor 502 in addition to the offset of the operational amplifier 211. Next, the N signal and S signal of the column selected by the horizontal scanning circuit 219 are sequentially read out, and the difference between the correlated N signal and S signal is executed by the difference amplifier 218, thereby outputting the optical response. Is obtained.

  Based on FIG. 7, an embodiment when the solid-state imaging device according to the present invention is applied to a still camera capable of moving images will be described in detail.

  FIG. 7 is a block diagram showing a case where the solid-state imaging device according to the present invention is applied to a “still camera” for moving images.

  In FIG. 7, reference numeral 1101 denotes a barrier that serves as a lens protect and a main switch, 1102 denotes a lens that forms an optical image of a subject on an image sensor (solid-state imaging device) 1104, and 1103 denotes a variable amount of light passing through the lens 1102. Aperture, 1104 is an image sensor for capturing the subject imaged by the lens 1102 as an image signal, 1106 is an A / D converter that performs analog / digital conversion of an image signal output from the image sensor 1104, and 1107 is an A / D converter. A signal processing unit 1108 performs various corrections on the image data output from the D converter 1106 and compresses the data. An image sensor 1104, an image signal processing circuit 1105, an A / D converter 1106, and a signal processing unit 1107 A timing generator for outputting various timing signals, 11109 is various operations and still video An overall control / arithmetic unit for controlling the entire camera, 1110 is a memory unit for temporarily storing image data, 1111 is an interface unit for recording or reading on a recording medium, and 1112 is a unit for recording or reading image data. A removable recording medium such as a semiconductor memory for performing 1113 is an interface unit for communicating with an external computer or the like.

Next, the operation of the still video camera at the time of shooting in the above configuration will be described.
When the barrier 1101 is opened, the main power supply is turned on, then the control system power supply is turned on, and the power supply of the imaging system circuit such as the A / D converter 1106 is turned on.
Then, in order to control the exposure amount, the overall control / arithmetic unit 1109 opens the diaphragm 1103, and the signal output from the image sensor 1104 is converted by the A / D converter 1106 and then input to the signal processing unit 1107. Is done. Based on the data, exposure calculation is performed by the overall control / calculation unit 1109.

  The brightness is determined based on the result of the photometry, and the overall control / calculation unit 1109 controls the aperture according to the result.

  Next, based on the signal output from the image sensor 1104, a high-frequency component is extracted and the distance to the subject is calculated by the overall control / calculation unit 1109. Thereafter, the lens is driven to determine whether or not it is in focus. When it is determined that the lens is not in focus, the lens is driven again to perform distance measurement. Then, after the in-focus state is confirmed, the main exposure starts.

  When the exposure ends, the image signal output from the image sensor 1104 is A / D converted by the A / D converter 1106, passes through the signal processing unit 1107, and is written in the memory unit 1110 by the overall control / calculation unit 1109.

  Thereafter, the data stored in the memory unit 1110 is recorded on a removable recording medium 1112 such as a semiconductor memory through the recording medium control I / F unit 1111 under the control of the overall control / arithmetic unit 1109.

  Further, the image may be processed by directly inputting to a computer or the like through the external I / F unit 1113.

  Further, based on FIG. 8, an example in which the solid-state imaging device of the present invention is applied to a video camera (imaging system) will be described in detail.

  FIG. 8 is a block diagram showing a case where the solid-state imaging device of the present invention is applied to a video camera. Reference numeral 1201 denotes a focus lens 1201A for performing focus adjustment by a photographing lens, a zoom lens 1201B for performing a zoom operation, and an imaging lens. A lens 1201C is provided.

  1202 is a diaphragm, 1203 is a solid-state imaging device (solid-state imaging device) that photoelectrically converts a subject image formed on the imaging surface and converts it into an electrical imaging signal, and 1204 is an imaging signal output from the solid-state imaging device 1203. A sample hold circuit (S / H circuit) that samples and holds and further amplifies the level, and outputs a video signal.

  A process circuit 1205 performs predetermined processing such as gamma correction, color separation, and blanking processing on the video signal output from the sample hold circuit 1204, and outputs a luminance signal Y and a chroma signal C. The chroma signal C output from the process circuit 1205 is subjected to white balance and color balance correction by a color signal correction circuit 1221 and is output as color difference signals RY and BY.

  In addition, the luminance signal Y output from the process circuit 1205 and the color difference signals RY and BY output from the color signal correction circuit 1221 are modulated by an encoder circuit (ENC circuit) 1224 and used as a standard television signal. Is output. Then, it is supplied to a monitor EVF such as a video recorder (not shown) or an electronic viewfinder.

  Next, reference numeral 1206 denotes an iris control circuit, which controls the iris driving circuit 1207 based on the video signal supplied from the sample hold circuit 1204 so that the aperture of the diaphragm 1202 is set so that the level of the video signal becomes a predetermined value. The ig meter is automatically controlled to control the amount. Reference numerals 1213 and 1214 denote different band-limited bandpass filters (BPF) for extracting high-frequency components necessary for performing focus detection from the video signal output from the sample and hold circuit 1204. Signals output from the first bandpass filter 1213 (BPF1) and the second bandpass filter 1214 (BPF2) are gated by the gate circuit 1215 and the focus gate frame signal, respectively, and the peak value is detected by the peak detection circuit 1216. Is detected and held, and input to the logic control circuit 1217.

This signal is called a focus voltage, and the focus is adjusted by this focus voltage.
Reference numeral 1218 denotes a focus encoder that detects the movement position of the focus lens 1201A, 1219 denotes a zoom encoder that detects the focal length of the zoom lens 1201B, and 1220 denotes an iris encoder that detects the opening amount of the diaphragm 1202. The detection values of these encoders are supplied to a logic control circuit 1217 that performs system control. The logic control circuit 1217 performs focus adjustment by detecting focus on the subject based on the video signal corresponding to the set focus detection area. That is, the peak value information of the high frequency component supplied from each of the bandpass filters 1213 and 1214 is taken in, and the focus driving circuit 1209 is driven to the focus motor 1210 to drive the focus lens 1201A to the position where the peak value of the high frequency component is maximized. Control signals such as a rotation direction, a rotation speed, and rotation / stop are supplied and controlled.

  The present invention is preferably used for a solid-state imaging device capable of performing a high-speed pixel average readout operation, particularly an imaging device compatible with both progressive readout and interlace readout.

It is a figure for demonstrating 1st embodiment of this invention. It is a timing chart for demonstrating the progressive read-out operation | movement of 1st embodiment of this invention. It is a timing chart for demonstrating the interlace read-out operation | movement of 1st embodiment of this invention. It is a figure for demonstrating 2nd embodiment of this invention. (Example of equivalent circuit diagram of unit pixel of MOS type imaging apparatus to which the present invention is applicable) It is a figure for demonstrating 3rd embodiment of this invention. It is a circuit diagram which shows a partial structure of the solid-state imaging device of 4th embodiment of this invention. It is a block diagram which shows the case where the solid-state imaging device concerning this invention is applied to the "still camera" corresponding to a moving image. It is a block diagram which shows the case where the solid-state imaging device concerning this invention is applied to a video camera. It is an equivalent circuit diagram of an example of a unit pixel of a MOS type imaging device. It is a figure for demonstrating operation | movement of the unit pixel of a MOS type imaging device. 5 is a timing chart for explaining the operation of a unit pixel of a MOS type imaging apparatus.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Photoelectric conversion element 2 Source follower input MOS transistor 3 Transfer MOS transistor 4 Reset MOS transistor 5 Select MOS transistor 6 Signal output line 6o Odd-row signal output line 6e Even-row signal output line 7 Pixel area 8 Unit pixel 8o Odd-row Unit pixel 8e Unit pixel in even row 9 Constant current load 10 Column amplifier 11 Operational amplifier 12 Column amplifier input capacitive element 12o Column amplifier input capacitive element in odd row 12e Column amplifier input capacitive element in even row 13 Column amplifier feedback capacitive element 14 columns Amplifier clamp control switch 15s Column amplifier output transfer switch 15n Column amplifier output transfer switch 16s Line memory 16n Line memory 17 Line memory transfer switch 18 Differential amplifier 19 Horizontal scanning circuit 20 Vertical scanning circuit 20o Odd row vertical scanning circuit 2 0e Vertical scanning circuit for even rows 21, 22 MOS switch 23 Reset JFET
24 selection control line 25 selection capacity

Claims (17)

A solid-state imaging device in which a plurality of pixels including a photoelectric conversion unit are arranged,
Having a plurality of signal output lines for outputting signals from different pixels,
Each of the plurality of signal output lines is connected to an electrode at one end of a plurality of capacitors, and an electrode at the other end of the plurality of capacitors is short-circuited. The pixels are arranged in one or two dimensions,
The solid-state imaging device according to claim 1, wherein a plurality of pixels belonging to one pixel column are distributed and connected to the plurality of signal output lines. The pixels are two-dimensionally arranged,
2. The solid-state imaging device according to claim 1, wherein a plurality of signal output lines are provided for a plurality of pixel columns, and a plurality of pixels belonging to one pixel row are connected to the plurality of signal output lines, respectively. . 4. The solid-state imaging device according to claim 1, wherein the short-circuited electrode at the other end of the plurality of capacitors is connected to an input terminal of an amplifier circuit. 5. The solid-state imaging device according to claim 1, further comprising a switch unit that switches between electrical connection and non-connection between electrodes at one end of the plurality of capacitors. The solid-state imaging device according to claim 1, wherein the signal output line is connected to the capacitor via a switch unit. The solid-state imaging device according to claim 2, wherein the signal output line is provided for each of an odd-numbered pixel row and an even-numbered pixel row. The first switch means for switching on and off the electrical connection and non-connection between the electrodes at one end of the plurality of capacitors, each of the plurality of signal output lines is turned on and off the electrical connection and non-connection, Connected to the capacitor via a second switch means switched by turning off;
Turning on the second switch means of the selected signal output line at the time of the all-row read operation, and turning on the first switch means;
8. The solid-state imaging device according to claim 2, wherein the second switch unit of each of the plurality of signal output lines is turned on and the first switch unit is turned off during the pixel average readout operation. Scanning means for sequentially selecting odd-numbered pixel rows and even-numbered pixel rows at the time of all-row reading operation and simultaneously selecting a set of odd-numbered pixel rows and even-numbered pixel rows at the time of pixel average reading operation The solid-state imaging device according to claim 7 or 8, characterized in that When the signal output line to which the odd-numbered pixel row or the even-numbered pixel row is connected by the second switch means is electrically connected to the capacitor, the odd-numbered pixel row and the even-numbered pixel row are respectively The two capacitors connected to the two signal output lines to be connected are electrically connected by the first switch means,
When two signal output lines to which the odd-numbered pixel rows and the even-numbered pixel rows are connected by the second switch means are electrically connected to the capacitors, the odd-numbered pixel rows and the even-numbered pixels are 10. The logic circuit according to claim 9, further comprising: a logic circuit that is electrically disconnected between the two capacitors connected to the two signal output lines connected to each other by the first switch means. Solid-state imaging device. The short-circuited electrode at the other end of the plurality of capacitors is connected to an amplifier, and the amplifier is a feedback amplifier, and has a coupling capacitor that capacitively couples the output terminal and the input terminal of the amplifier. The solid-state imaging device according to claim 1, wherein a gain is determined based on a ratio of a capacitance of the capacitor and the coupling capacitance. 12. The memory unit according to claim 1, further comprising: a memory unit that holds an output signal of the amplifier and includes memory cells arranged corresponding to at least some of the plurality of pixels. Solid-state imaging device. The solid-state imaging device according to claim 12, wherein the memory cell is an amplifying memory cell including at least a signal storage capacitor, a transistor for writing a signal, and a transistor for amplifying the signal. It is arranged for each column of the amplification type memory cells of the memory unit, and has circuit means for outputting an output offset between the amplifier and the amplification type memory cell and a signal from the amplification type memory cell. The solid-state imaging device according to claim 13. The circuit means stores a first storage capacitor for storing the output offset, a first transfer transistor for transferring the output offset to the first storage capacitor, and a first storage transistor for storing a signal from the amplification type memory cell. The solid-state imaging device according to claim 14, further comprising: a storage capacitor of 2 and a second transfer transistor that transfers a signal from the amplification type memory cell to the second storage capacitor. The solid-state imaging device according to claim 15, further comprising means for subtracting the output offset from the circuit means and the signal. The solid-state imaging device according to any one of claims 1 to 16, an optical system that forms an image of light on the solid-state imaging device, and signal processing that processes an output signal from the solid-state imaging device And an imaging system.