JPH0213514B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a clamp circuit, and in particular, it is an object of the present invention to provide a clamp circuit that can clamp the pedestal level of a television video signal (hereinafter referred to as a video signal) without damaging the burst signal. .

2. Description of the Related Art In a device for recording and reproducing a video signal, such as a general video tape recorder, the synchronization tip and maximum amplitude (white) level of the video signal are fixed to constant values in order to modulate the video signal.
And in order to fix the synchronization tip at a constant level,
A so-called synchronous tip clamp circuit is used.

On the other hand, in devices used for special purposes such as analog recording of video signals on floppy disks, where only the video portion of the video signal is recorded and not the synchronization signal, the synchronization tip described above is fixed. Instead of this method, it becomes necessary to fix the pedestal level to a constant level. A pedestal clamp circuit used for this purpose can be treated similarly to a synchronous tip clamp circuit by retarding the phase of the clamp reference signal of the synchronous clamp circuit to a position corresponding to the back porch. However, this pedestal clamp circuit cannot be applied to a signal having a color burst signal at a position corresponding to the back porch, such as an NTSC color video signal. This is because the color burst signal becomes distorted or disappears.

The present invention aims to solve the drawbacks of the conventional pedestal clamp circuit, that is, to provide a clamp circuit that can fix the pedestal level of the video signal to a constant DC level without damaging the color burst signal. It is.

The present invention will be explained based on the embodiment shown in FIG. Reference numeral 1 denotes an input terminal, into which a video signal with an unstable DC level is input. Amplifiers 2, 3, and 4 are used for buffering or amplifying the signal level. Reference numeral 5 denotes a synchronization separation circuit that separates and shapes the synchronization signal S in the video signal from the input terminal 1. 6 is a circuit that delays the synchronization signal S;
This creates a clamp pulse CP to clamp the pedestal of the back porch of the synchronization signal.
7 and 8 are so-called synchronous clamp circuits, which are clamped to the level of clamp reference signals A and B from clamp reference signal sources 9 and 10 only during the period when the synchronization signal S and clamp pulse CP are applied, respectively. It is configured. Capacitors 11 and 12 attached to each circuit 7 and 8 are used to suppress noise and stabilize the DC level. The clamp reference signal source 10 includes a DC voltage source 13 and a variable resistor 14, and applies a constant voltage to the clamp circuit 8. On the other hand, the clamp reference signal source 9 includes a video signal source clamped by the pedestal clamp circuit 8 and a circuit 15 that samples and holds a synchronization signal from this video signal source, and outputs a hold signal (clamp signal) to the clamp circuit 7 at a synchronization period. Reference signal) A is given. Reference numeral 16 denotes a filter for removing color burst signals from the input video signal. A trap circuit or a reduced pass filter is suitable. 17 and 18 are buffer amplifiers, and 19 is an output terminal.

Next, the operation of this circuit will be explained. The video signal from the input terminal 1 is applied to a sync separation circuit 5, a pedestal clamp circuit 8, and a sync tip clamp circuit 7. Input signal is pedestal clamp circuit 8
The signal passes through the buffer amplifier 3, the filter 16, and the buffer amplifier 4, and the burst signal and color signal components are removed and the impedance is reduced before being applied to the buffer amplifier 3. The pedestal level of this video signal is determined by the well-known pedestal clamp circuit 8.
By this operation, the potential _V1 determined by the clamp reference signal source 10 is set as shown in FIG. This pedestal clamped video signal is supplied to a buffer amplifier 18, the output of which is supplied to a sample hold circuit 15, where only the synchronizing signal portion is taken out. The potential V ₂₁ or V ₂₂ at the sync tip of the pedestal-clamped video signal is applied to the sync tip clamp circuit 7 as a clamp reference signal. On the other hand, the video signal passing through the amplifier 2 is supplied to a sync tip clamp circuit 7, and the tip of the sync signal H is clamped as shown in A and B of FIG.

Now, suppose that a video signal as shown in _FIG . The synchronization leading edge of the video signal is clamped at the reference potential _V21 (see the same figure). Since the synchronizing signal level ΔV ₁ is the same in FIG. 2, a pedestally clamped video signal is finally obtained at the output terminal 19 in terms of direct current. And the color burst signal of this output signal is not impaired. Even if video signals with different synchronization signal levels are supplied to the input terminal as shown in Figure 2B, the potential that fixes the pedestal remains unchanged, and the DC potential _V22 supplied to the synchronization tip clamp circuit is Since the voltage is equal to the potential of the synchronization tip, a pedestal-clamped video signal is outputted to the output terminal with no loss of the color burst signal as in the case described above.

In this way, the present invention uses the sync tip level of the video signal clamped at the pedestal portion by the pedestal clamp circuit as a clamp reference signal to drive the sync tip clamp circuit. The pedestal clamp can be useful.

[Brief explanation of drawings]

FIG. 1 is a block diagram of the clamp circuit of the present invention.
FIG. 2 is an explanatory diagram of the operation. 8... Pedestal clamp circuit, 15... Sample hold circuit, 7... Synchronous tip clamp circuit.

Claims (1)

[Claims] 1 A pedestal clamp circuit that uses a constant voltage from a DC voltage source as a clamp reference signal, a circuit that samples and holds the synchronization signal of the television video signal clamped by the pedestal clamp circuit, and a circuit that clamps the output from the sample and hold circuit. A clamp circuit comprising a synchronous tip clamp circuit used as a reference signal.