JPH021425B2 - - Google Patents

Description

[Detailed description of the invention] The present invention relates to a video signal clamp circuit.

When reproducing the DC component of a video signal, if the burst part is clamped with a fast-response keying clamp circuit, the burst phase will be reversed every 1H.
The pedestal fluctuated every 1H due to the output of the clamp circuit, and there were also drawbacks such as increased scratches on the burst section. In addition, in order to eliminate this drawback, if the response of the clamp circuit is slowed down, when the pedestal fluctuates greatly, the time required to clamp the pedestal to a constant level with the input of the clamp circuit becomes longer, which may adversely affect the downstream stage of the clamp circuit or cause a hum. It had the disadvantage of worsening the compression ratio.

An object of the present invention is to provide a video signal clamp circuit that can reduce damage caused by bursts without impairing response speed, and can suppress pedestal fluctuations every 1H to a small level.

In order to achieve the above object, the video signal clamp circuit according to the present invention is connected to a first keying clamp circuit, and the first keying clamp circuit has a lower clamping strength and a lower response speed than the first keying clamp circuit. After the first keying clamp circuit clamps the sync chip of the video signal, the second keying clamp circuit clamps the burst portion.

According to the above configuration, the first keying clamp circuit suppresses the fluctuation of the pedestal every 1H and removes the hum component, and the second keying clamp circuit eliminates the sync in the first keying clamp circuit without damaging the burst part. Pedestal fluctuations due to level differences are eliminated, and the object of the present invention is fully achieved.

Hereinafter, the present invention will be explained in more detail with reference to the drawings.

FIG. 1 is a diagram showing an embodiment of a video signal clamp circuit according to the present invention. This embodiment includes a video signal input terminal 1, a buffer amplifier 2, a capacitor,
A first keying clamp circuit 3 consisting of an electronic switch 11, a clamp potential setting power source 4, etc.; a second keying clamp circuit 5 consisting of a capacitor 10, a resistor 9, an electronic switch 12, a clamp potential setting power source 6, etc.; It is composed of an output terminal 7.

Figure 2 is a waveform diagram of each part of the above circuit, where A is an input video signal waveform diagram, B is a keying pulse generated by the first keying clamp circuit 3 when the electronic switch 1 is closed, and C is a second keying clamp circuit. Circuit 5 each shows a keying pulse generated by the closing of electronic switch 12. FIG. FIG. 3 shows a video signal having a part A without an image and a part B with an image, where A is the signal input to the first keying clamp circuit 3, B is the output 8 of the first keying clamp circuit 3, and C is the signal input to the first keying clamp circuit 3. The output waveforms of the second keying clamp circuit 5 are shown. The first keying clamp circuit 3 is connected to the electronic switch 1
1, a keying pulse is generated at the timing shown in FIG. 2B, and the sync chip 1 shown in FIG. 2A is clamped. The clamping strength is increased compared to the second keying clamp circuit. In this first keying clamp circuit 3, the level of the sync chip becomes constant as shown in FIG. 3B. The second keying clamp circuit 5 clamps the burst portion A-2 of the video signal shown in FIG. 2A at the timing shown in FIG. 2C. This clamping of the burst section E-2 eliminates pedestal level fluctuations due to differences in sync levels in the first keying clamp circuit 3.
This clamp circuit 5 is a DC regeneration capacitor 10
is increased, and the clamping strength is weakened by the resistor 9, and at the same time, the leakage of the clamp pulse to the burst portion is reduced. Therefore, although the response to the difference in the sync level is slow, it is smaller than the variation in the pedestal of the input signal, so even if the response time of the clamp circuit 5 is slow, it will not adversely affect the subsequent circuits.

Note that a, b, and c shown in FIG. 3C show pedestal level fluctuations due to the difference in the sync level in the case where the second keying clamp circuit is not provided.

As explained above in detail, the present invention eliminates fluctuations in the pedestal of the video signal using a sync chip clamp circuit with a strong clamping strength, and then eliminates fluctuations in the sync level using a clamp circuit with a weak clamping strength that clamps the burst portion. , can provide a fast-response clamp circuit.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an embodiment of a video signal clamp circuit according to the present invention, and FIGS. 2 and 3 are waveform diagrams of video signals, etc., for explaining the circuit operation of FIG. 1. 1... Video signal input terminal, 2... Buffer amplifier, 3... First keying clamp circuit, 4,
6... Power supply for clamp potential setting, 5... Second keying clamp circuit, 7... Output terminal of the clamp circuit, 8... Output of the first keying clamp circuit, 9... Resistor, 10... Capacitor, 11,
12...Electronic switch.

Claims (1)

[Claims] 1 a first keying clamp circuit;
and a second keying clamp circuit connected to the first keying clamp circuit, which has a weaker clamping strength and a lower response speed than the keying clamp circuit, and the first keying clamp circuit clamps the sync chip of the video signal. and a video signal clamp circuit configured to clamp the burst portion with a second keying clamp circuit.