JPH044674A - Synchronizing separator circuit and dc restoration circuit using the same - Google Patents

Abstract

PURPOSE:To operate the title circuit stably without malfunction even against a level fluctuation of an input video signal and a rapid DC fluctuation by deciding a synchronizing separation level from both a maximum value and a minimum value of the input video signal and comparing the obtained synchronization separation level with the input video signal level and separating synchronizing signal from the input video signal. CONSTITUTION:A video signal whose noise is eliminated by a low pass filter 3 is given to a maximum value latch circuit 4, in which a maximum value signal VMAX representing the maximum value of the video signal is detected and latched. Similarly, the video signal whose noise is eliminated by the low pass filter 3 is given to a minimum value latch circuit 5, in which a minimum value signal VMIN representing the minimum value of the video signal is detected and latched. The detected maximum value signal VMAX minimum value signal VMIN are inputted to a synchronizing separation level generating circuit 6, in which a synchronizing separation level VTH is generated. The synchronizing separation level VTH and the input video signal VL whose noise eliminated by the low pass filter 3 are compared to realize the synchronizing separator circuit with less malfunction due to fluctuation even when a level fluctuation of an input video signal or a rapid DC fluctuation takes place.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a synchronization separation circuit for video signals, and more particularly to a synchronization separation circuit used in television receivers, magnetic recording and reproducing devices, and the like.

[Conventional technology]

2. Description of the Related Art In video signal processing devices such as television receivers and magnetic recording and reproducing devices, a synchronization separation circuit is used to obtain a composite synchronization signal (hereinafter referred to as synchronization signal) from a video signal. An example of a conventional synchronous separation circuit is shown in FIG.

The moving object shown in FIG. 3 will be explained assuming that the input video signal has a negative polarity synchronization signal as shown in FIG. 2(a). The video signal inputted from the input terminal 8 is clamped by the sync tip clamp circuit 10 so that the potential at the sync tip becomes equal to the clamp potential C■. In the example of FIG. 3, the synchronization tip is clamped to be equal to ground potential. The clamped video signal is sent to the comparator 12
A voltage comparison is performed with a synchronization separation level signal VTH which is inputted to the synchronous isolation level signal VTH and connected from a power supply 11 having a predetermined fixed potential. At this time, if the potential of the VTR is set smaller than the synchronization signal amplitude of the input video signal as shown in FIG. You can get SP.

As described above, the conventional synchronous separation circuit clamps the input video signal to a predetermined potential and performs synchronous separation by comparing it with a fixed potential. In addition, related to this type of synchronous separation circuit, for example, Japanese Patent Application Laid-Open No. 58-187078
Publications No. 1, etc. can be cited.

[Problem to be solved by the invention]

The conventional synchronization separation circuit described above separates the synchronization signal by comparing the input video signal with a preset fixed potential synchronization separation level. Therefore, it is necessary to always fix the synchronization signal included in the input video signal to a predetermined potential. For this reason, in the conventional synchronous separation circuit, a clamp circuit is inserted as shown in FIG. However, since this clamp circuit is inserted before the sync separation circuit, an active clamp circuit that operates by a clamp pulse generated from a sync signal cannot be used. Therefore, when the content of the video signal suddenly changes from black to white or from white to black, a clamp error may occur as shown in FIG. 4(c). In this case, in the conventional synchronization separation circuit, since the synchronization separation level is fixed, there is a problem that malfunctions such as loss of the synchronization signal as shown in FIG. 4(d) occur.

Furthermore, when the level of the input video signal becomes lower than a predetermined level, the synchronization separation level reaches the video signal portion as shown in FIG. 4(e).
As shown in Figure 3, there was a problem in that synchronization separation was not performed correctly, resulting in malfunctions in which synchronization pulses were mixed in abnormally.

SUMMARY OF THE INVENTION An object of the present invention is to provide a synchronization separation circuit that operates stably without malfunctions even when the level of an input video signal fluctuates or suddenly changes in C.

[Means to solve the problem]

In order to achieve the above object, the synchronous separation circuit of the present invention has the following features:
It has means for detecting and holding the maximum value of the input video signal, means for detecting and holding the minimum value, and means for determining the synchronization separation level from both the maximum value and the minimum value obtained by the above two means, The configuration is such that the synchronization signal is separated by means of comparing the obtained synchronization separation level and the input video signal.

In addition, in order to stably separate a synchronization signal with higher precision without malfunction, a clamp pulse is generated from the synchronization signal separated by the first synchronization separation means shown above, and an active clamp circuit is operated by this clamp pulse. After clamping the input video signal using the method, the synchronization may be separated by comparison with a predetermined fixed synchronization separation level.

[Effect]

Let VMAX be the maximum value obtained by the means for detecting and holding the maximum value of the input video signal, and VMIN be the minimum value obtained by the means for detecting and holding the minimum value of the input video signal. The video signal including the synchronization signal input at this time has a level that is at least higher than VMIN and lower than VMAX. In addition, since the ratio of the amplitude of the synchronization signal part included in the input video signal and the maximum amplitude of the video signal (from 100% white to the synchronization tip) is always constant, VMAX
The appropriate synchronization isolation level V from both the value of left VMIN
TH can be determined. Maximum amplitude of video signal (1
00% white to the sync tip) and the amplitude of the sync signal is 1:K (0<K<1), then if the sync separation level VTR is determined as in equation (1), VTR= '-VMAX+(1-to')・VMIN
・・・・・・・・・(1) However, O<K'<K Good. The ratio of the maximum amplitude of the video signal (from 100% white to the sync tip) and the amplitude of the sync signal is 10:3, that is, =
0.3+7), a value lower than the level that divides the level difference between VMAX and VMIN into 7:3 and higher than the level of VMIN, for example, a level that divides the level difference between VMAX and VMIN into 8=2 ( K' = 0.2) to VTR
All you have to do is set .

As described above, by determining the synchronization separation level from the maximum and minimum values of the input video signal, even if there are level fluctuations or DC fluctuations in the input video signal, an appropriate synchronization separation level can always be obtained, resulting in malfunctions. There's nothing to do.

In addition, if a clamp pulse is generated from the synchronization signal separated by this synchronization separation circuit and the video signal is clamped using this clamp pulse, the synchronization signal included in the input video signal can always be fixed at a predetermined potential. By inputting this clamped video signal to a second sync separation circuit having a fixed sync separation level, highly accurate and stable sync separation can be achieved.

In addition, when performing synchronization separation from a video signal to which a ternary opening signal is added as shown in FIG. Since the value is higher than the level of VTH, it is possible to determine a more appropriate synchronization separation level VTH that is less affected by the content of the video signal, and therefore it is possible to enhance the effect of preventing malfunctions such as synchronization pulse omission and abnormality. Furthermore, when performing synchronization separation from a signal in which a negative polarity synchronization signal and a burst signal, which is the time axis reference of the video signal, are multiplexed as shown in FIG. 2(c), the burst signal multiplexed during the horizontal blanking period Depending on the signal, the maximum value VMAX of the video signal always takes a value equal to or higher than a predetermined level determined by the maximum value of the burst signal. As a result, as in the case of the ternary opening signal shown in FIG. 2(b), it is less susceptible to the influence of the contents of the video signal, and it is possible to enhance the effect of preventing malfunctions such as missing synchronizing pulses and abnormalities.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

In FIG. 1, 1 is an input terminal for a video signal VI containing a synchronization signal, 2 is an output terminal for a separated synchronization signal SP, and 3
1 is a low-pass filter that removes unnecessary noise in the high-frequency components of the input video signal, 4 is a maximum value holding circuit that detects and holds the maximum value of the noise-removed video signal VL, and 5 is noise A minimum value holding circuit detects and holds the minimum value of the removed video signal VL, and 6 indicates the maximum value VMAX of the video signal obtained in step 4 and the minimum value V of the video signal obtained in step 5.
A synchronization separation level generation circuit that generates a synchronization separation level VTR from MIN, and 7 is a video signal V from which noise has been removed in step 3.
This is a comparison circuit that compares the synchronization separation level VTR generated in L and 6. Note that the output of the comparison circuit 7 is outputted from the terminal 2 as a synchronization signal SP.

The video signal input from terminal 1 is passed through low-pass filter 3.
In order to prevent malfunctions due to impulsive noise, etc., high frequency components unnecessary for synchronous separation are removed. The video signal VL from which noise has been removed by the low-pass filter 3 is sent to a maximum value holding circuit 4, which outputs a maximum value signal VL representing the maximum value of the video signal.
MAX is detected and held. Similarly, the image-detected maximum value signal VMAX and minimum value signal VMIN from which noise has been removed are input to a sync separation level generation circuit 6 to generate a sync separation level VTH. This synchronization separation level V
TR is the maximum value signal VMAX and minimum value signal V of the video signal
Since the MIN changes in response to the video signal level and DC offset, an appropriate synchronization separation level can always be obtained even when there are level fluctuations and DC fluctuations in the video signal.

By comparing this synchronization separation level VTR with the input video signal VL from which noise has been removed by the low-pass filter 3, even if there are level fluctuations or DC fluctuations in the input video signal, synchronization with fewer malfunctions due to these fluctuations can be achieved. A separate circuit can be realized.

Next, we will discuss the operation of this synchronization separation level generation circuit 6 in the fifth section.
This will be explained using the operation waveform diagram shown in the figure. FIG. 5(a) is an operational waveform diagram when the input video signal changes from white to black. For the video signal VL from which noise has been removed, the maximum value signal V
MAX is always the upper limit level of the video signal, and even when the content of the video signal changes from white to black, it changes to the black level with a predetermined time constant. Also, the minimum value signal■
MIN is always the lower limit level of the video signal, which is approximately equal to the level of the leading edge of the synchronization signal.

In this way, the video signal VL including the negative polarity synchronization signal always takes a level between the value of VMAX and the value of VMIN. Therefore, by setting the sync isolation level VTR to a level that internally divides the difference between VMAX and VMIN at a predetermined ratio, as shown in FIG. 5(a), an appropriate sync isolation level can always be obtained. Also, as shown in Figure 5(b), when the video content suddenly changes and sudden DC fluctuations occur,
Since VMAX and VMIN change depending on the video signal,
An appropriate synchronization separation level can always be obtained, and malfunctions such as missing synchronization pulses shown in FIGS. 4(c) and 4(d) due to rapid DC fluctuations can be prevented. Furthermore, since the synchronization separation level KTH is a level that internally divides the difference between both VMAX and VMIN at a predetermined ratio, even if the amplitude of the input video signal changes, the ratio between the 100% level of the video signal and the synchronization signal level If is constant, the synchronization separation level will also change depending on the amplitude of the video signal, so as shown in Fig. 4(e), (
It is possible to prevent malfunctions such as synchronization pulse abnormalities shown in f).

Next, an example of a specific configuration of the synchronization separation level generation circuit 6 will be described with reference to FIG. In FIG. 6, 13 is an input terminal for a maximum value signal VMAX representing the maximum value of the video signal;
14 is the input terminal for the minimum value signal V'MIN representing the minimum value of the video signal, 15 is the output terminal for the synchronization separation level signal VTR, and 16 is the input terminal 13 for VMAX and the output terminal 1 for KTH.
5 is connected to a resistor having a resistance value R□, 17 is VM
This is a resistor having a resistance value R2 connected to the input terminal 14 of IN and the output terminal 15 of KTH. Next, the operation will be explained. Maximum value signal VMAX from terminal 13, terminal 14
When the minimum value signal VMIN is inputted, the resistor 16,
and 17, the potentials of VMIN and VMAX are divided,
A potential expressed by equation (2) is outputted to the terminal 15 as the synchronization separation level KTH. Here, if we set ' = R, / (R + R2), equation (2) becomes KTH = ' ・VMAX 1 (1-) ・VMI
N・・・・・・・・・ (3) However, ' = R, / (R engineering + R2) The synchronization separation level KTH is the level difference between VMAX and VMIN (1-')
): The level is internally divided into K'. Here, if the ratio of the maximum amplitude of the video signal included in the input video signal (from 100% white to the synchronization tip) to the amplitude of the synchronization signal is 2, then by satisfying equation (4), always '
=R2/ (R work + R2) <K ・・・・・・・・・
(4) An optimal synchronization separation level can be obtained.

For example, the ratio of the maximum amplitude of the video signal (from 100% white to the sync tip) to the amplitude of the sync signal is 10:3 (K=0.
3), for example, R1=800Ω and R2=200Ω so that '=o,2. An appropriate synchronization separation level VTR can be obtained from the maximum value signal VMAX and the minimum value signal VMIN of the video signal using a small-scale circuit such as an abnormal one.

Next, a second embodiment of a specific configuration of the synchronization separation level generation circuit 6 will be described with reference to FIG.

FIG. 7 shows the input terminal 14 of the minimum value signal VMIN and the output terminal 1 of the synchronization separation level signal KTH in the embodiment of FIG.
5, a Zener diode 18 is added between them. This Zener potential vz is set approximately equal to the potential difference between the terminals 15 and 14 when the input video signal is at a black level in the embodiment shown in FIG. This Zener diode 18
By adding VMIN, which always represents the potential of the synchronization tip even when the content of the input video signal is higher than the black level.
Since a potential higher by vZ than VTH is output as the synchronization separation level VTH, the synchronization is always separated at a fixed position of the synchronization signal waveform regardless of changes in the video content, which makes it possible to reduce fluctuations in the pulse width of the output synchronization signal SP. can. Furthermore, if the level of the input video signal decreases due to some abnormality, the potential difference between terminals 15 and 14 will be equal to the Zener potential vZ.
Zener diode 18 does not operate because the voltage decreases further,
As in the embodiment of FIG. 6, the synchronization separation level is determined by the potentials of VMAX and VMIN and the resistance values R□ and R2 of the resistors 16 and 17, so that an appropriate synchronization separation level can always be obtained.

Next, an example of a specific configuration of the maximum value holding circuit 4 and the minimum value holding circuit 5 will be described using FIG. 8. 8th
Figure (a) shows an example of a maximum value holding circuit, and Figure (b) shows an example of a minimum value holding circuit. In FIG. 8(a), 19 is an input terminal for the noise-removed video signal VL, 20 is an output terminal for the maximum value signal VMAX, 21 is a diode, 22 is a capacitor that holds the maximum potential, and 23 is the capacitor 22. A resistor 24 is a buffer amplifier for discharging charges at a predetermined time constant.

When the potential of the capacitor 22 is low with respect to the video signal VL input from the terminal 19, the diode 21 is turned on, and the potential of the capacitor 22 is increased until it becomes equal to the level of the video signal. When the level of the input video signal VL is lower than the potential of the capacitor 22, the diode 21 is turned off and the potential of the capacitor 22 gradually decreases according to a time constant determined by the resistance value of the resistor 23 and the capacitance of the capacitor 22.

Through the above-described operation, the potential of the capacitor 22 is held at the maximum value of the input video signal VL.

The potential of this capacitor 22 is outputted to a terminal 20 via a buffer amplifier 24 as a maximum value signal VMAX.

FIG. 8(b) shows an example of the configuration of the minimum value holding circuit.

25 is the input terminal for the video signal VL, 26 is the minimum value signal VM
27 is a diode, 28 is a capacitor, 29 is a resistor, and 3o is a buffer amplifier. The configuration is such that the polarity of the diode 21 is reflected in the configuration of the maximum value holding circuit shown in FIG. 8(a). Therefore, the same figure (
In the minimum value holding circuit b), when the level of the input video signal VL is lower than the potential of the capacitor 28, the diode is turned on and the minimum value of the video signal is held. The potential of this capacitor 28 is output as the minimum value signal VMIN from the terminal 26 via the buffer amplifier 3o.

As described above, by detecting and holding the maximum and minimum values of the video signal, it is possible to generate a synchronization separation level that corresponds to DC fluctuations and level fluctuations of the video signal.

The synchronization separation circuit of the present invention can directly separate synchronization from a video signal containing a synchronization signal, and does not require other timing pulses or the like. Therefore, by combining a signal processing device that performs processing using timing pulses generated from a synchronization signal and the synchronization separation circuit of the present invention, a more stable signal processing device can be realized. As an example of this:
An example of the DC regeneration circuit will be described below with reference to FIG. 9.

In FIG. 9, 31 is a video signal VI including a synchronization signal.
, 32 is an output terminal for the DC-regenerated video signal VIC, 33 is a sync separation circuit of the present invention, and 34 shapes the sync signal separated by the sync separation circuit 33 of the present invention to generate a clamp pulse CP. Pulse shaping circuit, 35
is a clamp circuit that actively clamps the input video signal VI to a predetermined potential using the clamp pulse CP generated by the pulse shaping circuit, and outputs the output VIC to the output terminal 32.

Next, the operation of this embodiment will be explained using the waveform diagrams of FIGS. 1o (a) to (d). FIG. 10 (,) shows the video signal VI input from the terminal 31.

This input video signal VI is subjected to synchronization separation by the synchronization separation circuit 33 of the present invention, and a synchronization signal SP as shown in FIG. 10(b) is output. As shown above, the synchronization separation circuit of the present invention can separate synchronization without malfunctions such as missing synchronization pulses or abnormalities even if there is DC fluctuation in the input video signal as shown in Figure 1 (,). It is done. This synchronizing signal SP is shaped by the pulse shaping circuit 34 into a clamp pulse CP having a predetermined pulse width as shown in FIG. 10(Q). In the clamp circuit 35, by fixing the synchronization tip of the input video signal VI to a predetermined potential using the above-mentioned clamp pulse CP, DC fluctuations are removed and the DC component of the original video is reproduced, as shown in FIG. 10(d). A video signal VIC can be obtained.

According to this embodiment, since the synchronous separation circuit of the present invention is used to generate clamp pulses, the video signal can be reliably clamped regardless of DC fluctuations in the input video signal. As a result, the DC component lost during the transmission process can be regenerated with high accuracy without applying a clamp pulse from the outside, and is extremely effective as a clamp circuit when converting a video signal into digital data.

In the embodiments shown in FIGS. 9 and 10 described above, the synchronization tip of the input video signal is clamped to be equal to the ground potential. The chromatic level or the like may be clamped to be equal to a predetermined potential.

At this time, the pulse shaping circuit 14 performs a shaping process on the synchronizing pulse SP so that the clamp pulse CP is generated at a predetermined clamp position.

Next, FIGS. 11 and 10 (d) and (e
).

In FIG. 11, 31 is a video signal V containing a synchronization signal.
36 is an output terminal for the separated synchronization signal SP2, 33 is the sync separation circuit of the present invention, and 34 is the sync signal SP separated by the sync separation circuit 33 of the present invention, and is shaped to generate a clamp pulse CP. pulse shaping circuit, 3
5 is a clamp circuit that actively clamps the input video signal VI to a predetermined potential using the clamp pulse CP generated by the pulse shaping circuit, and outputs the output VIC to the terminal 32;
7 is a DC reproduced video signal V input from the terminal 32
A comparison circuit compares the IC with a predetermined synchronization separation level VTH2, separates the synchronization signal, and outputs it to a terminal 36. Reference numeral 38 is a potential generator that generates the predetermined synchronization separation level VTH2.

The configurations of the input terminal 31, the synchronous separation circuit 33 of the present invention, the pulse shaping circuit 34, the clamp circuit 35, and the output terminal 32 for the DC-regenerated video signal VIC are shown in FIGS. 9 and 10.
This is similar to the embodiments in Figures (,) to (d). The DC reproduced video signal VIC output to the terminal 32 is shown in FIG.
), the potential at the synchronous tip is always constant.

Thereafter, synchronous separation is performed by the comparator 37 using a synchronous separation level having a predetermined potential VTH2, and as shown in FIG.
) can be obtained as an output.

According to this embodiment, since DC reproduction is performed using the synchronization separation circuit of the present invention for clamp pulse generation, DC fluctuations in the input video signal can be removed.

Thereafter, synchronization separation is performed by comparison with a constant fixed potential from the synchronization tip, so that it is possible to stably obtain a synchronization signal with extremely high time axis precision with little variation in pulse width of the separated synchronization signal.

The above embodiments have all been explained using the example of separating a negative polarity synchronization signal as shown in FIG. figure(
c) Negative polarity as shown.

In a signal in which a period signal and a burst signal serving as a time axis reference of a video signal are multiplexed, the minimum value signal VM of the video signal
The fact that IN takes almost the level of the synchronization tip is the same as in the case of the negative polarity synchronization signal, but the maximum value signal VMAX is lower than at least the positive polarity level of the ternary opening signal or the maximum amplitude level of the burst signal. There's nothing to do. Therefore, it is less susceptible to the influence of the contents of the video signal, and an appropriate synchronization separation level can be obtained more stably. Therefore, compared to a negative polarity synchronization signal, when a three-value open signal or a burst signal is included, it is more effective to prevent synchronization pulses from being mixed in or missing due to DC fluctuations, gain fluctuations, etc. of the input video signal. The effect can be increased.

〔Effect of the invention〕

According to the present invention, when separating a synchronization signal from a video signal including a synchronization signal, the synchronization separation level is determined using the maximum and minimum values of the input video signal, so DC fluctuations and gain fluctuations of the input video signal Even if there is a problem, it is possible to obtain an appropriate synchronization separation level corresponding to various fluctuations, and there is an effect of preventing abnormal mixing and omission of synchronization pulses. Furthermore, by generating a clamp pulse using the synchronization signal separated by the present synchronization separation circuit and actively clamping the input video signal, accurate DC reproduction can be performed without applying a clamp pulse from the outside. Further, by synchronously separating the DC reproduced video signal at a predetermined synchronous separation level, a stable synchronous signal with high time axis accuracy can be obtained. In addition, in video signals that include not only negative polarity synchronization signals but also ternary open-time signals and burst signals, the maximum value of the video signal is at least determined by the maximum amplitude value of the burst signal, as the length of the positive pole of the ternary open-time signal is determined by the maximum amplitude value of the burst signal. , it is less susceptible to the influence of video signals, and is more effective than preventing abnormal mixing and omission of synchronizing pulses.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a waveform diagram of a synchronization signal, FIG. 3 is a block diagram showing an example of the configuration of a conventional synchronization separation circuit, and FIG. Operation waveform diagram of
Fig. 5 is an explanatory diagram of the operation of the present invention, Figs. 6 and 7 are block diagrams showing the structure of a synchronization separation level generation circuit, and Fig. 8 shows an example of the structure of a maximum value holding circuit and a minimum value holding circuit. FIG. 9 is a block diagram showing a second embodiment of the present invention, FIG. 1o is an operation waveform diagram of FIG. 9, and FIG. 11 is a block diagram showing a third embodiment of the present invention. . 3. Low pass filter, 4. Maximum value holding circuit. 5... Minimum value holding circuit, 6... Synchronization separation level generation circuit, 7, 37... Comparison circuit, 18... Zener diode, 33... Synchronization separation circuit, 34... Pulse shaping circuit , 35...clamp circuit. Al mouth MIN Me2 Tomoe Akira 5 Kuchi Akira 40 td)”'F (fn
sr Akira, 5 eyes 1z Taku 7 Oka. ) Akira 80 3. . Departure C? mouth<e+
51'2 170th

Claims (1)

[Scope of Claims] 1. In a sync separation circuit that separates sync signals multiplexed during a blanking period of a video signal, means (4) for detecting and holding the maximum value of the sync signal multiplexed in the video signal; , means (5) for detecting and holding the minimum value of the multiplexed video signal of the synchronization signal; means (6) for generating a synchronization separation level from the obtained maximum and minimum values; A synchronization separation circuit comprising means (7) for generating a pulse train by comparing a multiplexed video signal and a synchronization separation level, and configured to use the pulse train as a separated synchronization output. 2. In a synchronization separation circuit that takes as an input signal a multiplexed signal of at least a negative polarity synchronization signal and a reference signal having a level higher than the black level of the video signal during the blanking period of the video signal, and separates the synchronization signal, the above input means (4) for detecting and holding the maximum value of the signal at a level higher than the reference signal; means (5) for detecting and holding the minimum value of the input signal; and synchronization from the obtained maximum and minimum values. The present invention is configured to include means (6) for generating a separation level, and means (7) for generating a pulse train by comparing the input signal with the synchronization separation level, and using the pulse train as a separate synchronization output. Features a synchronous separation circuit. 3. In a DC regeneration circuit that receives as an input signal a signal multiplexed with a negative polarity synchronization signal during a blanking period of a video signal, means (4) for detecting and holding the maximum value of the input signal; means (5) for detecting and holding the minimum value of , means (6) for generating a synchronization separation level from the obtained maximum and minimum values, and a first means (7) for generating a pulse train; means (34) for shaping the first pulse train to generate a second pulse train; and a part of the blanking period of the input signal by the second pulse train. means (35) for fixing the potential to a predetermined potential, and is configured to output a DC reproduction signal with a signal fixed to a predetermined potential during a part of the blanking period. 4. Claim 1, wherein the means (6) for generating a synchronization separation level from the obtained maximum value and minimum value includes means (16, 17) for generating a synchronization separation level by linear calculation of the maximum value and minimum value. Or the synchronous separation circuit according to claim 2. 5. Means (6) for generating a synchronization separation level from the obtained maximum value and minimum value, means (16, 17) for generating a synchronization separation level by linear calculation of the maximum value and minimum value; 3. The synchronization separation circuit according to claim 1, further comprising means (18) for limiting the difference between the level and the minimum value to a predetermined value. 6. Means (38) for generating a second synchronization separation level for the DC reproduction output; Means (37) for comparing the DC reproduction output and the second synchronization separation level to separate and output a synchronization signal. The DC regeneration circuit according to claim 3, comprising: