JPS60171871A - Clamp circuit - Google Patents

Abstract

PURPOSE:To obtain a highly stable clamp circuit at a high speed by comparing two threshold levels and an input pulse level, and keeping the pulse level between the two threshold levels. CONSTITUTION:An input signal is outputted through an amplifier 1, resistor 2 and a voltage buffer 3. The output of the buffer 3 is supplied to voltage comparators 5, 6 through an LPF4. The threshold voltages VTh1, VTh2 of the comparators 5, 6 are set as VTh1>VTh2. A voltage current converter 11 adjusts a current flowing to the resistor 2 to clamp the SYNC level between the VTh1 and VTh2.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a clamp circuit that clamps the pulse tip level of an input pulse train to a predetermined potential, and is particularly suitable for use in a sync tip clamp circuit for television signals.

BACKGROUND ART AND THEIR PROBLEMS In video machines such as TV receivers and VTRs, clamp circuits are used for DC reproduction of input video signals. The level to be clamped is the synchronization tip level or pedestal level of the video signal.

In the case of a sync-step clamp, since the pulse width of the synchronizing signal is narrow, a normal diode clamp circuit cannot be expected to perform a sufficient ramp operation, resulting in a slow response speed and a clamp error. Furthermore, signal deterioration is likely to occur due to sag caused by discharge of the clamp capacitor.

Further, when performing synchronous sync tip clamping using a clamp pulse, a synchronizing signal is required. The synchronization signal is obtained by separating it from the video signal in a synchronization separation circuit, but in order for the synchronization separation circuit to operate normally, it is a prerequisite that the level of the synchronization signal portion of the input video signal is stable. Therefore, in reality, a clamp circuit is also required before the synchronous separation circuit. In other words, stable lamp operation cannot be expected with only a synchronous sync step clamp circuit.

OBJECTS OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and its purpose is to provide a reliable and high-speed method that does not require clamp pulses and even if the width of the pulse to be clamped is narrow. An object of the present invention is to provide a clamp circuit that operates stably.

Summary of the Invention The clamp circuit of the present invention compares two threshold levels with minute level differences with the pulse tip level of the input signal train, and depending on each comparison output, the pulse tip level is set to the first threshold level. On the trail, 1st. Second
During the threshold level of υ, we obtain six logic levels corresponding to the three states below the second threshold level, and based on this state signal, the pulse tip between the two threshold levels. Try to hold the level 7
It is a ζ thing. With this configuration, a high-speed, highly stable operation sink circuit that does not require an external clamp pulse can be obtained.

Example The present invention will be explained below based on examples.

FIG. 1 is a block diagram of a clamp circuit to which the present invention is applied, and FIG. 2 is an operating waveform diagram thereof.

The input video signal is S/N at the time of sync chip level detection.
After being appropriately amplified by amplifier 1, in order to increase the
, and is output through the voltage buffer 3. On the other hand, the output waveform of the buffer 6 passes through a low-pass filter 4 to remove noise, and is applied to voltage comparators 5 and 6. The low-pass filter 4 suppresses pulse noise that protrudes from the sync tip. The threshold voltage of the comparator 5 is vth i (a), and the threshold voltage of the comparator 6 is Vth 2.

As shown in Figure 2, Vth 1 ) and Vth 2 are assumed. The difference between these threshold voltages is, for example, 10rn
It is minute like v.

The outputs of the comparators 5 and 2 are fed to the IJ Galaple mono multivibrator 7.8, which has a metastable time constant of one horizontal scanning period or more, and these outputs output low or high logic levels depending on the input. is obtained.

The outputs of the multivibrator 7.8 are summed by a resistor adder 9, passed through an integrator 10 (low-pass filter) for suppressing transients, and applied to a voltage-current converter 11. The voltage-current converter 11 adjusts the current flowing through the resistor 2, and controls the DC level of the video signal determined by the divided voltage between the resistor 2 and the resistor 12 connected to the negative voltage power source -VK.

Now, as shown in Figure 2, the sync chip level of the video signal applied to the comparator 5.6 is Vth 1.
If it is high, comparators 5 and 6 as shown in Figure 2 B and O
The outputs of both become low level, and the output of adder 9 also remains low level, passes through integrator 10, and enters voltage-current converter 11. Here, the voltage-current converter 11 operates such that as the voltage applied thereto decreases, the current flowing into its output increases. Therefore, the DC current flowing through resistor 2 increases,
As a result, the input and output DC voltages of the buffer 6 operate in the direction of decreasing.

Next, as shown in Figure 2, the sync chip level is V.
When th is lower than 1 and higher than Vth 2, the output of comparator 5 becomes high level, and the output of comparator 6 remains at low level, as shown in FIG. 2B and O. The monomulti 7 extends the high level of the output of the comparator 5 by one horizontal synchronization period, as shown in part H of the second diagram. As a result, the output of the monomulti 7 becomes high level, the output of the mono multi 8 becomes low level, and the output of the adder 9 becomes high level. After the integrator 10 suppresses the transient, the voltage-current converter 11 operates to reduce the DC current flowing through the resistor 2, and the DC voltage output from the buffer 6 has a sink tip level of Vth 1 and Vth
It is controlled so that it falls between 2 and 2.

Next, as in Figure 2, the old capital of man, the sink chip level is Vt.
If h is lower than 2, the outputs of comparators 5 and 6 are both at high level, as shown in FIG. The output becomes twice as high level. Integrator 1
After passing through 0, the voltage-current converter 11 operates to further reduce the DC current flowing through the resistor 2, and the DC voltage at the output of the buffer 6 increases.

Through the above process, the sink chip has the vthl and Vth
It is clamped at a level between 2 and 2.

Note that by flowing an appropriate bias current through the resistor 2, it is possible to set the sink chip to be stable while increasing and decreasing the level of Vth 2, for example.

According to the above configuration, it is possible to reliably clamp the clamping circuit even if a clamping pulse is applied from the outside and a force is applied, so that it is particularly useful as a clamping circuit installed in the front stage of a synchronous separation circuit. In addition, unlike conventional diode clamp circuits, the clamp capacitor does not impose a time constant on the clamp operation, and the control circuit actively acts in both directions to lower and raise the DC potential of the input signal, resulting in a faster response. It will be done. In addition, since the human capulus width is unrelated to the clamping operation, the input pulse width is extremely thin.
'L/ Because the low-pass filter 4 is inserted before detecting the hello, it is stable against noise.

In the configuration of the above-described embodiment, the control signal applied to the voltage-current converter 11Vc through the integrator 10 is, for example, negative,
It may be in three states, zero and positive.

Effects of the Invention As described above, the present invention compares two (7) threshold levels with minute level differences and the pulse tip level of the input pulse train, and when the pulse tip level falls between the two threshold levels. A 6-level state signal is obtained from the three states of deviating from above and below, and with this state signal, the pulse tip level is set to two thresholds M.
The DC level of the input pulse train is controlled so that K is maintained at 1 JtL. Therefore, the clamp operation can be performed without applying a clamp pulse from the outside as in the conventional case, so it can be used in a circuit part where a clamp pulse cannot be obtained. Also, since there is no clamp capacitor,
There is no room for a time constant in the clamp operation, so even with a narrow input pulse it operates stably and at high speed. Furthermore, since the input signal does not pass through the clamp capacitor, a high quality clamp output without signal deterioration can be obtained.

[Brief explanation of drawings]

Figure 1 is a circuit diagram of a clamp circuit to which the present invention is applied;
The figure is an operation waveform diagram of FIG. 1. In the drawing numbers used, 1...... Amplifier 2... Resistor 6... Voltage buffer 4...
......Low pass filter 5.6...
Voltage comparator 7.8...Retrigger pull mono multivibrator 9...Adder 10...Integrator 11... ......Current current converter 12...
・・・・・・・・・・・・Resistance. Agent Masaru Doyo Yoshio Tsunekami

Claims (1)

[Claims] Comparing the first and second threshold levels of the minute level difference with the pulse tip level of the input pulse train 2
the outputs of these comparators are received so that the pulse tip level is υ above the first threshold level,
, a circuit for obtaining a state signal having three logic levels corresponding to three states p below the second threshold level during the second threshold level, and a circuit for obtaining the above two states based on this state signal. and a control circuit that holds a pulse tip level of an input pulse train between a threshold level.