JPS59200528A - Detection system for phase-unlocked state of phase-locked loop - Google Patents

Detection system for phase-unlocked state of phase-locked loop

Info

Publication number
JPS59200528A
JPS59200528A JP58073295A JP7329583A JPS59200528A JP S59200528 A JPS59200528 A JP S59200528A JP 58073295 A JP58073295 A JP 58073295A JP 7329583 A JP7329583 A JP 7329583A JP S59200528 A JPS59200528 A JP S59200528A
Authority
JP
Japan
Prior art keywords
phase
circuit
signal
locked loop
pulse
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58073295A
Other languages
Japanese (ja)
Inventor
Yoshio Kiriyama
良雄 桐山
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP58073295A priority Critical patent/JPS59200528A/en
Publication of JPS59200528A publication Critical patent/JPS59200528A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00Automatic control of frequency or phase; Synchronisation
    • H03L7/06Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08Details of the phase-locked loop
    • H03L7/085Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/095Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using a lock detector

Landscapes

  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

PURPOSE:To remove unstableness from phase-unlocked state detecting operation by generating pulse signals from an original signal and a feedback signal respectively, and detecting the crossing of those two pulse signals. CONSTITUTION:An input signal [original signal (a)] and the feedback signal (b) to the phase comparing circuit 1 of a phase-locked loop are inputted to a pulse generating circuit 6 respectively. The circuit 6 generates pulse signals (f) and (g) from the original signal (a) and feedback signal (b). The signals (f) and (g) are controlled in relative phase relation while the phase-locked loop is in a phase- locked state, so a pulse crossing detecting circuit 7 detects no crossing of the signals (f) and (g). When the phase-locked loop enters the phase-unlocked state, the relative phase relation between the signals (f) and (g) is not maintained any more and varies continuously in either direction, and the circuit 7 detects the crossing of the signals (f) and (g) synchronously to send a pulse crossing detection signal (h) to an unlocked-state detection output circuit 8, which outputs a phase-unlocked state detection output signal (e).

Description

【発明の詳細な説明】 本発明は、位相同期ループにおける非同期状態検出方式
に関するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an asynchronous state detection method in a phase-locked loop.

従来の位相同期ループの非同期状態の検出方式の構成は
第1図に示すとおりである。第1図において、■は位相
比較回路、2はループフィルタ回路、3は電圧制御発振
回路、4は非同期状態検出用比較回路、5は非同期状態
検出出力回路を示す。
The configuration of a conventional method for detecting an asynchronous state of a phase-locked loop is shown in FIG. In FIG. 1, ■ indicates a phase comparison circuit, 2 indicates a loop filter circuit, 3 indicates a voltage controlled oscillation circuit, 4 indicates an asynchronous state detection comparison circuit, and 5 indicates an asynchronous state detection output circuit.

つ1り従来、位相同期ループにおける非同期状態の検出
は、位相同期ループ内の位相比較回路の出力を、・次段
のループフィルタ回路に通し、ループフィルタ回路の直
流出力レベルが、比較回路に予め設定された闇値の範囲
内に入っているか否かをもって、当該位相同期ループが
、同期状態であるか、あるいは、非同期状態であるかを
判定することにより実施されていた。
Conventionally, in order to detect an asynchronous state in a phase-locked loop, the output of the phase comparison circuit in the phase-locked loop is passed through the next-stage loop filter circuit, and the DC output level of the loop filter circuit is determined beforehand by the comparison circuit. This has been implemented by determining whether the phase-locked loop is in a synchronous state or an asynchronous state based on whether the darkness value is within a set range.

かかる非同期状態検出方式では、ループフィルタ回路の
直流出力レベル及びその後段に設けられた比較回路の設
定閾値を判定基準としているため、ループフィルタ回路
及びその後段の比較回路の構成部品の持っている偏差、
特性等によって、前記直流出力レベル及び比較回路にて
設定の閾値自体が、それぞれ偏移し、安定な検出動作が
得られず、再調整を必要とするなどの欠点を有していた
In such an asynchronous state detection method, since the DC output level of the loop filter circuit and the set threshold of the comparison circuit provided in the subsequent stage are used as the judgment criteria, deviations in the components of the loop filter circuit and the comparison circuit in the subsequent stage are used as the determination criteria. ,
Due to characteristics, etc., the DC output level and the threshold value set in the comparator circuit deviate from each other, making it impossible to obtain a stable detection operation and requiring readjustment.

本発明の目的は、上記欠点を除去するため、ループフィ
ルタ回路の直流出力レベル及び、比較回路によって設定
した閾値という判定レベルを使用せず、位相同期ループ
に入力される信号(以後、原信号と呼ぶ)と、位相同期
ループの位相同期回路に帰還される信号(以後、帰還信
号と呼ぶ)から、それぞれパルス信号を生成し、これら
2つのパルス信号の交差を論理回路にて検出することに
より、回路構成要素の偏差、特性に起因する前記非同期
状態検出動作の不安定性を取り除くことを可能とした位
相同期ループの簡易的な非同期状態検出方式を提供する
ことにある。
An object of the present invention is to eliminate the above-mentioned drawbacks by eliminating the use of the DC output level of the loop filter circuit and the judgment level of the threshold value set by the comparator circuit, and instead of using the signal input to the phase-locked loop (hereinafter referred to as the original signal). By generating pulse signals from the signal (hereinafter referred to as the feedback signal) and the signal fed back to the phase-locked circuit of the phase-locked loop (hereinafter referred to as the feedback signal), and detecting the intersection of these two pulse signals using a logic circuit, It is an object of the present invention to provide a simple asynchronous state detection method for a phase-locked loop that makes it possible to eliminate instability in the asynchronous state detection operation caused by deviations and characteristics of circuit components.

前記目的達成のため、本発明は、原信号及び帰還信号か
ら、それぞれパルス信号を生成するだめのパルス生成回
路と、前記パルス生成回路にて生成された2つのパルス
信号の交差を検出するパルス交差検出回路及び前記パル
ス交差検出回路から、前記の2つのパルス信号の交差を
検出して出力される出力信号にて、当該位相同期ループ
の非同期状態の検出信号を出力する出力回路を具備して
構成される。
To achieve the above object, the present invention provides a pulse generation circuit for generating pulse signals from an original signal and a feedback signal, respectively, and a pulse crossing circuit for detecting the intersection of two pulse signals generated by the pulse generation circuit. An output circuit configured to output a detection signal of an asynchronous state of the phase-locked loop using an output signal outputted from the detection circuit and the pulse crossing detection circuit by detecting the crossing of the two pulse signals. be done.

次に、本発明の実施例について図面を参照して説明する
Next, embodiments of the present invention will be described with reference to the drawings.

第1図は、基本的な位相同期ループと、従来の非同期検
出方式の構成図、第2図は、−w本釣な位相同曲ループ
と、本発明にかかる非同期検出方式の構成の一実施例で
ある。また第3図及び第4図は、本発明における非同期
検出の原理を説明するための信号波形であり、第3図は
、同期状態の第4図は非同期状態を示している。
FIG. 1 is a configuration diagram of a basic phase-locked loop and a conventional asynchronous detection method, and FIG. 2 is a configuration diagram of a -w-based phase-locked loop and an asynchronous detection method according to the present invention. This is an example. Further, FIGS. 3 and 4 show signal waveforms for explaining the principle of asynchronous detection in the present invention, with FIG. 3 showing a synchronous state and FIG. 4 showing an asynchronous state.

第2図において、位相同期ループの位相比較回路1への
入力信号(原信号イ)と、帰還信号口を、それぞれパル
ス生成回路6に入力する。パルス生成回路6は、前記、
原信号イ及び帰還信号口から、パルス信号ト及び手をそ
れぞれ生成する。これら2つのパルス信号ト及びチは、
位相同期ループが同期状態であるとき、第3図に示すよ
うに、相対的な位相関係を維持するよう制御されている
ため、後段に設けたパルス交差検出回路7において、前
記の2つのパルス信号トとチの交差は検出されない。
In FIG. 2, the input signal (original signal A) to the phase comparison circuit 1 of the phase-locked loop and the feedback signal port are respectively input to the pulse generation circuit 6. The pulse generation circuit 6 includes the above-mentioned
Pulse signals G and H are generated from the original signal A and the feedback signal port, respectively. These two pulse signals G and H are
When the phase-locked loop is in a synchronous state, as shown in FIG. The intersection of G and G is not detected.

それに対して、位相同期ループが非同期状態となったと
き、第3図に示すような前記パルス生成回路6からのパ
ルス信号トとチの相対的な位相関係の安定性は維持され
ず、第4図に示すように、矢印で示すどちらかの方向に
相対的な位相関係が連続的に変動することとなる。そこ
で、後段に設けたパルス交差検出回路7は、前記入力信
号(原信号イ及び帰還信号口)に由来するパルス信号ト
及びチの交差を周期的に検出することとなり、非同期状
態検出出力回路8に、パルス交差検出信号りを受けて、
当該位相同期ルーズが非同期状態にあることを示す非同
期状態検出出力信号へを出力し、あるいは、当該状態検
出の表示を行なう。
On the other hand, when the phase-locked loop becomes asynchronous, the stability of the relative phase relationship between the pulse signals T and C from the pulse generation circuit 6 as shown in FIG. As shown in the figure, the relative phase relationship changes continuously in either direction indicated by the arrow. Therefore, the pulse crossing detection circuit 7 provided at the subsequent stage periodically detects the crossing of the pulse signals G and Q derived from the input signals (original signal A and the feedback signal port), and the asynchronous state detection output circuit 8 Then, upon receiving the pulse crossing detection signal,
It outputs an asynchronous state detection output signal indicating that the phase synchronization loose is in an asynchronous state, or displays the detected state.

第3図は、第2図の実施例において、同期状態であると
きの前記パルス信号ト及びテの相対的な位相関係が、第
3図のように維持されていることを示し、第4図は、第
2図の実施例において、非同期状態であるとき、前記パ
ルス信号ト及びチの相対的な位相関係が第4図の矢印で
示したどちらかの方向に、連続的にずれることを示した
ものである。
FIG. 3 shows that in the embodiment of FIG. 2, the relative phase relationship of the pulse signals T and T in the synchronous state is maintained as shown in FIG. 3, and FIG. indicates that in the embodiment of FIG. 2, when in an asynchronous state, the relative phase relationship of the pulse signals G and C continuously deviates in either direction shown by the arrow in FIG. It is something that

本発明は、以上説明した如く、位相同期ループ=5− の位相比較回路に入力される原信号及び帰還信号から、
パルス信号をそれぞれ生成し、両パルス信号の交差を論
理回路により検出、処理する方式により、従来の非同期
検出方式に内在していた回路構成要素の偏差、特性等に
起因する検出動作の不安定性を除去すると供に、前記不
安定性を改善するだめの再調整を不用とする効果がある
As explained above, the present invention is based on the original signal and feedback signal input to the phase comparison circuit of phase locked loop = 5-.
The method of generating pulse signals individually and detecting and processing the intersection of both pulse signals using a logic circuit eliminates the instability of detection operation caused by deviations and characteristics of circuit components inherent in conventional asynchronous detection methods. This has the effect of eliminating the need for readjustment of the device for improving the instability.

【図面の簡単な説明】[Brief explanation of the drawing]

m1図は、基本的な位相同期ループと従来の非同期状態
検出方式の構成図、第2図は本発明の実施例を示す構成
図、第3図と第4図は第2図の実施例を説明するだめの
図である。 1・・・・・・位相比較(ロ)路、2・・・・・・ルー
プフィルタ回路、3・・・・・・電圧制御発振回路、4
・・・・・・非同期状態検出用比較回路、5・・・・・
・非同期状態検出出力回路6・・・・・・パルス生成回
路、7・・・・・・パルス交差検出回路、8・・・・・
・非同期状態検出出力回路、イ・・・・・・位相同期ル
ープ入力信号(原信号)、口・・・・・・位相同期ルー
プ出力信号(帰還信号)、ノ・・・・・・・・位相誤差
信6一 号、二・・・・・・電圧制御発振回路制御信号、ホ・・
・・・・非同期状態検出信号、へ・・・・・・非同期状
態検出出力信号、ト・・・・・・原信号イより生成のパ
ルス信号、チ・・・・・・帰還信号口より生成のパルス
信号、す・・・・・・パルス交差検出信号、へ・・・・
・・非同期状態検出出力信号。 完l閃 寮3区
Fig. m1 is a block diagram of a basic phase-locked loop and a conventional asynchronous state detection method, Fig. 2 is a block diagram showing an embodiment of the present invention, and Figs. 3 and 4 show the embodiment of Fig. 2. This is a diagram for illustration purposes only. DESCRIPTION OF SYMBOLS 1... Phase comparison (b) path, 2... Loop filter circuit, 3... Voltage controlled oscillation circuit, 4
...Comparison circuit for detecting asynchronous state, 5...
- Asynchronous state detection output circuit 6...Pulse generation circuit, 7...Pulse crossing detection circuit, 8...
・Asynchronous state detection output circuit, A: Phase-locked loop input signal (original signal), A: Phase-locked loop output signal (feedback signal), No: Phase error signal 6 No. 1, 2... Voltage controlled oscillation circuit control signal, E...
...Asynchronous state detection signal, G...Asynchronous state detection output signal, T...Pulse signal generated from the original signal A, CH...Generated from the feedback signal port Pulse signal,...Pulse crossing detection signal,...
...Asynchronous state detection output signal. Kanl Senryo Ward 3

Claims (1)

【特許請求の範囲】[Claims] 位相同期ループにおける非同期状態検出において、位相
同期ループに対する入力信号及び、位相比較回路への帰
還信号から、それぞれパルス信号を生成し、両パルスの
交差を検出することにより位相同期ループの非同期状態
検出を行なうことを特徴とする位相同期ループの非同期
状態検出方式。
In detecting an asynchronous state in a phase-locked loop, pulse signals are generated from the input signal to the phase-locked loop and the feedback signal to the phase comparison circuit, respectively, and the asynchronous state of the phase-locked loop is detected by detecting the intersection of both pulses. A phase-locked loop asynchronous state detection method characterized by:
JP58073295A 1983-04-26 1983-04-26 Detection system for phase-unlocked state of phase-locked loop Pending JPS59200528A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58073295A JPS59200528A (en) 1983-04-26 1983-04-26 Detection system for phase-unlocked state of phase-locked loop

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58073295A JPS59200528A (en) 1983-04-26 1983-04-26 Detection system for phase-unlocked state of phase-locked loop

Publications (1)

Publication Number Publication Date
JPS59200528A true JPS59200528A (en) 1984-11-13

Family

ID=13514023

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58073295A Pending JPS59200528A (en) 1983-04-26 1983-04-26 Detection system for phase-unlocked state of phase-locked loop

Country Status (1)

Country Link
JP (1) JPS59200528A (en)

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