JPH05227452A - Synchronization separation circuit - Google Patents

Abstract

PURPOSE:To always fetch the synchronizing signal of a constant level even when a synchronizing signal different in the level is inputted. CONSTITUTION:A synchronizing signal level detection circuit 2 detecting level of the input synchronizing signal 1 and generating reference voltage 12 in accordance with the detected level is provided. A comparator 4 comparing reference voltage 12 generated from the circuit 2 with the input synchronizing signal 1 is provided so as to output the synchronizing signal 5 by comparing them.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sync separation circuit for separating sync signals such as video signals.

[0002]

2. Description of the Related Art FIG. 3 is a block diagram of a conventional sync separation circuit. In FIG. 3, a clamp circuit 10 fixes a lower limit voltage of an input sync signal 1. 4 is a comparator,
Input sync signal 1 clamped by the clamp circuit 10
1 is compared with the reference voltage 12 output from the reference power supply 3, and the output synchronization signal 5 having a certain voltage or higher is output.

Next, the operation of the above configuration will be described. The input synchronizing signal 1 having a waveform as shown in FIG. 2A is clamped by the clamp circuit 10, and the clamped input synchronizing signal 11 is input to one of the comparators 4 and the other input of the comparator 4 is also input. A reference voltage 12 is input to the two, and the two are compared. Here, the clamped input synchronization signal 11 is
As shown in (a), the lower limit of the input synchronizing signal 1 is fixed to the clamp voltage 13, and the clamped input synchronizing signal 11 is the reference voltage 12 and the comparator 4 described above.
The output synchronizing signal 5 having the waveform as shown in FIG.

[0004]

Since the conventional sync separation circuit is constructed as described above, when the sync signal 1 having the waveform as shown in FIG. The clamped input synchronization signal 11 is as shown in FIG. At this time, since the reference voltage 12 and the upper limit of the clamped input synchronization signal 11 match, the noise component superimposed on the clamped input synchronization signal 11 is compared when comparing by the comparator 4, and FIG. As shown in (c), the output synchronization signal 5 is not normal. This is because the voltage difference (Δv) between the clamp voltage 13 and the reference voltage 12 is constant irrespective of the level of the input synchronization signal 1, and thus the input synchronization with an amplitude smaller than this voltage difference (Δv). When the signal 1 is input, there is a problem that the circuit does not operate normally and a normal output cannot be obtained.

The present invention has been made to solve the above problems, and provides a sync separation circuit which can always obtain a normal output synchronizing signal regardless of the amplitude of the input synchronizing signal. The purpose is to do.

[0006]

A sync separation circuit according to the present invention includes a sync signal level detection circuit for detecting the size of an input sync signal, and a sync signal level detected by the sync signal level detection circuit. According to the above, the configuration is such that the level for performing the sync separation is changed.

[0007]

According to the present invention, the magnitude of the input sync signal is detected, the sync separation level is changed to match the detected magnitude, and the sync separation is performed. Instead, a constant output synchronization signal is always obtained.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of a sync separation circuit according to an embodiment of the present invention. In FIG. 1, reference numerals 1, 4, and 5 are the same as those in the conventional example shown in FIG. Therefore, detailed description thereof will be omitted.

In FIG. 1, reference numeral 2 is a sync signal level detection circuit for detecting the amplitude of the input sync signal 1. 12
Is according to the upper limit voltage and the lower limit voltage of the input synchronization signal 1,
The reference voltage output from the sync signal level detection circuit 2 as the intermediate voltage is input to the comparator 4 and compared with the input sync signal 1.

Next, the operation of the above configuration will be described with reference to the operation waveform diagram of FIG. The input synchronization signal 1 is input to the synchronization signal level detection circuit 2, where an intermediate reference voltage 12 is output according to the upper limit voltage 6 and the lower limit voltage 7 of the input synchronization signal 1, and the input synchronization signal 1 and the comparator 4 Be compared. Then, as a result of the comparison, as shown in FIG. 2C, a constant upper limit voltage 8 (Vcc) and a lower limit voltage 9 (GND) are constantly output.

By the way, in the case of the sync separation circuit having the configuration shown in FIG. 1, as shown in FIGS. 2A and 2B, the input signal is always input regardless of the amplitude (level) of the amplitude of the input synchronization signal 1. The sync separation is performed in the middle of the amplitude of the sync signal 1, and the normal operation is performed even if the sync signal 1 has a small amplitude.

[0012]

As described above, according to the present invention, since the level for performing the sync separation is changed according to the magnitude of the input sync signal, the normal level is always maintained regardless of the magnitude of the sync signal. , Accurate sync separation is possible and a constant sync signal can be obtained.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a sync separation circuit according to an embodiment of the present invention.

FIG. 2 is a diagram showing operating waveforms in the circuit of FIG.

FIG. 3 is a configuration diagram of a conventional sync separation circuit.

FIG. 4 is a diagram showing operation waveforms in the circuit of FIG.

[Description of symbols] 1 input sync signal 2 sync signal level detection circuit 4 comparator

Claims (1)

[Claims] 1. A sync signal level detection circuit for detecting the size of an input sync signal, and means for changing the level for performing sync separation according to the size of the sync signal detected by the sync signal level detection circuit. A sync separation circuit comprising: