JPS61120585A - Synchronizing signal separating and clamping circuit - Google Patents

Synchronizing signal separating and clamping circuit

Info

Publication number
JPS61120585A
JPS61120585A JP59241147A JP24114784A JPS61120585A JP S61120585 A JPS61120585 A JP S61120585A JP 59241147 A JP59241147 A JP 59241147A JP 24114784 A JP24114784 A JP 24114784A JP S61120585 A JPS61120585 A JP S61120585A
Authority
JP
Japan
Prior art keywords
signal
amplifier
comparator
synchronizing signal
dynamic range
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59241147A
Other languages
Japanese (ja)
Inventor
Kunio Sekimoto
関本 邦夫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP59241147A priority Critical patent/JPS61120585A/en
Publication of JPS61120585A publication Critical patent/JPS61120585A/en
Pending legal-status Critical Current

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  • Picture Signal Circuits (AREA)
  • Synchronizing For Television (AREA)

Abstract

PURPOSE:To attain excellent synchronizing separation and clamping by passing a video signal through an amplifier having a dynamic range where the synchro nizing signal part to be clamped before being fed to a comparator is not suppressed even when a DC potential of the synchronizing signal is fluctuated before the video signal is fed to the comparator. CONSTITUTION:An amplifier 4 is provided after a clamp amplifier 2, the tip of the synchronizing signal being its output signal is clamped by a clamp circuit 5, the result is fed to the comparator 6, and the amplifier 4 has the dynamic range from B to E so as to be activated at a low power supply voltage and small current consumption. When the amplifier 4 has a dynamic range lower than F and an input signal changes from a period T1 to a period T2, a correct synchronizing signal does not appear at the output of the comparator 6 and the loop of the amplifier 2 is not operated normally. When the input signal c changes from the period T1 to the period T1, since the circuit 5 clamps the tip of the synchronizing signal because the upper dynamic range of the amplifier 4 is E, the level responds to a level shown in a signal 13 and then normal synchronizing signal is obtained.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は、VTRやTV等映像機器で、同期信号を分離
し、映像信号をクランプする場合に利用可能な同期信号
分離クランプ装置に関する。
DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a sync signal separation and clamping device that can be used to separate sync signals and clamp video signals in video equipment such as VTRs and TVs.

従来の技術 第3図に従来の同期信号分離・クランプ回路の一例を、
第4図にその各部波形を示す。第3図において、1は映
像信号入力端子、2はクランプ増幅器、3はクランプさ
れた映像信号出力端子、6はクランプ回路、6は比較器
、7はサンプルホールド回路、8は差動増幅器、9は同
期信号出力端子である。端子1に印加された映像信号は
、クランプ増幅器2で増幅・クランプされた後、クラン
プ回路5に導かれ、その同期信号の先端でクランプされ
、比較器6で第4図11に破線で示すような基進電位で
比較され、端子9に同期信号が得られる。一方、端子3
の出力映像信号は、サンプルホールド回路7に導かれ、
端子9の同期信号より作成されたサンプルパルスにより
、そのペデスタル部の電位が検出され、差動増幅器8へ
導かれ、基準電位(図ではグランド)との差が増幅され
、その出力電圧でクランプ増幅器2が制御される。
Conventional technology Figure 3 shows an example of a conventional synchronous signal separation/clamp circuit.
FIG. 4 shows the waveforms of each part. In FIG. 3, 1 is a video signal input terminal, 2 is a clamp amplifier, 3 is a clamped video signal output terminal, 6 is a clamp circuit, 6 is a comparator, 7 is a sample and hold circuit, 8 is a differential amplifier, and 9 is a synchronization signal output terminal. The video signal applied to the terminal 1 is amplified and clamped by the clamp amplifier 2, then led to the clamp circuit 5, where it is clamped at the tip of the synchronizing signal, and the comparator 6 outputs the signal as shown by the broken line in FIG. A synchronization signal is obtained at terminal 9. On the other hand, terminal 3
The output video signal of is led to the sample hold circuit 7,
The potential of the pedestal is detected by the sample pulse generated from the synchronization signal at terminal 9, and is guided to the differential amplifier 8, where the difference from the reference potential (ground in the figure) is amplified, and the output voltage is used to connect the clamp amplifier. 2 is controlled.

クランプ増幅器2は、例えば、差動増幅器8の出力電位
が上がると端子3の出力電位が下がるという様に働き、
差動増幅器8の利得が十分大きいと、サンプルホールド
回路7の出力電位と差動増幅器8の他方の入力の基準電
位が一致する機制御さね、その結果として、端子3に一
定電位にクランプされた映像信号が得られる。入力映像
信号としては、スイッチで切換えられた場合等、第4図
12に示すように同期信号の直流電位が変化するような
場合も考えられる。クランプ回路6がないと、このよう
な場合に、比較器6の出力9に正常な同期信号が出ない
ため、クランプ増幅器2のループが正常に働かず、追従
しなくなる。このためクランプ回路6は、クランプ増幅
器2のループより速い応答になるように設定し、第4図
13に示すように応答させると、この応答後、端子9に
正常な同期信号が出力され、ループる追従させることが
できる。第4図11のAに示すように、映像信号にオー
バーシュート等が生じて、それが同期信号部に入った時
、比較器θの出力には、このオーバーシュート部分が誤
って出力されてしまい、同期信号゛が正常でなくなるの
みならず、サンプルホールド7で誤った点の電位が検出
され、ループを誤った方向に制御してしまい、そのため
、端子3の映像信号が乱れ、従って、端子9には更に誤
った同期信号が出力されるという悪循環を生ずる。
The clamp amplifier 2 works in such a way that, for example, when the output potential of the differential amplifier 8 increases, the output potential of the terminal 3 decreases.
If the gain of the differential amplifier 8 is sufficiently large, the output potential of the sample-and-hold circuit 7 and the reference potential of the other input of the differential amplifier 8 will match, and as a result, the terminal 3 will be clamped to a constant potential. A video signal can be obtained. As for the input video signal, there may be a case where the DC potential of the synchronizing signal changes as shown in FIG. 4, such as when the input video signal is changed by a switch. Without the clamp circuit 6, in such a case, a normal synchronizing signal would not be output to the output 9 of the comparator 6, and the loop of the clamp amplifier 2 would not work properly and would not follow. For this reason, the clamp circuit 6 is set to have a faster response than the loop of the clamp amplifier 2, and when it responds as shown in FIG. can be made to follow. As shown in Fig. 4-11A, when an overshoot occurs in the video signal and enters the synchronization signal section, this overshoot portion is erroneously output to the output of the comparator θ. , not only does the synchronization signal become abnormal, but the potential at the wrong point is detected in the sample hold 7, and the loop is controlled in the wrong direction.As a result, the video signal at terminal 3 is disturbed, and therefore the voltage at terminal 9 is This creates a vicious cycle in which an erroneous synchronization signal is further output.

これを防ぐには、第4図11の破線で示す基準電位をで
きるだけ、同期先端に近い所に設定すれば良いが、信号
の直流変動に対し不安定になるとともに、同期先端にビ
ートノイズが乗っていると、これで誤動作しやすくなる
To prevent this, the reference potential shown by the broken line in Figure 4-11 should be set as close to the synchronization tip as possible, but this will result in instability due to DC fluctuations in the signal and beat noise will be added to the synchronization tip. If you do this, it will be more likely to malfunction.

本発明は、映像信号にオーバーシュートやビートノイズ
があっても良好な同期分離とクランプを行える装置を提
供することを目的とする。
SUMMARY OF THE INVENTION An object of the present invention is to provide a device that can perform good synchronization separation and clamping even if there is overshoot or beat noise in a video signal.

問題点を解決するだめの手段 本発明の同期信号分離・フラング装置は、映像信号を比
較器に供する前に、映像信号中の同期信号の直流電位が
変動しても、比較器に供される前にクランプされる同期
信号の部分が抑圧されない様なダイナミックレンジを有
する増幅器を通している。
Means for Solving the Problems The synchronizing signal separation/franging device of the present invention allows the synchronizing signal to be supplied to the comparator even if the DC potential of the synchronizing signal in the video signal fluctuates before the video signal is supplied to the comparator. It is passed through an amplifier with a dynamic range such that the portion of the synchronization signal that was previously clamped is not suppressed.

作  用 本発明は前記した構成により比較器による同期信号分離
時の余裕度を上げるとともに、増幅器のダイナミックレ
ンジを少なくして、電流の節減をはかる構成を有してい
る。
Operation The present invention has a configuration in which the above-described configuration increases the margin when separating synchronizing signals by the comparator, and reduces the dynamic range of the amplifier to save current.

実施例 @1図に本発明の一実施例のプ07り図、第2同じ動作
をする。4は増幅器である。第3図で述べた問題点を解
決する方法として、比較器6に映像信号を供する前に映
像信号を増幅し、基準電位をオーバーシュートの下で同
期信号部のビートより上の部分だ設定し、基準電位との
比較時に余裕をもたせる方法がある。この時、端子1に
第2図12のような信号が入った場合を考えると、信号
を忠実に増幅するには、増幅器4の出力として第2図1
3のBからDまでのダイナミックレンジが必要である。
Embodiment@1 Figure 1 is a schematic diagram of an embodiment of the present invention, and the second example has the same operation. 4 is an amplifier. As a method to solve the problem described in Fig. 3, the video signal is amplified before being supplied to the comparator 6, and the reference potential is set at a portion above the beat of the sync signal section under overshoot. There is a method to provide a margin when comparing with a reference potential. At this time, if we consider the case where a signal as shown in Figure 2 12 is input to terminal 1, in order to faithfully amplify the signal, the output of amplifier 4 must be as shown in Figure 2 1.
A dynamic range from B to D of 3 is required.

しかしこのためには、電源電圧を大きくとる必要があり
、消費電流も多くなる。以上の点より、本発明は、クラ
ンプ増幅器2の後に増幅器4を設け、その出力信号の同
期信号の先端をり2ンプ回路5でクランプし、比較°器
6へ供し、かつこの増幅器4は、少なくとも、第2図1
3のBからEまでのダイナミックレンジを有するものと
し、低い電源電圧、消費電流でまかなえるようにしてい
る。増幅器4が第2図13のFより下のダイナミックレ
ンジがないとすると、入力信号がT1部からT2 部へ
変った時、増幅器4の出方だ同期信号がなくなり、従っ
て、クランプ回路6で信号を上へもち上げることがない
ため、比較器6の出力には正しい同期信号が出す、クラ
ンプ増幅器2のループが正常に動作しない。従って増幅
器4の下のダイナミックレンジを第2図13のBまでに
している。また、入力信号が、第2図T2部からT1 
部へ変化した時、増幅器4の上のダイナ号の先端をクラ
ンプしているため、第2図13のように応答し、その後
、正常な同期信号を得ることができる。
However, for this purpose, it is necessary to increase the power supply voltage, and the current consumption also increases. From the above points, the present invention provides an amplifier 4 after the clamp amplifier 2, clamps the leading end of the synchronizing signal of the output signal with the amplifier circuit 5, and supplies it to the comparator 6. At least, Fig. 2 1
It has a dynamic range from B to E of 3, which can be achieved with low power supply voltage and current consumption. Assuming that the amplifier 4 does not have a dynamic range below F in FIG. As a result, the loop of the clamp amplifier 2, which outputs a correct synchronizing signal at the output of the comparator 6, does not operate normally. Therefore, the dynamic range under the amplifier 4 is limited to B in FIG. 13. In addition, the input signal is transferred from the T2 section in FIG. 2 to the T1 section.
Since the tip of the dyna signal above the amplifier 4 is clamped, it responds as shown in FIG. 2, and after that a normal synchronization signal can be obtained.

なお、本実施例ではクランプ回路5として同期信号の先
端をクランプする場合について述べた力ζペデスタルを
クランプするような場合は、増幅器4のダイナミックレ
ンジは、少なくとも第2図13のGからDに設定すれば
良い。
In addition, in this embodiment, when clamping the force ζ pedestal described in the case where the clamp circuit 5 clamps the tip of the synchronizing signal, the dynamic range of the amplifier 4 is set at least from G to D in FIG. Just do it.

発明の効果 以上のように本発明によれば、入力映像信号の電位が変
化した場合や、オーバーシュート、ビートノイズがある
場合にも良好な同期信号の分離とクランプを行ない得る
Effects of the Invention As described above, according to the present invention, it is possible to perform good synchronization signal separation and clamping even when the potential of the input video signal changes, or when there is overshoot or beat noise.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例のブロック図、第2図はその
動作を説明するだめの信号波形図、第3図は従来例を示
すブロック図、第4図はその各部波形図である。 2・・・・・・クランプ増幅器、4・・・・・・増幅器
、6・・・・・・クランプ回路、6・・・・・・比較器
、7・・・・・・サンプルホールド回路、8・・・・・
・差動増幅器。
Fig. 1 is a block diagram of an embodiment of the present invention, Fig. 2 is a signal waveform diagram for explaining its operation, Fig. 3 is a block diagram showing a conventional example, and Fig. 4 is a waveform diagram of each part thereof. . 2... Clamp amplifier, 4... Amplifier, 6... Clamp circuit, 6... Comparator, 7... Sample hold circuit, 8...
・Differential amplifier.

Claims (1)

【特許請求の範囲】[Claims] 分離された同期信号より作成されたサンプルパルスを用
いて第1のクランプ回路により映像信号をクランプし、
このクランプされた映像信号を第2のクランプ回路を介
し比較手段に与え基準電位と比較して前記同期信号を分
離するようにし、かつ、映像信号を前記比較手段に供す
る前に、映像信号中の同期信号の直流電位が変動しても
少なくとも前記第2のクランプ回路により同期信号のク
ランプされる部分が抑圧されることがないダイナミック
レンジを有する増幅器を通すことを特徴とする同期信号
分離・クランプ装置。
Clamping the video signal by a first clamp circuit using a sample pulse created from the separated synchronization signal,
This clamped video signal is supplied to a comparison means via a second clamp circuit and compared with a reference potential to separate the synchronization signal, and before the video signal is provided to the comparison means, A synchronous signal separation/clamping device characterized in that the synchronous signal is passed through an amplifier having a dynamic range such that at least a portion of the synchronous signal that is clamped by the second clamp circuit is not suppressed even if the DC potential of the synchronous signal fluctuates. .
JP59241147A 1984-11-15 1984-11-15 Synchronizing signal separating and clamping circuit Pending JPS61120585A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59241147A JPS61120585A (en) 1984-11-15 1984-11-15 Synchronizing signal separating and clamping circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59241147A JPS61120585A (en) 1984-11-15 1984-11-15 Synchronizing signal separating and clamping circuit

Publications (1)

Publication Number Publication Date
JPS61120585A true JPS61120585A (en) 1986-06-07

Family

ID=17069963

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59241147A Pending JPS61120585A (en) 1984-11-15 1984-11-15 Synchronizing signal separating and clamping circuit

Country Status (1)

Country Link
JP (1) JPS61120585A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6437171A (en) * 1987-07-31 1989-02-07 Matsushita Electric Ind Co Ltd Luminance signal correction circuit
JPS6437170A (en) * 1987-07-31 1989-02-07 Matsushita Electric Ind Co Ltd Luminance signal correction circuit

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4864827A (en) * 1971-12-08 1973-09-07
JPS54100220A (en) * 1978-01-25 1979-08-07 Hitachi Ltd Synchronous signal isolator circuit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4864827A (en) * 1971-12-08 1973-09-07
JPS54100220A (en) * 1978-01-25 1979-08-07 Hitachi Ltd Synchronous signal isolator circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6437171A (en) * 1987-07-31 1989-02-07 Matsushita Electric Ind Co Ltd Luminance signal correction circuit
JPS6437170A (en) * 1987-07-31 1989-02-07 Matsushita Electric Ind Co Ltd Luminance signal correction circuit

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