JPS61120583A - Synchronizing separation and clamping device - Google Patents

Synchronizing separation and clamping device

Info

Publication number
JPS61120583A
JPS61120583A JP59241145A JP24114584A JPS61120583A JP S61120583 A JPS61120583 A JP S61120583A JP 59241145 A JP59241145 A JP 59241145A JP 24114584 A JP24114584 A JP 24114584A JP S61120583 A JPS61120583 A JP S61120583A
Authority
JP
Japan
Prior art keywords
signal
comparator
circuit
clamp
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59241145A
Other languages
Japanese (ja)
Inventor
Kunio Sekimoto
関本 邦夫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP59241145A priority Critical patent/JPS61120583A/en
Publication of JPS61120583A publication Critical patent/JPS61120583A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To attain excellent synchronizing signal separation by amplifying a video signal before being fed to a comparator and clipping a large-level part of the video signal after being clamped. CONSTITUTION:An amplifier 4 is provided after a clamp amplifier 2, and after the tip of a synchronizing signal of an output signal is clamped by a clamp circuit 5, the clamp circuit 10 clips the large level and supplies the result to a comparator 6. When a signal 12 is fed to an input terminal 12, a signal 13 appears at the output of the circuit 5. The circuit 10 clips a part of the signal 13 larger than the E and applies it to the comparator 6. Since the portion from the B to the E of the signal 13 is applied to the signal input of the comparator 6, the level is decreased remarkably in comparison with the case of no clip, the comparator 6 acts normally, the synchronizing signal portion is amplified and the synchronizing signal is separated stably.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は、VTRやTV等映像機器で、同期信号を分離
し、信号をクランプする場合に利用可能な同期信号分離
・クランプ装置に関する。
DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a synchronization signal separation/clamping device that can be used to separate synchronization signals and clamp the signals in video equipment such as VTRs and TVs.

従来の技術 第3図に従来の同期信号分離・クランプ回路の一例を、
第4図にその各部波形を示す。第3図において、1は映
像信号入力端子、2はクランプ増幅器、3はクランプさ
れた映像信号の出力端子、6はクランプ回路、eは比較
器、Tはサンプルホールド回路、8は差動増幅器、9は
同期信号出力端子である。端子1に印加された映像信号
は、クランプ増幅器2で増幅・クランプされた後、クラ
ンプ回路5に導かれ、その同期信号の先端でクランプさ
れ、比較器6で第4図11に破線で示すような基準電位
で比較され、端子9に同期信号が得られる。一方、端子
3の出力映像信号は、サンプルホールド回路アに導かれ
、端子9の同期信号より作成されたサンプルパルスによ
り、そのペデスタル部の電位が検出され、差動増幅器8
へ導かれ、基準電位(図ではグランド)との差が増幅さ
れ、その出力電圧でクランプ増幅器2が制御される。
Conventional technology Figure 3 shows an example of a conventional synchronous signal separation/clamp circuit.
FIG. 4 shows the waveforms of each part. In FIG. 3, 1 is a video signal input terminal, 2 is a clamp amplifier, 3 is a clamped video signal output terminal, 6 is a clamp circuit, e is a comparator, T is a sample and hold circuit, 8 is a differential amplifier, 9 is a synchronization signal output terminal. The video signal applied to the terminal 1 is amplified and clamped by the clamp amplifier 2, then led to the clamp circuit 5, where it is clamped at the tip of the synchronizing signal, and the comparator 6 outputs the signal as shown by the broken line in FIG. A synchronizing signal is obtained at terminal 9. On the other hand, the output video signal from terminal 3 is guided to sample and hold circuit A, and the potential at the pedestal is detected by the sample pulse created from the synchronization signal at terminal 9, and differential amplifier 8
The difference from the reference potential (ground in the figure) is amplified, and the clamp amplifier 2 is controlled by the output voltage.

クランプ増幅器2は、例えば、増幅器8の出力電位が上
がると端子3の出力電位が下がるという様に働き、差動
増幅器8の利得が十分大きいと、サンプルホールド回路
7の出力電位と差動増幅器8の他方の入力の基準電位が
一致する様制御され、その結果として、端子3に一定電
位にクランプされた映像信号が得られる。入力映像信号
としては、スイッチで切換えられた場合等、第4図12
に示すように同期信号の直流電位が変化するような場合
も考えられる。クランプ回路5がないと、このような場
合に、比較器6の出力9に正常な同期信号が出ないため
、クランプ増幅器2のループが正常に働かず、追従しな
くなる。このためクランプ回路6を、クランプ増幅器2
のループより速い応答になるように設定し、第4図13
忙示すように応答させると、この応答後、端子9に正常
な同期信号が出力され、ループを追従させることができ
ところが、この方法では以下のような問題がある。第4
図11のAに示すように、映像信号にオーバーシュート
等が生じて、それが同期信号部に入った時、比較器6の
出力には、このオーバーシュート部分が誤って出力され
てしまい、同期信号が正常でなくなるのみならず、サン
プルホールド7で誤った点の電位が検出され、ループを
誤った方向に制御してしまい、そのため、端子3の映像
信号が乱れ、従って、端子9には更に誤った同期信号が
出力されるという悪循環を生ずる。
The clamp amplifier 2 works in such a way that, for example, when the output potential of the amplifier 8 increases, the output potential of the terminal 3 decreases, and if the gain of the differential amplifier 8 is sufficiently large, the output potential of the sample and hold circuit 7 and the differential amplifier 8 The reference potential of the other input of the two input terminals is controlled so that they match, and as a result, a video signal clamped to a constant potential is obtained at the terminal 3. The input video signal is as shown in Fig. 4-12 when switched by a switch, etc.
There may also be a case where the DC potential of the synchronizing signal changes as shown in FIG. Without the clamp circuit 5, in such a case, a normal synchronizing signal would not be output to the output 9 of the comparator 6, so the loop of the clamp amplifier 2 would not work properly and would not follow. Therefore, the clamp circuit 6 is connected to the clamp amplifier 2.
Set it so that the response is faster than the loop of
If a response is made to indicate a busy schedule, a normal synchronization signal is output to the terminal 9 after the response, and the loop can be followed. However, this method has the following problems. Fourth
As shown in A of FIG. 11, when an overshoot or the like occurs in the video signal and enters the synchronization signal section, this overshoot portion is erroneously output to the output of the comparator 6, causing the synchronization Not only does the signal become abnormal, but sample and hold 7 detects the potential at the wrong point, controlling the loop in the wrong direction, which disturbs the video signal at terminal 3. This creates a vicious cycle in which an incorrect synchronization signal is output.

これを妨ぐには、第4図11の破線で示す基準電位をで
きるだけ、同期先端に近い所に設定すれば良いが、信号
の直流変動に対し不安定になるとともに、同期先端にビ
ートノイズが乗っていると誤動作しやすくなる。
In order to prevent this, the reference potential shown by the broken line in Figure 4-11 should be set as close to the synchronization tip as possible, but it will become unstable with respect to DC fluctuations in the signal and beat noise will be added to the synchronization tip. If you do, it will be more likely to malfunction.

本発明は、映像信号にオーバーシュートやビートノイズ
があっても良好な同期分離とクランプを行乞る装置を提
供することを目的とする。
SUMMARY OF THE INVENTION An object of the present invention is to provide a device that performs good synchronization separation and clamping even if there is overshoot or beat noise in a video signal.

問題点を解決するだめの手段 本発明の同期信号分離・クランプ装置は、映像信号の大
レベル部分をクリップするクリップ回路を備えている。
Means for Solving the Problems The synchronizing signal separating/clamping device of the present invention is equipped with a clipping circuit that clips the high level portion of the video signal.

作  用 本発明は、映像信号を比較器に供する前に、増幅し、ク
ランプした後に、映像信号の大レベル部をクリップする
ので、比較器による同期信号分離時の余裕度を上げるこ
とができ、比較器の差動入力オーバーによる誤動作をな
くすことができ、良好な同期信号分離を行なうことがで
きる。
Effect: The present invention amplifies and clamps the video signal before providing it to the comparator, and then clips the high level part of the video signal, so it is possible to increase the margin when separating the synchronizing signal by the comparator. Malfunctions due to over differential input of the comparator can be eliminated, and good synchronization signal separation can be achieved.

実施例 第1図に本発明の一実施例のブロック図、第2図にその
動作を説明するだめの信号波形を示す。
Embodiment FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 shows signal waveforms for explaining its operation.

第1図において、第3図と同じ番号は同じものを表、表
わし、同じ動作をする。4は増幅器、1oはクリップ回
路である。第3図で述べた問題点を解決する方法として
、比較器6に映像信号を供する前に映像信号を増幅し、
基準電位をオーバーシュートより下で同期信号部のビー
トより上の部分に設□定し基準電位との比較時に余裕を
もたせる方法がある。この時、比較器6の入力へは過大
な信号が加わることになる。比較器の差動入力レベルに
は制限があり、これを越えると、基準入力側が振られた
り、出力が歪んだり、正常な動作をしなくなる。以上の
点より、本発明は、クランプ増幅器2の後に、増幅器4
を設け、七の出力信号の同期信号の先端をクランプ回路
6でクランプした後、クリップ回路10でその大レベル
部をクリップしてから比較器6へ供している。入力端子
1に第2図12に示すような信号が印加さ几た時、クラ
ンプ回路6の出力には同図13のような信号が現れる。
In FIG. 1, the same numbers as in FIG. 3 represent the same things and perform the same operations. 4 is an amplifier, and 1o is a clip circuit. As a method to solve the problem described in FIG. 3, the video signal is amplified before being provided to the comparator 6,
There is a method of setting the reference potential below the overshoot and above the beat of the synchronizing signal section to provide some margin when comparing with the reference potential. At this time, an excessive signal is applied to the input of the comparator 6. There is a limit to the differential input level of the comparator, and if this limit is exceeded, the reference input side will be swayed, the output will be distorted, and normal operation will not occur. From the above points, the present invention provides an amplifier 4 after the clamp amplifier 2.
A clamp circuit 6 clamps the leading end of the synchronizing signal of the output signal No. 7, and a clip circuit 10 clips the high level portion before supplying it to the comparator 6. When a signal as shown in FIG. 2 is applied to the input terminal 1, a signal as shown in FIG. 13 appears at the output of the clamp circuit 6.

同図13でEより大レベルの部分をクリップ回路1oで
クリップして比較器eに供する。こうすると、比較器6
の信号入力へは、第2図13のBからEの部分のみ印加
されるので、クリップしない場合(13のBからC)に
比べ大幅に小さくすることができ、比較器6は正常に働
くとともに、同期信号部は、第3図の場合に比べ増幅さ
れ、安定に同期信号を分離することができる。
In FIG. 13, a portion having a higher level than E is clipped by a clipping circuit 1o and provided to a comparator e. In this way, comparator 6
Since only the portions B to E in Fig. 2 13 are applied to the signal input of , it can be much smaller than in the case of no clipping (B to C in 13), and the comparator 6 functions normally and , the synchronizing signal section is amplified compared to the case of FIG. 3, and the synchronizing signal can be stably separated.

なお本実施例では、クランプ回路5は同期信号の先端を
クランプするもので説明したが、ペデスタルをクランプ
するもの他どんな方法でも良い。
In this embodiment, the clamp circuit 5 has been described as one that clamps the leading end of the synchronizing signal, but any other method other than one that clamps the pedestal may be used.

また、クランプ増幅器2のループとクランプ回路Sの2
つのクランプをもつものでなく、単に1つのクランプ回
路(ループ形式′Cあるかないかを問わず)に°よるも
のにも本発明は有効である。更に、クリップのレベルは
、第2図13のEに限らず、同期信号が分離でき、比較
器60入カレベルが過大にならない点ならどこでも良い
In addition, the loop of the clamp amplifier 2 and the 2 loop of the clamp circuit S
The present invention is also effective in systems that do not have two clamps, but simply rely on one clamp circuit (regardless of loop type 'C' or not). Further, the clipping level is not limited to E in FIG. 2, but may be any level as long as the synchronizing signal can be separated and the input level of the comparator 60 does not become excessive.

発明の効果 以上のよう罠、本発明によれば、入力映像信号の電位が
変化した場合や、オーバーシュート、ビートノイズがあ
る場合にも良好な同期信号の分離とクランプを行ない得
る。
Effects of the Invention As described above, according to the present invention, it is possible to perform good synchronization signal separation and clamping even when the potential of the input video signal changes, or when there is overshoot or beat noise.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例のブロック図、第2図はその
動作を説明するための信号波形図、第3図は従来例を示
すブロック図、第4図はその各部波形図である。 2・・・・・・クランプ増幅器、4・・・・・・増幅器
、5・・・・・・クランプ回路、6・・・・・・比較器
、7・・・・・・サンプルホールド回路、8・・・・・
・差動増幅器、1o・・・・・・クリップ回路。 代理人の氏名 弁理士 中 尾 敏 男 ほか1名3図 4図
Fig. 1 is a block diagram of an embodiment of the present invention, Fig. 2 is a signal waveform diagram for explaining its operation, Fig. 3 is a block diagram showing a conventional example, and Fig. 4 is a waveform diagram of each part thereof. . 2... Clamp amplifier, 4... Amplifier, 5... Clamp circuit, 6... Comparator, 7... Sample hold circuit, 8...
・Differential amplifier, 1o... Clip circuit. Name of agent: Patent attorney Toshio Nakao and 1 other person Figures 3 and 4

Claims (1)

【特許請求の範囲】[Claims] 映像信号をクランプ回路によりクランプし、このクラン
プされた映像信号を比較手段により基準電位と比較して
同期信号を分離するに際し、映像信号を前記比較手段に
供する前に、映像信号の大レベル部分をクリップ回路に
よりクリップするように構成したことを特徴とする同期
信号分離・クランプ装置。
When a video signal is clamped by a clamp circuit and the clamped video signal is compared with a reference potential by a comparison means to separate a synchronization signal, a large level portion of the video signal is A synchronizing signal separating/clamping device characterized in that it is configured to be clipped by a clipping circuit.
JP59241145A 1984-11-15 1984-11-15 Synchronizing separation and clamping device Pending JPS61120583A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59241145A JPS61120583A (en) 1984-11-15 1984-11-15 Synchronizing separation and clamping device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59241145A JPS61120583A (en) 1984-11-15 1984-11-15 Synchronizing separation and clamping device

Publications (1)

Publication Number Publication Date
JPS61120583A true JPS61120583A (en) 1986-06-07

Family

ID=17069935

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59241145A Pending JPS61120583A (en) 1984-11-15 1984-11-15 Synchronizing separation and clamping device

Country Status (1)

Country Link
JP (1) JPS61120583A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04229777A (en) * 1990-04-30 1992-08-19 Thomson Consumer Electron Inc Synchronizing signal separator

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54100220A (en) * 1978-01-25 1979-08-07 Hitachi Ltd Synchronous signal isolator circuit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54100220A (en) * 1978-01-25 1979-08-07 Hitachi Ltd Synchronous signal isolator circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04229777A (en) * 1990-04-30 1992-08-19 Thomson Consumer Electron Inc Synchronizing signal separator

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