JPS62272766A - Video signal processor - Google Patents

Abstract

PURPOSE:To extremely stablly and exactly remove a sag from an image signal by inverting relatively a revel detection signal and a video signal in the leading end part of a synchronizing signal, and adding them with each other. CONSTITUTION:In case a signal having a sag like a signal (a) is inputted to an input terminal 1, an adder 3 adds the input signal and a signal outputted from a DC amplifier 6, and a DC amplifier 4 inverts and amplifies the resulting signal and outputs to an output terminal 2 and to a SYNC synchronism, tip detection circuit 5. The circuit 5 detects the DC level and the sag of the SYNC tip of the output signal, and inputs the result to the DC amplifier 6. The DC amplifier 6 amplifies said DC level and sag, and outputs them to the adder 3. The DC signal (figure (b)) is feedbacked to the adder 3 hence comes lower if the DC level of the input signal comes higher. Therefore, the input DC level and the output DC level of the DC inversion amplifier 4 come stable. Also, the sag inputted to the adder 3 comes to have its polarity opposite that of the input signal after being subjected to the DC amplifier 4.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a video signal processing device for removing so-called sag in a video signal caused by loss of low frequency information.

[Prior art] Conventionally, in the method of removing this type of sag, the 5YNC (synchronization) chip of the video signal (the leading edge of the synchronization signal) is
There are methods such as diode clamping and pulse clamping using 5YNC or its back porch.

[Problems to be Solved by the Invention] However, in the former method, there is a problem that the 5YNC signal portion is crushed, and in the latter method, the 5YNC signal must be separated in advance to create a clamp pulse. Therefore, if there is a sag in the original human input signal, the 5YNC signal cannot be separated correctly,
As a result, a phase shift occurs in the clamping pulse, and there is a problem in that the low frequency signal cannot be correctly reproduced with respect to the image signal.

An object of the present invention is to provide a video signal processing device that solves the above problems.

[Means for Solving the Problems] The present invention includes a detection means for detecting the level of the leading edge of a synchronization signal in a video signal, and a detection signal from the detection means and a video signal that are relatively inverted and added. and means.

[Function] According to the present invention, by relatively inverting and adding the level detection signal at the leading end of the synchronizing signal and the video signal,
To surely suppress sag without adversely affecting a video signal.

[Example] The present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram showing an example of the basic configuration of main parts of a video signal processing circuit according to the present invention.

1 is an input terminal to which a video signal is input manually. 2 is an output terminal, 3 is an input video signal, and a DC amplifier 6, which will be described later.
This is an adder that adds and outputs the signals from and at a constant rate.

4 is an inverting amplifier directly connected to DC, and 5 is a 5YNC chip that detects the voltage at the tip of the 5YNC signal (SYNC chip) in the output video signal of the inverting amplifier 4 and holds that voltage until the next 5YNC No. 4 comes. Detection circuit, 6 is 5
This is a DC amplifier that amplifies the voltage of the 5YNC chip detected by the YNC chip detection circuit 5.

In such a configuration, when a signal with a sag such as signal a shown in FIG. 2 is input to the input terminal 1, the adder 3 combines the input signal with the signal output from the DC amplifier 6. The DC amplifier 4 inverts and amplifies the signal, outputs it to the output terminal 2, and simultaneously sends it to the 5YNC chip detection circuit 5. The 5YNC chip detection circuit 5 detects the DC level and sag of the 5YNC chip of the output signal and inputs it to the DC amplifier 6. The DC amplifier 6 amplifies the DC level and the sag and inputs it to the adder 3.

The DC signal input to the adder 3 (Fig. 2b) is fed back so that it decreases as the DC level of the human signal increases, so the input DC level and output DC level of the DC inverting amplifier 4 are becomes stable. Further, the sag input to the adder 3 passes through the DC amplifier 4, so that the sag becomes opposite in polarity to the sag of the human input signal. Therefore, the sag remaining in the output signal of the DC inverting amplifier 4 (Fig. 2C) is improved to 1/1 of the combined gain of the DC inverting amplifier 4 and the C amplifier 6, and the sag remains in the output signal of the DC inverting amplifier 4 and the C amplifier 6. etc. will be sent to.

As described above, by feeding back the sag detected from the 5YNC chip to the input stage, the sag that has occurred in the video signal can be improved, and by feeding back the system to DC, bias fluctuations due to temperature fluctuations in the video signal amplifier circuit, etc. can be improved.

FIG. 3 shows a specific embodiment of the invention.

A signal input to the input terminal 11 is inputted to one input terminal of an adder 3 consisting of resistors 17 and 18 via an emitter follower 7, and is inputted to the other input terminal of the adder 3.
It is added to the source follower output signal from ET27.

The added signals are Tr19, Tr22, resistors 20, 2
Amplified by a DC inverting amplifier 4 consisting of Tr.
The signal is outputted to the output terminal 29 by the emitter follower from 22 and simultaneously inputted to the 5YNC chip detection circuit 5. In this 5YNC chip detection circuit 5, a diode 2
4. The peak level of the inverted video signal from the inverting amplifier 4, that is, 5YNC, is determined by the resistor 26 and capacitor 25.
The leading value of the signal is detected and inputted to the gate of FET27. The FET 27 serves as a source follower and supplies an output signal to the adder 3. According to this circuit, the DC amplifier 6 shown in FIG. 1 can be omitted.

FIG. 4 shows another specific embodiment of the invention.

Items with the same reference numbers as in Figure 3 have the same function.
Since the steps up to Tr22 are the same as those shown in FIG. 3, a description will be added below of the emitter output of Tr22. The inverted video signal Y+S output from the emitter of Tr22 is input to a peak detection circuit composed of an OP amplifier 30, a diode 24, a resistor 26, and a capacitor 25 to detect a 5YNC chip signal, and this detection signal is sent to an OP amplifier 31. , reference voltage 35, resistor 34 (resistance value R34), and capacitor 33 (resistance value R33).

[Effects of the Invention] As explained above, sag can be removed from an image signal extremely stably and reliably.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the main part configuration of a video signal processing circuit according to the present invention, FIG. 2 is a diagram showing signal waveforms at each point in FIG. 1, and FIG. 3 is a diagram showing a specific embodiment of the present invention. Circuit Diagram FIG. 4 is a circuit diagram of another specific embodiment of the present invention. 1...Input terminal, 2...Output terminal, 3...Adder, 4...DC inverting amplifier ψ' Fig. 1

Claims (1)

[Claims] The present invention includes a detection means for detecting the level of the leading edge of a synchronizing signal in a video signal, and a means for relatively inverting and adding the detection signal from the detection means and the video signal. Features of video signal processing device.