JPS6318779A - Separating device for horizontal synchronizing signal - Google Patents
Separating device for horizontal synchronizing signalInfo
- Publication number
- JPS6318779A JPS6318779A JP16243086A JP16243086A JPS6318779A JP S6318779 A JPS6318779 A JP S6318779A JP 16243086 A JP16243086 A JP 16243086A JP 16243086 A JP16243086 A JP 16243086A JP S6318779 A JPS6318779 A JP S6318779A
- Authority
- JP
- Japan
- Prior art keywords
- synchronizing signal
- synchronization signal
- output
- monostable multivibrator
- horizontal synchronizing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000002131 composite material Substances 0.000 claims abstract description 19
- 230000001960 triggered effect Effects 0.000 claims abstract description 7
- 238000000926 separation method Methods 0.000 claims description 21
- 230000001934 delay Effects 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000004913 activation Effects 0.000 description 1
- 230000003111 delayed effect Effects 0.000 description 1
- 239000000284 extract Substances 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
Landscapes
- Synchronizing For Television (AREA)
- Manipulation Of Pulses (AREA)
Abstract
Description
【発明の詳細な説明】
発明の目的
[産業上の利用分野]
本発明は、映像信号に多重している複合同期信号から、
水平同期信号を分離し、取り出す水平同期信号分離装置
に関する。[Detailed Description of the Invention] Purpose of the Invention [Industrial Field of Application] The present invention provides a method for decoding a composite synchronization signal multiplexed onto a video signal.
The present invention relates to a horizontal synchronization signal separation device that separates and extracts horizontal synchronization signals.
[従来の技術]
従来、NTSC方式では垂直同期期間の複合同期信号か
ら水平同期信号を分離し、垂直同期期間であっても水平
同期を保ち、また、インクレースを確実としてベアリン
グ現象の抑制を行っている。[Prior art] Conventionally, in the NTSC system, the horizontal synchronization signal is separated from the composite synchronization signal in the vertical synchronization period, horizontal synchronization is maintained even during the vertical synchronization period, and bearing phenomena are suppressed by ensuring increment. ing.
上記の動作を行う回路として、従来PLL (ptla
se I 0Cked l 00p)回路あるいは
2つの単安定マルチバイブレータを用いる水平同期信号
分離装置が周知でおる。PIL回路では、雑音による水
平同期信号の乱れがあろうとも、その変動幅が一定範囲
内であれば位相差の補正がなされて水平同期が保たれる
。A conventional PLL (ptla
Horizontal synchronization signal separation devices using a se I 0Cked l 00p circuit or two monostable multivibrators are well known. In the PIL circuit, even if the horizontal synchronization signal is disturbed by noise, if the fluctuation range is within a certain range, the phase difference is corrected and horizontal synchronization is maintained.
また、2つの単安定マルチバイブレータを用いる装置に
あっては、一方の単安定マルヂパイブレ−夕が等化パル
スによる再トリガを不能として作動し、その出力で他方
の単安定マルチバイブレータを1〜リガすることで水平
同明信号を発生さけ、等化パルスおよび214t ?’
iの除去を)構成している。In addition, in a device using two monostable multivibrators, one monostable multivibrator operates with retriggering disabled by the equalization pulse, and uses its output to trigger the other monostable multivibrator. This avoids generating a horizontal doubling signal, and the equalization pulse and 214t? '
(removal of i).
[発明が解決しようとする問題点]
しかし、上記のごとき水平同期信号分離装置におっても
未だに十分なものではなく、次のような問題点があった
。[Problems to be Solved by the Invention] However, the horizontal synchronizing signal separation device as described above is still not sufficient and has the following problems.
PLL回路を利用する水平同期信号分離装置は、PLL
回路自体の構成が複雑で装置の小型、軽量化を阻害する
要因となり、また高コスト化を招来していた。A horizontal synchronization signal separation device that uses a PLL circuit is a PLL circuit.
The circuit itself has a complicated configuration, which hinders the reduction in size and weight of the device, and also increases costs.
一方、2つの単安定マルチバイブレータを利用する水平
同期信号分離装置は、上記のような複雑な回路構成を必
要とけず小型、軽量、かつ安価な装置となるが、単安定
マルチバイブレータの発振011間が周囲の湿度等によ
って変動するため充分な雑音除去が不可能となる。すな
わら、一方の単安定マルチバイブレータが発(辰信号を
出力しており、再1〜リガ不能の期間に重畳した雑音は
、次段の単安定マルチバイブレータの1〜リガに影響し
ないが、この期間が温度により変動するため温度補償が
困難となる。On the other hand, a horizontal synchronization signal separation device that uses two monostable multivibrators does not require the above-mentioned complicated circuit configuration and is small, lightweight, and inexpensive. Since the noise varies depending on the surrounding humidity, etc., sufficient noise removal becomes impossible. In other words, one monostable multivibrator is outputting a signal, and the noise superimposed during the period in which re-registration is not possible does not affect the re-registration of the monostable multivibrator in the next stage. Since this period varies depending on the temperature, temperature compensation becomes difficult.
本発明は、上記問題点を解決するためになされたもので
、簡単な回路構成で小型、軽量、かつ安価であり、しか
も安定して高精度に雑音除去を達成する水平同期信号分
離装置を提供することをその目的としている。The present invention has been made to solve the above problems, and provides a horizontal synchronization signal separation device that has a simple circuit configuration, is small, lightweight, and inexpensive, and that achieves stable and highly accurate noise removal. Its purpose is to.
発明の構成
[問題点を解決するための手段]
上記問題点を解決するための本発明の水平同期信号分離
’l置は、複合同期信号中に含まれる雑音を除去しつ彎
、水平同期信号を分mtrる水平同明信号分離装置にお
いて、前記複合同明信号を入力し、該複合同期信号に含
まれる等化パルスのパルス幅より短い時間だけ該複合同
期信号を遅延される遅延回路と、該遅延回路の出力と前
記複合同明信号との論理積を演算する論理積演算回路と
、該論理積演算回路の出力によりトリガされ、水平同期
信号の周期より短く1/2周期より長い期間の出力を発
生する第1単安定マルチバイブレータと、該第1単安定
マルチバイブレータの出力によりトリガされ、水平同期
信号のパルス幅の出力を発生する第2単安定マルチバイ
ブレータとを備えることを特徴とする。Structure of the Invention [Means for Solving the Problems] In order to solve the above-mentioned problems, the horizontal synchronization signal separation arrangement of the present invention removes the noise contained in the composite synchronization signal and separates the horizontal synchronization signal. a horizontal dome signal separation device for mtr, which receives the composite dome signal and delays the composite synchronization signal by a time shorter than the pulse width of the equalization pulse included in the composite synchronization signal; an AND operation circuit that calculates an AND between the output of the delay circuit and the composite same signal; and an AND operation circuit that is triggered by the output of the AND operation circuit, and which is shorter than the period of the horizontal synchronization signal and longer than 1/2 period. A first monostable multivibrator that generates an output; and a second monostable multivibrator that is triggered by the output of the first monostable multivibrator and generates an output with a pulse width of a horizontal synchronization signal. .
[作用]
本発明の水平同期信号分離装置は、複合同期信号を遅延
回路によって等化パルスのパルス幅より短い時間だけ遅
延した信号と元の複合同期信号とを論理積演算回路によ
って積算し、こうして得られた信号によって水平同期信
号の周期THより短< T H/ 2より長い期間の出
力を発生する第1単安定マルチバイブレータをトリガす
る。そして、この第1単安定マルチバイブレータの出力
により水平同期信号のパルス幅の出力を発生する第2
ti安定マルヂバ、イブレータをトリガして水平同期信
号を1qる。[Operation] The horizontal synchronizing signal separation device of the present invention integrates the composite synchronizing signal delayed by a delay circuit by a time shorter than the pulse width of the equalization pulse and the original composite synchronizing signal using an AND operation circuit, and thus The obtained signal triggers a first monostable multivibrator that generates an output for a period shorter than the period TH of the horizontal synchronization signal and longer than TH/2. A second monostable multivibrator generates an output with the pulse width of the horizontal synchronization signal by the output of the first monostable multivibrator.
ti Stable Mardiver triggers the ibrator to generate 1q horizontal synchronization signal.
以下、本発明をより具体的に説明するために実施例を挙
げて説明する。EXAMPLES Hereinafter, in order to explain the present invention more specifically, examples will be given and explained.
[実施例]
第1図は実施例の水平同期信号分離装置の電気回路ブロ
ック図、第2図は第1図中の信号線に現われる電圧波形
を横軸に時間をとって表わしたタイミングヂャートであ
る。[Example] Fig. 1 is an electric circuit block diagram of a horizontal synchronizing signal separation device according to an embodiment, and Fig. 2 is a timing chart in which the voltage waveform appearing on the signal line in Fig. 1 is plotted against time on the horizontal axis. It is.
図示のように、同期信号を多重した映像信号は同期分離
回路2に与えられて黒レベルに割当てられた同期信号の
みが取出される(第2図(A))。As shown in the figure, a video signal multiplexed with synchronization signals is applied to a synchronization separation circuit 2, and only the synchronization signal assigned to the black level is extracted (FIG. 2(A)).
このとき、第2図<A)に示すように、映像信号に同期
信号と同レベルの雑音dが混在している可能性がある。At this time, as shown in FIG. 2<A), there is a possibility that the video signal contains noise d having the same level as the synchronization signal.
ただし、映像信号に対して雑音の大ぎなものは、通常図
示しない前段に設けられる周知のドロップアウト補償回
路で完全に除去されるため、図のように極めて鋭いパル
ス的な雑音dのみとなる。この信@(A)は、直接およ
び遅延回路4を介してAND回路6へ入力され、論理積
が取られる。遅延回路4の遅延時間TDは等化パルスの
パルス幅(通常的2.5μs)よりも短かく(第2図(
B))、従ってAND回路6での積咋結果は第2図(C
)に示すごとく複合同期信号(B)と同一位相で単に全
てのパルス幅がTDだG−J短くなった信号となる。す
なわら、前述した鋭いパルスである雑音dは時間TDは
ど艮い時間存在するものではなく、論理積演締で確実に
除去されることになる。こうして1ηられた信号(C)
の立上がり点で第1段の単安定マルチバイブレータ8が
トリガされ時間1−wの発娠を繰り返ず(第2図(D)
)。時間Twとは、水平同期信号の出力周期をT I−
1とするとき1/2TI−1<Tw <THなる関係を
有するもので、周期THの1/2毎に挿入されている複
合同期信号中の等化パルスPおよび垂直同期パルスQに
よる再1〜リガを不能としている。従って、信号(D>
は水平同期信号と全く同一周期で発生ずるパルス列とな
り、単にそのパルス幅Twのみが水平同期信号と異なる
ものであることが明らかである。そこで、この第1段の
単安定マルチバイブレータ8の出力(D)により、出力
が水平同期信号のパルス幅と同一(約5μs)の第2段
の単安定マルチバイブレータ10を1へリガし、最終的
な水平同期信号Eを1するのである。However, noise that is too large for the video signal is usually completely removed by a well-known dropout compensation circuit (not shown) provided at the previous stage, so that only extremely sharp pulse-like noise d is left as shown in the figure. This signal @(A) is directly inputted to the AND circuit 6 via the delay circuit 4, and a logical product is taken. The delay time TD of the delay circuit 4 is shorter than the pulse width of the equalization pulse (typically 2.5 μs) (see Fig. 2).
B)), therefore, the multiplication result in the AND circuit 6 is shown in Figure 2 (C
), it is a signal that has the same phase as the composite synchronizing signal (B) and simply has all pulse widths TD (G-J) shorter. In other words, the noise d, which is the sharp pulse described above, does not exist at any time during the time TD, and can be reliably removed by the logical product operation. The signal (C) that has been reduced by 1η in this way
The first stage monostable multivibrator 8 is triggered at the rising point of , and the activation for time 1-w is not repeated (Fig. 2 (D)).
). The time Tw is the output period of the horizontal synchronization signal T I-
1, it has the relationship 1/2TI-1<Tw<TH, and the equalization pulse P and vertical synchronization pulse Q in the composite synchronization signal inserted every 1/2 of the period TH re-1 to It makes Riga impossible. Therefore, the signal (D>
is a pulse train generated at exactly the same period as the horizontal synchronizing signal, and it is clear that only the pulse width Tw is different from the horizontal synchronizing signal. Therefore, the output (D) of the first stage monostable multivibrator 8 triggers the second stage monostable multivibrator 10 whose output is the same as the pulse width of the horizontal synchronizing signal (approximately 5 μs) to 1, and the final The horizontal synchronization signal E is set to 1.
上記実施例の水平同明信号分離装置によれば、同明信号
に混在する雑音dは論理積を取る簡素なAND回路6に
よって確実に除去され、かつ、後段の2つの単安定マル
チバイブレータによって等化パルスの除去がなされる。According to the horizontal dome signal separation device of the above embodiment, the noise d mixed in the dome signal is reliably removed by the simple AND circuit 6 that performs logical product, and is equalized by the two monostable multivibrators in the subsequent stage. The oxidation pulse is removed.
すなわら、2つの単安定マルチバイブレータは、単に等
化パルスを除去するのみであるため、その発]辰期間の
温度補償を厳密とする必要もない。従って、本実施例の
水平同期信号分離装置は、簡略的で小型、軽量、安価な
回路構成であるにも拘らず、その雑音除去および水平同
期信号の分離は湿度に関係けず高精度に実行されること
となり、本水平同期信号分離装置を使用して映像信号を
再生するならば、極めて安定した鮮明な画像を得ること
ができる。In other words, since the two monostable multivibrators simply remove the equalization pulse, there is no need for strict temperature compensation during their emission period. Therefore, although the horizontal synchronization signal separation device of this embodiment has a simple, compact, lightweight, and inexpensive circuit configuration, its noise removal and horizontal synchronization signal separation are performed with high precision regardless of humidity. Therefore, if a video signal is reproduced using this horizontal synchronization signal separation device, an extremely stable and clear image can be obtained.
以上、本発明の一実施例について説明したが、本発明は
こうした実施例に何等限定されるものではなく、その要
旨を逸脱しない範囲において種々なる態様で実施しえる
ことは勿論である。Although one embodiment of the present invention has been described above, the present invention is not limited to this embodiment in any way, and it goes without saying that the present invention can be implemented in various forms without departing from the spirit thereof.
発明の効果
以上、実施例を挙げて詳述したように本発明の水平同明
信号分離装置は、論理積演算手段や単安定マルチバイブ
レータ等の簡素な電気素子を用いて小型、軽量、安価に
構成される。しかも、その雑音除去能力は極めて安定、
高精度であり、水平同期信号を確実に分離する。As described in detail with reference to the embodiments, the horizontal dosing signal separation device of the present invention is small, lightweight, and inexpensive by using simple electric elements such as AND operation means and a monostable multivibrator. configured. Moreover, its noise removal ability is extremely stable.
High accuracy and reliable separation of horizontal synchronization signals.
第1図は実施例である水平同期信号分離装置のブロック
回路図、第2図(A)〜(E)は同実施例の各ラインの
電圧波形を表わずタイミングヂャートを示している。
2・・・同期分離回路
4・・・遅延回路
6・・・AND回路FIG. 1 is a block circuit diagram of a horizontal synchronizing signal separation device according to an embodiment, and FIGS. 2(A) to 2(E) show timing charts without representing the voltage waveforms of each line of the same embodiment. 2...Synchronization separation circuit 4...Delay circuit 6...AND circuit
Claims (1)
信号を分離する水平同期信号分離装置において、 前記複合同期信号を入力し、該複合同期信号に含まれる
等化パルスのパルス幅より短い時間だけ該複合同期信号
を遅延される遅延回路と、 該遅延回路の出力と前記複合同期信号との論理積を演算
する論理積演算回路と、 該論理積演算回路の出力によりトリガされ、水平同期信
号の周期より短く1/2周期より長い期間の出力を発生
する第1単安定マルチバイブレータと、 該第1単安定マルチバイブレータの出力によりトリガさ
れ、水平同期信号のパルス幅の出力を発生する第2単安
定マルチバイブレータと、 を備えることを特徴とする水平同期信号分離装置。[Scope of Claims] A horizontal synchronization signal separation device that separates a horizontal synchronization signal while removing noise contained in the composite synchronization signal, the said composite synchronization signal being input, and the equalization pulse contained in the composite synchronization signal being input. a delay circuit that delays the composite synchronization signal by a time shorter than the pulse width of the composite synchronization signal; an AND operation circuit that performs an AND operation between the output of the delay circuit and the composite synchronization signal; a first monostable multivibrator that is triggered and generates an output with a period shorter than the period of the horizontal synchronization signal and longer than 1/2 period; A horizontal synchronization signal separation device comprising: a second monostable multivibrator that generates an output;
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP16243086A JPS6318779A (en) | 1986-07-10 | 1986-07-10 | Separating device for horizontal synchronizing signal |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP16243086A JPS6318779A (en) | 1986-07-10 | 1986-07-10 | Separating device for horizontal synchronizing signal |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6318779A true JPS6318779A (en) | 1988-01-26 |
Family
ID=15754456
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP16243086A Pending JPS6318779A (en) | 1986-07-10 | 1986-07-10 | Separating device for horizontal synchronizing signal |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6318779A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02135995A (en) * | 1988-11-17 | 1990-05-24 | Sony Corp | Television receiver |
JPH037419A (en) * | 1989-06-05 | 1991-01-14 | Victor Co Of Japan Ltd | Frequency discrimination circuit |
-
1986
- 1986-07-10 JP JP16243086A patent/JPS6318779A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02135995A (en) * | 1988-11-17 | 1990-05-24 | Sony Corp | Television receiver |
JPH037419A (en) * | 1989-06-05 | 1991-01-14 | Victor Co Of Japan Ltd | Frequency discrimination circuit |
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