JPH06327023A - Burst gate pulse generating circuit - Google Patents

Abstract

PURPOSE:To provide a burst gate pulse generating circuit in which a burst gate pulse is generated only after a horizontal synchronizing signal. CONSTITUTION:Monomulches 2 and 3 generate the burst gate pulse by a composite synchronizing signal. An AND gate 8 outputs only an edge pulse generated by the horizontal synchronizing signal from both a pulse whose leading edge is present between the tailing edge of an equalized pulse and the tailing edge of the horizontal synchronizing signal, and whose tailing edge is present behind the tailing edge of the horizontal synchronizing signal, which is outputted from the monostable multivibrator 6, and an edge pulse generated by the failing edge of the composite synchronizing signal, which is outputted from the monostable multivibrator 7. A monostable multivibrator 9 generates a pulse whose width is wider than the burst gate pulse by the edge pulse. Then, an AND gate 10 obtains the AND of the output pulse of the monostable multivibrator 9 and the output pulse of the monostable multivibrator 3, and outputs the burst gate pulse only after the horizontal synchronizing signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a burst gate pulse generation circuit for generating a burst gate pulse for gating a burst period in a composite video signal in a television signal.

[0002]

2. Description of the Related Art It is well known that a burst gate pulse corresponding to a burst period is required when constructing a 3.58 MHz PLL circuit that is phase locked to a burst signal included in a composite video signal.

FIG. 5 is a block diagram showing an example of a conventional burst gate pulse generation circuit. The operation of the burst gate pulse circuit will be described with reference to the waveform chart shown in FIG. In FIG. 5, a sync signal separated from the composite video signal is input to the input terminal 1. The sync signal includes a horizontal sync signal, an equalization pulse, and a vertical sync signal, and is hereinafter referred to as a composite sync signal. In FIG.
(A) shows a composite video signal centering on the horizontal blanking period, and (B) shows a composite sync signal (positive polarity) separated by synchronization. When a composite sync signal as shown in FIG. 6 (B) is input to the input terminal 1, the monostable multivibrator (hereinafter referred to as mono-multi) 2 is triggered at the leading edge of the composite sync signal, and FIG. The pulse shown in () is output.

This pulse is input to the monomulti 3, the monomulti 3 is triggered by the trailing edge of the pulse, and the pulse shown in FIG. 6 (D) is output to the output terminal 4. The pulse widths generated in the monomultis 2 and 3 are adjusted so that this pulse has the same period as the burst signal indicated by hatching in FIG. 6 (A). The mono-multi 2 may be an operation triggered by the trailing edge of the composite sync signal. In this case, the output of the mono-multi 2 has a narrow pulse width, as shown in FIG. 6 (C) '. The conventional burst gate pulse generation circuit generates the burst gate pulse by the above configuration and operation.

[0005]

As described above, the composite sync signal includes the horizontal sync signal, the equalization pulse, and the vertical sync signal. Since the burst signal is inserted only after the horizontal synchronizing signal, the conventional burst gate pulse generation circuit described above has a problem that the burst gate pulse is generated even after the equalizing pulse and the vertical synchronizing signal. The present invention has been made in view of such problems, and an object thereof is to provide a burst gate pulse generation circuit capable of generating a burst gate pulse only after a horizontal synchronizing signal.

[0006]

In order to solve the above-mentioned problems of the prior art, the present invention provides a burst gate pulse generating circuit for generating a burst gate pulse from a composite synchronizing signal in a television signal, which comprises (1) input Means for generating a burst gate pulse from the composite sync signal, means for generating an edge pulse rising only at the trailing edge of the horizontal sync signal in the composite sync signal, and the burst gate pulse triggered by the edge pulse And a means for generating a third pulse having a wider pulse width, and a means for passing only the burst gate pulse generated after the horizontal synchronizing signal by the burst gate pulse and the third pulse. A burst gate pulse generation circuit characterized by
(2) Means for generating an edge pulse rising only at the trailing edge of the horizontal synchronizing signal in the composite synchronizing signal, and means for generating a burst gate pulse only after the horizontal synchronizing signal based on the edge pulse. (3) means for generating a burst gate pulse from an input composite synchronizing signal, and a trailing edge of an equalizing pulse in the composite synchronizing signal Means for generating a first pulse having a leading edge between the trailing edge of the sync signal and a trailing edge after the trailing edge of the horizontal sync signal; and a trigger for inputting the composite sync signal to an input terminal By inputting the first pulse to the enable terminal, a third pulse having a pulse width wider than that of the burst gate pulse rising only at the trailing edge of the horizontal synchronizing signal. Burst gate pulse, and means for passing only the burst gate pulse generated after the horizontal synchronizing signal by the burst gate pulse and the third pulse. (4) a generation circuit is provided, wherein (4) there is a leading edge between a trailing edge of the equalization pulse in the composite sync signal and a trailing edge of the horizontal sync signal, and a trailing edge after the trailing edge of the horizontal sync signal; A means for generating one pulse and a fourth pulse which rises only at a trailing edge of the horizontal synchronizing signal by inputting the composite synchronizing signal to an input terminal and inputting the first pulse to a trigger enable terminal. And a means for generating a burst gate pulse only after the horizontal synchronizing signal based on the fourth pulse. There is provided a preparative gate pulse generation circuit.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A burst gate pulse generation circuit according to the present invention will be described below with reference to the accompanying drawings. 1 is a block diagram showing a first embodiment of a burst gate pulse generation circuit of the present invention, FIG. 2 is a block diagram showing a second embodiment of the burst gate pulse generation circuit of the present invention, and FIG. 3 is a burst gate of the present invention. FIG. 4 is a waveform diagram for explaining the operation of the pulse generation circuit, and FIG. 4 is a partial block diagram showing another embodiment of the burst gate pulse generation circuit of the present invention. 1 and 2, the same parts as those in FIG. 5 are designated by the same reference numerals.

First, the configuration and operation of the first embodiment shown in FIG. 1 will be described with reference to the waveform chart shown in FIG. Figure 3
, (A) to (C) are composite sync signals,
(A) shows a horizontal synchronizing signal, (B) shows an equalizing pulse, and (C) shows a vertical synchronizing signal with positive polarity. In FIG. 1, a composite sync signal (which is a positive polarity input) is input to the input terminal 1, and the monomultis 2 and 3 output the burst gate pulse shown in FIG. 3D by the same operation as in FIG. In this case, the mono-multi 2 operates at the rising edge (leading edge) and the mono-multi 3 operates at the trailing edge of the input pulse. The composite sync signal is also input to the mono-multi 5, and the output of the mono-multi 6 is controlled by the gate amount shown in FIG. 3E depending on the delay amount setting by the mono-multi 5 and the pulse width setting by the mono-multi 6. A pulse is obtained.

In the gate pulse shown in FIG. 3 (E), the leading edge is the trailing edge of the equalizing pulse shown in FIG. 3 (B).
It is between the trailing edge of the horizontal synchronizing signal shown in (A) and the trailing edge is after the trailing edge of the horizontal synchronizing signal. On the other hand, the composite sync signal is also input to the mono-multi 7, and the mono-multi 7 is triggered by the falling edge of the composite sync signal and outputs a pulse having a sufficiently narrow width. That is,
Performs falling edge pulse generation operation. AND gate 8
The edge pulse and the gate pulse output from the monomulti 6 are input to.

The edge pulse output from the monomulti 7 is generated from the horizontal synchronizing signal by the AND gate 8 shown in FIG.
Only the edge pulse shown in (F) passes and is input to the monomulti 9. The edge pulse generated by the equalizing pulse or the vertical synchronizing signal does not match the timing of the gate pulse shown in FIG. Then, the mono-multi 9 has a width including all the burst gate pulses shown in FIG.
The pulse shown in is generated. The pulse shown in FIG. 3 (G) and the burst gate pulse shown in FIG. 3 (D) are input to the AND gate 10, the burst gate pulse only after the horizontal synchronizing signal is generated at the output, and the output terminal 11 Will be output. As a result, according to the burst gate pulse generation circuit of the present invention, no burst gate pulse is generated after the equalizing pulse or the vertical synchronizing signal.

Next, the structure and operation of the second embodiment shown in FIG. 2 will be described. The second embodiment comprises mono-multis 5 to 7, an AND gate 8 and mono-multis 12 and 13 similar to the first embodiment. The composite sync signal is input to the input terminal 1, and the multi-multi 5 to 7 and the AND gate 8
By the same operation as in the first embodiment, the AND gate 8 outputs the edge pulse shown in FIG. This edge pulse is input to the monomulti 12. Then, the pulse shown in FIG. 3 (H) is output by setting the delay amount by the mono-multi 12, and the burst gate pulse shown in FIG. 3 (D) is generated by setting the pulse width by the mono-multi 13, and the output terminal 11 Will be output. This will generate a burst gate pulse only after the horizontal sync signal,
No burst gate pulse is generated after the equalizing pulse or the vertical synchronizing signal.

Further, as another embodiment, the structure of monomulti 5 to monomulti 9 in the first embodiment shown in FIG. 1,
The configuration of the monomulti 5 to monomulti 12 in the second embodiment shown in FIG. 2 may be configured as shown in FIG. That is, a monomulti 15 having a trigger enable terminal and performing a trigger operation when the trigger enable terminal is high is used, and the gate pulse output from the monomulti 6 shown in FIG. Then, the composite synchronizing signal is inverted and input to the mono-multi 15 by the inverter 14. The inverter 14 is not necessary if the mono-multi 15 operates at the falling edge. If such a configuration is used instead of the mono-multi 5 to the mono-multi 9 in FIG.
The pulse shown in FIG.
If used instead of the monomulti 12, the monomulti 15 may generate the pulse shown in FIG. The mono-multi 15 may be, for example, a C-MO.
This embodiment can be easily constructed by using 4528 integrated circuits of S, 4500 series.

[0013]

As described above in detail, the burst gate pulse generation circuit of the present invention has the above-described configuration, in which the burst gate pulse generated after the vertical synchronizing signal after the equalizing pulse is removed and the horizontal synchronizing signal is generated. Since the burst gate pulse can be generated only after, the accurate burst gate pulse matching the burst signal period can be obtained. Therefore, the burst gate pulse generated after the equalizing pulse and after the vertical synchronizing signal is not adversely affected. Further, the burst gate pulse generation circuit of the present invention can be configured with a small scale circuit. Further, even when external noise is mixed in the composite sync signal, the burst gate pulse is generated only when the pulse width of the noise is close to the width of the horizontal sync signal, so that the noise resistance is excellent.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a block diagram showing a second embodiment of the present invention.

FIG. 3 is a waveform diagram for explaining the present invention.

FIG. 4 is a partial block diagram showing another embodiment of the present invention.

FIG. 5 is a block diagram showing a conventional example.

FIG. 6 is a waveform diagram for explaining a conventional example.

[Explanation of symbols]

1 input terminal 2,3,5-7,9,12,13,15 monostable multivibrator (mono-multi) 4,11 output terminal 8,10 AND gate 14 inverter

Claims (5)

[Claims] 1. A burst gate pulse generation circuit for generating a burst gate pulse from a composite sync signal in a television signal, means for generating a burst gate pulse from an input composite sync signal, and the horizontal synchronization in the composite sync signal. Means for generating an edge pulse that rises only at the trailing edge of the signal; means for generating a third pulse that is triggered by the edge pulse and has a wider pulse width than the burst gate pulse; the burst gate pulse and the third pulse And a means for allowing only the burst gate pulse generated after the horizontal synchronizing signal to pass through the burst gate pulse generating circuit. 2. A burst gate pulse generation circuit for generating a burst gate pulse from a composite synchronizing signal in a television signal, and means for generating an edge pulse rising only at a trailing edge of the horizontal synchronizing signal in the composite synchronizing signal, And a means for generating a burst gate pulse only after the horizontal synchronizing signal based on the edge pulse. 3. The means for generating the edge pulse has a leading edge between a trailing edge of an equalizing pulse and a trailing edge of a horizontal synchronizing signal in the composite synchronizing signal, the trailing edge being after the trailing edge of the horizontal synchronizing signal. AN for generating a first pulse having a trailing edge, a means for generating a second pulse rising at the trailing edge of the composite synchronization signal, and an AND of the first pulse and the second pulse
3. The burst gate pulse generation circuit according to claim 1, comprising a D gate. 4. A burst gate pulse generation circuit for generating a burst gate pulse from a composite sync signal in a television signal, means for generating a burst gate pulse from an input composite sync signal, and an equalization pulse in the composite sync signal. A leading edge between the trailing edge and the trailing edge of the horizontal sync signal, the means for generating a first pulse having a trailing edge after the trailing edge of the horizontal sync signal, and the composite sync signal at the input terminal Means for generating a third pulse having a pulse width wider than that of the burst gate pulse rising only at the trailing edge of the horizontal synchronizing signal by inputting the first pulse to the trigger enable terminal. The burst gate pulse and the third pulse allow only the burst gate pulse generated after the horizontal synchronization signal to pass. And a burst gate pulse generation circuit. 5. A burst gate pulse generation circuit for generating a burst gate pulse from a composite sync signal in a television signal, wherein a leading edge is provided between a trailing edge of an equalization pulse in the composite sync signal and a trailing edge of a horizontal sync signal. Means for generating a first pulse having a trailing edge after the trailing edge of the horizontal synchronizing signal, and the composite synchronizing signal is input to an input terminal and the first pulse is input to a trigger enable terminal. By so doing, there are provided means for generating a fourth pulse rising only at the trailing edge of the horizontal synchronizing signal, and means for generating a burst gate pulse only after the horizontal synchronizing signal based on the fourth pulse. A burst gate pulse generation circuit characterized by being configured as follows.