JPH0496578A - Vertical synchronizing signal separation circuit - Google Patents

Abstract

PURPOSE:To separate a vertical synchronizing signal completely and to output the vertical synchronizing signal by using a pseudo horizontal synchronizing signal generating means so as to shape a pseudo horizontal synchronizing signal with a same period and a same pulse width as those of a horizontal synchronizing signal based on a trigger pulse of the same period as that of the horizontal synchronizing signal. CONSTITUTION:With a composite synchronizing signal HV inputted to an input terminal 1, a delay circuit 2 forms a delay synchronizing signal HVL whose phase is slightly delayed from the phase of the HV. Then an AND gate 8 outputs only a pulse being a high level pulse of an output signal P2 among pulses of an output signal P1 of an exclusive OR circuit 6 as a trigger pulse TP. When the TP is inputted to a pseudo horizontal synchronizing signal generating means 4, a monostable multivibrator 9 forms a pseudo horizontal synchronizing signal H' having a same period and a same pulse width as those of the horizontal synchronizing signal and the signal H' is inputted to a horizontal synchronizing signal erasure means 5. Then the horizontal synchronizing signal component HV is erased and only the vertical synchronizing signal V is completely separated.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention provides a method for extracting a horizontal synchronization signal component from a composite synchronization signal obtained by combining a vertical synchronization signal and a horizontal synchronization signal in a video signal processing system such as a television or VTR. The present invention relates to a vertical synchronization signal separation circuit that erases and separates vertical synchronization signals.

[Conventional technology]

Conventionally, a vertical synchronization signal for vertical synchronization of video signals and a horizontal synchronization signal for horizontal synchronization are transmitted from a transmitting side to a receiving side as a composite synchronizing signal in which both are combined, and on the receiving side, The vertical synchronization signal and the horizontal synchronization signal are separated and extracted.

In this case, conventional separation circuits for separating vertical synchronization signals from composite synchronization signals are composed of a time constant circuit 33 consisting of a capacitor 31 and a resistor 32, and an inverter 34, as shown in FIG. The composite synchronization signal input to the terminal 35 is integrated by the time constant circuit 33, and
Further, the signal is subjected to waveform shaping processing by an inverter 34, and is output as a pulse waveform vertical synchronization signal.

FIG. 4 is a graph showing the signal waveform, and the composite synchronization signal A that is formed on the transmitting side and inputted to the receiving side is a vertical synchronizing signal that can be completely separated on the receiving side. An equalization pulse BP is inserted between the vertical synchronization pulse vp that constitutes the horizontal synchronization signal and the horizontal synchronization pulse HP that constitutes the horizontal synchronization signal.

When the composite synchronization signal A is input to the separation circuit, it is first subjected to integration processing in the time constant circuit 33 to obtain an integral signal B.

In the integral signal B, in the horizontal synchronizing signal part, the pulse width of the synchronizing signal pulse HP is short and the potential of the capacitor of the integrating circuit is extremely weak compared to the case using the vertical synchronizing signal, so a low potential signal is output. , when transitioning from equalization pulse EP to vertical synchronization pulse VP, the pulse width becomes longer, so
The potential of the capacitor increases.

Then, at the time of transition to the vertical synchronization signal portion, the potential reaches the transition point of the inverter 34, a high level signal is output from the inverter 34, and the vertical synchronization signal C can be separated.

[Problem to be solved by the invention]

However, the potential of the integral signal B gradually increases due to the equalization pulse EP that precedes the vertical synchronizing signal V, and when the leading edge of the waveform reaches the transition point of the inverter 34, the vertical synchronizing signal C is inverted and becomes low. level noise pulse NP,
The signal may be mixed with

Furthermore, if the potential of the integral signal rises too much before moving to the vertical synchronization signal portion, the signal becomes a signal in which a noise pulse NP2 is mixed immediately before the original vertical synchronization signal.

And these noise pulses N P I, N P z
If this is mixed in, the vertical synchronizing signals will not be completely separated, and there will be a problem that the vertical synchronization of the video signal will not be achieved.

Therefore, an object of the present invention is to make it possible to reliably separate only the vertical synchronization signal from a composite synchronization signal obtained by combining the vertical synchronization signal and the horizontal synchronization signal.

[Means to solve the problem]

In order to solve this problem, the present invention provides a vertical synchronization signal separation circuit that separates a vertical synchronization signal by erasing a horizontal synchronization signal from a composite synchronization signal obtained by combining a vertical synchronization signal and a horizontal synchronization signal, trigger pulse generating means for outputting a trigger pulse having the same period as a horizontal synchronizing signal based on a delayed synchronizing signal whose phase is slightly delayed from that of the composite synchronizing signal; A pseudo-horizontal synchronization signal generating means for forming a pseudo-horizontal synchronization signal having the same period and the same pulse width, and a horizontal synchronization signal erasing means for erasing a horizontal synchronization signal component from a composite synchronization signal based on the pseudo-horizontal synchronization signal. It is characterized by

[Effect]

According to the present invention, the trigger pulse generating means can generate a trigger pulse having the same period as the horizontal synchronizing signal,
Based on this trigger pulse, the pseudo-horizontal sync signal generating means generates a pseudo-horizontal sync signal with the same period and pulse width as the horizontal sync signal, so the horizontal sync signal erasing means uses the pseudo-horizontal sync signal to The horizontal synchronization signal can be deleted from a composite synchronization signal obtained by combining the synchronization signal and the horizontal synchronization signal, and the vertical synchronization signal can be completely separated and output.

〔Example〕

Hereinafter, the present invention will be specifically described based on embodiments shown in the drawings.

FIG. 1 is a circuit diagram showing an example of a vertical synchronization signal separation circuit according to the present invention, and FIG. 2 is a graph showing signal waveforms at each point thereof.

The vertical synchronization signal separation circuit includes a delay circuit 2 that outputs a delayed synchronization signal HV whose phase is slightly delayed from a composite synchronization signal HV input from an input terminal 1, and a delay circuit 2 that outputs a delayed synchronization signal HV whose phase is slightly delayed from the composite synchronization signal HV inputted from an input terminal 1;
trigger pulse generating means 3 for outputting a trigger pulse TP having the same period as the horizontal synchronizing signal H based on vL and the composite synchronizing signal HV; It consists of a pseudo-horizontal synchronization signal generating means 4 for forming a horizontal synchronization signal H', and a horizontal synchronization signal erasing means 5 for erasing the horizontal synchronization signal H from the composite synchronization signal HV based on the pseudo-horizontal synchronization signal H'. A vertical synchronizing signal V is output from the horizontal synchronizing signal erasing means 5.

The composite synchronization signal HV is a horizontal synchronization signal H and a vertical synchronization signal V.
For example, the signals are inverted at the rising and falling positions of the pulses forming the horizontal synchronizing signal H and the vertical synchronizing signal (2), for example, using an exclusive OR circuit.

When this composite synchronous signal HV is input to the input terminal l, a delayed synchronous signal I (VL) whose phase is slightly delayed than that of the composite synchronous signal HV is formed in the delay circuit 2, and a composite synchronous signal f
(It is input to the trigger pulse generating means 3 together with V.

The trigger pulse generating means 3 includes an exclusive OR circuit 6 that forms a pulse credit at the out-of-phase portions of the rising and falling edges of the pulse from the composite synchronizing signal H■ and the delayed synchronizing signal HV I, and the exclusive OR circuit 6. Based on the output signal P of the monostable multi-bi break 7 and the output signal P2 of the monostable multi-bi break 7, the trigger pulse TP having the same period as the horizontal synchronizing signal H is extracted and an AND gate 8 is provided.

The AND gate 8 selects the output signal P of the exclusive OR circuit 6.
Among the pulses of , the pulses located where the output signal P2 from the monostable multi-bi break 7 is at a low level are masked, and only the pulses located where the output signal P2 is at a high level are triggered. Pulse TP
This will be output as .

The input side of the monostable multi-bi break 7 is connected to the output of the AND gate 8, and the trigger pulse TP is adjusted so that only the pulse that rises at the same time as the horizontal synchronizing signal H can be taken out of the pulses of the output signal p. A pulse signal with a constant pulse width a is output using the falling edge as a trigger.

Further, the pseudo horizontal synchronizing signal generating means 4 is configured to generate a pseudo horizontal synchronizing signal H' having the same pulse width and the same pulse period as the horizontal synchronizing signal H based on the trigger pulse TP outputted from the trigger pulse generating means 3. The output side of the multi-high break 9 is connected to a horizontal synchronizing signal output terminal 10 and also to the horizontal synchronizing signal erasing means 5.

The horizontal synchronization signal erasing means 5 includes an exclusive OR circuit 11 for erasing the horizontal synchronization signal H from the composite synchronization signal HV and separating the vertical synchronization signal ■ based on the pseudo horizontal synchronization signal H°; and a noise reduction circuit 12 that removes noise from the output signal of.

The above is an example of the configuration of the present invention, and its operation will now be described with reference to the graph showing signal waveforms in FIG.

First, when the composite synchronization signal HV is input to input terminal 1,
A delayed synchronization signal HV is formed in the delay circuit 2, and its delay time is determined by the minimum pulse width of the composite synchronization signal HV so that a pulse signal including a pulse synchronized with the falling edge of the horizontal synchronization signal H can be formed. The time corresponding to the narrower width is selected.

When this delayed synchronization signal HVI- is input to the trigger pulse generation means 3 together with the composite synchronization signal HV, the exclusive OR circuit 6 outputs a high level pulse when the input levels of the two input signals are different, and both are high level. Or, if the level is low, a low level pulse is output, so the output signal P
1 (delayed synchronization signal) IVL and the composite synchronization signal HV have pulses in which the rising and falling portions are shifted to a high level.

Then, when the output signal P1 of the exclusive OR circuit and the output signal P2 of the multi-by-break 7 are input to the AND gate, a high level pulse is output only when both signals are at high level, and synchronized with the pulse period of the horizontal synchronizing signal H. The triggered pulse TP is extracted.

Next, when the trigger pulse TP is input to the pseudo-horizontal synchronization signal generating means 4, the monostable multi-high break 9 generates a pseudo-horizontal synchronization signal H" having the same period and the same pulse width as the horizontal synchronization signal H, based on the trigger pulse TP. is formed, and the pseudo horizontal synchronizing signal H' is input to the horizontal synchronizing signal erasing means 5.

The exclusive OR circuit 11 of the horizontal synchronization signal erasing means 5 outputs a high level pulse when the input levels of the two input signals are different, and outputs a low level pulse when both are high level or low level. When the pseudo horizontal synchronizing signal H' is input to the horizontal synchronizing signal erasing means 5, since the horizontal synchronizing signal H and the pseudo horizontal synchronizing signal H' have the same pulse period and pulse width, the horizontal synchronizing signal H' of the composite synchronizing signal HV is The synchronization signal component is erased, and only the vertical synchronization signal V can be completely separated.

(Effects of the Invention) As described above, according to the present invention, a pseudo-horizontal synchronization signal having the same period and the same pulse width as the horizontal synchronization signal is formed, and horizontal synchronization is performed from the composite synchronization signal based on the pseudo-horizontal synchronization signal. Since the signal is erased, the vertical synchronizing signal can be completely separated, and synchronization failures due to disturbances in the vertical synchronizing signal will not occur.

[Brief explanation of drawings]

Fig. 1 is a circuit diagram showing an embodiment of the present invention, Fig. 2 is a graph showing signal waveforms, Fig. 3 is a circuit diagram showing a conventional technique, and Fig. 4 is a circuit diagram showing an embodiment of the present invention.
The figure is a graph showing signal waveforms in a conventional circuit. Explanation of symbols 2 = - Delay circuit 3 - Trigger pulse generating means 4 - Pseudo horizontal synchronizing signal generating means 5 - Horizontal synchronizing signal signal erasing means 6 - Exclusive OR circuit 7 - Monostable multi-bi break 8 ---A N D gate 9 - Monostable multi-by break 11 - Exclusive OR circuit

Claims (1)

[Claims] A vertical synchronization signal separation circuit that separates a vertical synchronization signal by erasing a horizontal synchronization signal from a composite synchronization signal (HV) that is a combination of a vertical synchronization signal (V) and a horizontal synchronization signal (H), wherein the composite synchronization signal Trigger pulse generating means (3) for outputting a trigger pulse (TP) having the same period as the horizontal synchronization signal based on the delayed synchronization signal (HV_L) whose phase is slightly delayed from (HV) and the composite synchronization signal; pseudo-horizontal synchronization signal generating means (4) for forming a pseudo-horizontal synchronization signal (H') having the same period and same pulse width as the horizontal synchronization signal (H) based on the trigger pulse (TP); horizontal synchronization signal erasing means (5) for erasing horizontal synchronization signal components from the composite synchronization signal (HV) based on H');
A vertical synchronization signal separation circuit comprising: