JP3405008B2 - Vertical sync signal circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a vertical synchronizing signal circuit applicable to a television receiver and a monitor receiver and capable of stably obtaining a vertical synchronizing signal.

[0002]

2. Description of the Related Art A conventional vertical synchronizing signal circuit of a television receiver and a monitor receiver has a structure as shown in FIG. A video signal or an RGB composite signal is applied to the sync separation circuit 1, a vertical sync signal as its output is input to the vertical oscillation circuit 6, and the output pulse drives the vertical deflection circuit 7 to perform vertical scanning.

In Japanese Patent Application No. 3-20159, there is proposed a countdown method of dividing a horizontal frequency to obtain a vertical synchronizing signal instead of providing the vertical oscillating circuit 6.

[0004]

However, such a conventional technique has a problem in that if any one of the vertical synchronizing signals is missing, normal vertical scanning cannot be performed and the image is disturbed.

The present invention solves the above-mentioned problems, and in a television receiver and a monitor receiver, for example, A
It is an object of the present invention to provide a vertical synchronizing signal circuit that can stably obtain a synchronizing signal even when the vertical synchronizing signal is lost due to PL fluctuation.

[0006]

In order to achieve the above object, the present invention provides a sync separation circuit for extracting a vertical sync signal, a delay circuit for delaying two vertical periods using its output as a trigger, and a delay circuit for the delay circuit. Another delay circuit that delays for two vertical periods by using the output of the sync separation circuit as a trigger, and a reset circuit that clears the operation of one delay circuit by the comparison circuit when the two delay circuits have the same output. It is composed of a circuit, a sync separation circuit, an adder circuit for combining the outputs of two delay circuits, a vertical oscillation circuit, and a vertical deflection circuit.

Here, each delay circuit delays by two vertical periods instead of one vertical period. For example, in a VTR device, one frame length is constant when a video signal recorded once is reproduced. However, the lengths of the vertical periods of the first field and the second field are not equal to each other, and there is a case where the length of the vertical period is replaced with a repetition of the original vertical period.

If the signal whose length has been changed to short is delayed for one vertical period, the positional relationship between the synchronization signal and the video signal is shifted, and the video is vertically swung. Therefore, the signals are delayed by two vertical periods, the vertical oscillation of the first field of the next frame is performed with the synchronization signal of the first field of the frame, and the vertical oscillation of the second field of the next frame is performed with the synchronization signal of the second field. It is configured to oscillate.

[0009]

According to the present invention, even if the vertical synchronizing signal of the output of the sync separation circuit is lost due to the APL fluctuation, for example, the output of the sync separation circuit and the output of the two delay circuits are combined to stabilize the operation. A vertical synchronizing signal can be obtained.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS.
This will be described with reference to FIG.

FIG. 1 is a block diagram of a vertical synchronizing signal circuit for stably obtaining a vertical synchronizing signal. FIG. 2 is a waveform chart of each part at the time of normal operation, and FIG. 3 is a waveform diagram of each part at the time of malfunction.

In FIG. 1, reference numeral 1 is a sync separation circuit for extracting a vertical sync signal, 2 and 3 are delay circuits, 4 is a comparison circuit for comparing the output waveforms of the delay circuits 2 and 3, and 5 is an addition circuit.
6 is a vertical oscillation circuit, and 7 is a vertical deflection circuit.

Next, the operation of the above-described circuit will be described. A video signal or an RGB composite signal is input to the sync separation circuit 1 to extract a vertical sync signal. The output is input to the two delay circuits 2 and 3 and the adder circuit 5. The delay circuit 2 outputs a pulse obtained by delaying the output of the sync separation circuit 1 by two vertical periods, and the delay circuit 3 delays the output of the sync separation circuit 1 by two vertical periods while the delay circuit 2 is operating. Output the pulse.

The respective outputs obtained from the sync separation circuit 1 and the delay circuits 2 and 3 are added by the adder circuit 5. Then, the added waveforms are input to the vertical oscillation circuit 6 as a pseudo vertical synchronization signal to drive the vertical deflection circuit to perform vertical scanning.

In FIG. 2, (a) is a waveform diagram of a vertical sync signal output from the sync separation circuit 1, (b) is an output waveform diagram of the delay circuit 2, and (c) is an output waveform diagram of the delay circuit 3. d)
FIG. 4 is an output waveform diagram of the adder circuit 5.

The circuit operation when one vertical sync signal output from the sync separation circuit 1 is missing will now be described.

In FIG. 2, a sync separator circuit 1 output (a), a delay circuit 2 output (b), a delay circuit 3 output (c)
The amplitude of each pulse is 1. It is assumed that the waveform of the output (a) of the sync separation circuit 1 at t2 is missing in FIG.

Since the delay circuit 2 operates by using the pulses at the times t1, t3, and t5 of the output (a) of the sync separation circuit 1 as a trigger, there is no influence. The delay circuit 3 is the sync separation circuit 1
Since the output (a) is operated by using the pulses at the times t2, t4, and t6 as a trigger, it does not output at the time t4. When each pulse of the sync separation circuit 1 output (a), the delay circuit 2 output (b), and the delay circuit 3 output (c) is added by the adder circuit 5, a pulse like an adder circuit 5 output (d) is obtained. If the operable input amplitude level of the vertical oscillator circuit 6 is set to 1 or more, t1, t2, t3, t4 of the output (d) of the adder circuit 5
The vertical oscillation circuit 6 operates stably by the pulses at t5 and t6.

Next, the operation when the delay circuits 2 and 3 output at the same time will be described. In FIG. 3, (a) is a waveform diagram of a vertical synchronizing signal output from the sync separation circuit 1, (b) is an output waveform diagram of the delay circuit 2, (c) is an output waveform diagram of the delay circuit 3, and (d) is. 7 is an output waveform diagram of the comparison circuit 4. FIG.

If the delay circuits 2 and 3 operate by using the pulse at the time t1 of the sync separation circuit 1 output (a) as a trigger, as shown in the delay circuit 2 output (b) and the delay circuit 3 output (c), Also generates a pulse at t3. A comparison circuit determines whether the outputs of the delay circuits 2 and 3 are the same. If they are different, the comparison circuit 4 does not give a reset signal to the delay circuit 3, but if they are the same, a pulse (d) is generated. . When the operation of the delay circuit 3 is temporarily suspended by this pulse (d), the delay circuit 3 operates by using the vertical synchronizing signal at time t4 given by the synchronization separating circuit 1 as a trigger,
A pulse is output at t6. Therefore, delay circuits 2 and 3
Will alternately output pulses.

[0021]

As is apparent from the above embodiments, according to the vertical synchronizing signal circuit of the present invention, even if the vertical synchronizing signal is missing in the output of the synchronizing separating circuit due to APL fluctuation, for example, the output of the synchronizing separating circuit is By synthesizing the outputs of the two delay circuits that operate using the output as a trigger, the vertical synchronization signal can be stably obtained.

[Brief description of drawings]

FIG. 1 is a block diagram of a vertical synchronizing signal circuit according to an embodiment of the present invention.

FIG. 2 is a waveform chart of each part at the time of malfunction in FIG.

FIG. 3 is a waveform diagram of each part during normal operation in FIG.

FIG. 4 is a block configuration diagram of a conventional vertical synchronizing signal circuit.

[Explanation of symbols]

1 Sync separation circuit 2 delay circuit 3 delay circuit 4 Comparison circuit 5 adder circuit 6 Vertical oscillation circuit 7 Vertical deflection circuit

Claims (2)

(57) [Claims] 1. A synchronization separation circuit for extracting a vertical synchronization signal and its output as a trigger, a delay circuit for delaying by two vertical periods, and an output of the synchronization separation circuit while the delay circuit is operating as a trigger. A delay circuit for delaying a vertical period,
When the two delay circuits have the same output, the comparator circuit has a reset circuit that clears the operation of one delay circuit,
A vertical synchronization signal circuit that stably obtains a vertical synchronization signal by combining the outputs of the synchronization separation circuit and the outputs of two delay circuits with an addition circuit. 2. A vertical synchronizing signal circuit which uses a signal delayed by two vertical periods as a pseudo vertical synchronizing signal in a delay circuit which operates by using the vertical synchronizing signal extracted by the synchronizing separation circuit as a trigger.