JPH04250777A - Horizontal synchronizing separator circuit and television receiver - Google Patents

Horizontal synchronizing separator circuit and television receiver

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Publication number
JPH04250777A
JPH04250777A JP2563491A JP2563491A JPH04250777A JP H04250777 A JPH04250777 A JP H04250777A JP 2563491 A JP2563491 A JP 2563491A JP 2563491 A JP2563491 A JP 2563491A JP H04250777 A JPH04250777 A JP H04250777A
Authority
JP
Japan
Prior art keywords
horizontal
signal
circuit
composite
synchronization signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2563491A
Other languages
Japanese (ja)
Inventor
Hiroshi Okatsu
大勝 博
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP2563491A priority Critical patent/JPH04250777A/en
Publication of JPH04250777A publication Critical patent/JPH04250777A/en
Pending legal-status Critical Current

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  • Synchronizing For Television (AREA)

Abstract

PURPOSE:To apply a horizontal synchronizing signal capable of implementing phase control of a horizontal AFC at all times to the television receiver by extracting substantially only the horizontal synchronizing signal even for an equalizing pulse period and a vertical synchronizing signal period from a composite synchronizing signal. CONSTITUTION:A synchronizing separator circuit 3 of a horizontal synchronizing separator circuit 1 separates a composite synchronizing signal (a) from an input video signal from an input terminal 2 and outputs a composite synchronizing signal (b). The signal (b) is delayed via an automatic frequency control circuit 4 by a delay circuit 5 so that the horizontal synchronization position is set within a pulse width of a signal (c). The output signal (c) of the circuit 4 is fed to a clear terminal CLR, a delayed composite synchronizing signal c' from the circuit 5 is fed to a clock terminal CLK and an output (d) from the circuit 6 is only the horizontal synchronizing signal for a period even when an equalization pulse and a vertical synchronizing signal are in existence.

Description

【発明の詳細な説明】[Detailed description of the invention]

【0010】0010

【産業上の利用分野】本発明はテレビジョン受像機に関
するものであり、特にその水平同期分離回路に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a television receiver, and more particularly to a horizontal synchronization separation circuit thereof.

【0020】[0020]

【従来の技術】テレビジョン受像機においては図6に示
すように映像信号中の水平同期信号を同期分離回路30
で分離して水平AFC回路31の制御に使うようにして
いる。 水平AFC回路31は水平出力回路34中のフライバッ
クトランスからのフライバックパルスと同期分離回路3
0からの水平同期信号とを位相比較器32で位相比較し
、その出力で水平発振回路33を制御するようになって
いる。従来の同期分離回路30は入力された複合映像信
号を振幅分離することにより水平同期信号を得ていたが
、その出力は垂直ブランキング期間の等化パルスや垂直
同期信号も含まれる。そのため、例えば垂直同期信号期
間は水平AFC回路31の位相制御を切って水平AFC
回路31の乱れを少なくするようにしていた。
2. Description of the Related Art In a television receiver, as shown in FIG.
The signal is separated and used for controlling the horizontal AFC circuit 31. The horizontal AFC circuit 31 connects the flyback pulse from the flyback transformer in the horizontal output circuit 34 to the synchronization separation circuit 3.
A phase comparator 32 compares the phase with the horizontal synchronizing signal from 0, and the horizontal oscillation circuit 33 is controlled by the output. The conventional synchronization separation circuit 30 obtains a horizontal synchronization signal by amplitude-separating the input composite video signal, but its output also includes an equalization pulse during the vertical blanking period and a vertical synchronization signal. Therefore, for example, during the vertical synchronization signal period, the phase control of the horizontal AFC circuit 31 is turned off and the horizontal AFC circuit 31 is turned off.
An attempt was made to reduce disturbances in the circuit 31.

【0030】[0030]

【発明が解決しようとする課題】しかしながら、この方
法では等化パルスによる影響は払拭されていないため水
平AFC回路の乱れが生じていた。また、比較的幅の広
い雑音パルスによっても水平AFC回路の乱れが生じて
いた。一方、垂直同期信号期間は位相制御を行なわない
ため、この期間の直後の位相制御再開時にやはり水平A
FC回路の乱れを生じ、そのため画面上部において画像
が曲がるという問題があった。
[Problems to be Solved by the Invention] However, this method does not eliminate the influence of the equalization pulse, causing disturbances in the horizontal AFC circuit. Additionally, relatively wide noise pulses also caused disturbances in the horizontal AFC circuit. On the other hand, since phase control is not performed during the vertical synchronization signal period, when phase control is resumed immediately after this period, the horizontal
There was a problem in that the FC circuit was disturbed and the image was distorted at the top of the screen.

【0040】本発明はこのような点に鑑みなされたもの
であって、常時水平AFCの位相制御を行なうことがで
きるような水平同期信号を供給する水平同期分離回路及
びそれを用いたテレビジョン受像機を提供することを目
的とするものである。
The present invention has been made in view of the above points, and provides a horizontal synchronization separation circuit that supplies a horizontal synchronization signal capable of constantly controlling the phase of horizontal AFC, and a television reception using the same. The purpose is to provide opportunities.

【0050】[0050]

【課題を解決するための手段】上記の目的を達成するた
め本発明の水平同期信号分離回路は、複合映像信号から
複合同期信号を分離する複合同期分離手段と、水平周波
数で発振する発振器を有するとともに前記複合同期分離
手段からの複合同期信号を用いて前記発振器の周波数を
制御する自動周波数制御回路と、前記自動周波数制御回
路から出力された水平信号の各1周期期間内において該
期間に存する前記複合同期信号の最初の同期信号を順次
抽出する抽出手段と、から成っている。
[Means for Solving the Problems] In order to achieve the above object, the horizontal synchronization signal separation circuit of the present invention includes a composite synchronization separation means for separating a composite synchronization signal from a composite video signal, and an oscillator that oscillates at a horizontal frequency. and an automatic frequency control circuit that controls the frequency of the oscillator using the composite synchronization signal from the composite synchronization separation means; and extraction means for sequentially extracting the first synchronization signal of the composite synchronization signal.

【0060】また、本発明の水平同期分離回路は、複合
映像信号から複合同期信号を分離する複合同期分離手段
と、水平周波数で発振する発振器を有するとともに前記
複合同期分離手段からの複合同期信号を用いて前記発振
器の周波数を制御する自動周波数制御回路と、前記複合
同期分離手段から出力された複合同期信号を所定時間遅
延する遅延手段と、前記自動周波数制御回路と前記遅延
手段の出力を入力し前記自動周波数制御回路から出力さ
れた水平パルスの各1周期期間内において前記遅延手段
からの複合同期信号の最初の信号を抽出するゲ−ト手段
と、から構成してもよい。尚、この場合、前記抽出手段
から出力された水平同期信号のパルス幅を一定に揃える
パルス整形回路を付加するとよい。
Further, the horizontal synchronization separation circuit of the present invention has a composite synchronization separation means for separating a composite synchronization signal from a composite video signal, and an oscillator that oscillates at a horizontal frequency, and also includes a composite synchronization signal from the composite synchronization separation means. an automatic frequency control circuit for controlling the frequency of the oscillator using the oscillator, a delay means for delaying the composite synchronization signal output from the composite synchronization separation means for a predetermined time, and outputs of the automatic frequency control circuit and the delay means are inputted. The apparatus may further include gate means for extracting the first signal of the composite synchronization signal from the delay means within each period of the horizontal pulse output from the automatic frequency control circuit. In this case, it is preferable to add a pulse shaping circuit that makes the pulse width of the horizontal synchronizing signal outputted from the extraction means constant.

【0070】また、本発明のテレビジョン受像機として
は、複合映像信号から複合同期信号を分離する複合同期
分離手段と、水平周波数で発振する発振器を有するとと
もに前記複合同期分離手段からの複合同期信号を用いて
前記発振器の周波数を制御する自動周波数制御回路と、
前記自動周波数制御回路から出力された水平信号の各1
周期期間内において該期間に存する前記複合同期信号の
最初の同期信号を順次抽出する抽出手段と、前記抽出手
段で抽出された水平同期信号を入力して水平AFCを行
なう水平AFC回路と、を備える構成とする。
Further, the television receiver of the present invention includes a composite sync separation means for separating a composite sync signal from a composite video signal, and an oscillator that oscillates at a horizontal frequency, and also includes a composite sync signal from the composite sync separation means. an automatic frequency control circuit that controls the frequency of the oscillator using
Each one of the horizontal signals output from the automatic frequency control circuit
A horizontal AFC circuit that performs horizontal AFC by inputting the horizontal synchronizing signal extracted by the extracting means; and a horizontal AFC circuit that performs horizontal AFC by inputting the horizontal synchronizing signal extracted by the extracting means. composition.

【0080】[0080]

【作用】上記本発明の水平同期分離回路によると、複合
同期信号が入力される自動周波数制御回路の水平発振信
号は複合同期信号中の等化パルスや垂直同期信号による
影響を受けた部分が本来のものとは少しずれた位相で出
力されるが、その自動周波数制御回路の出力である水平
信号の各1周期期間が複合同期信号の水平同期信号抽出
に作用する。
[Operation] According to the above-mentioned horizontal synchronization separation circuit of the present invention, the horizontal oscillation signal of the automatic frequency control circuit to which the composite synchronization signal is input is originally affected by the equalization pulse and vertical synchronization signal in the composite synchronization signal. Although it is output with a phase slightly shifted from that of the horizontal signal, each period of the horizontal signal output from the automatic frequency control circuit acts on the horizontal synchronization signal extraction of the composite synchronization signal.

【0090】そして、複合同期信号のうち水平同期信号
のみが存する部分では前記1周期期間に1つの信号しか
存しないことになるので、その水平同期信号が取り出さ
れる。次に、1周期期間が等化パルスの存する部分に対
応する1周期には複数のパルスが存するが、その最初の
ものだけが抽出され、他は抽出されない。垂直同期信号
が存する部分に対応する1周期期間についても同様に複
合同期信号には切込みパルスにより複数のパルスが存す
るが、その最初のパルス(水平同期に対応するパルス)
のみが抽出される。このように、等化パルス期間及び垂
直同期信号期間も水平同期信号が実質的に得られる。
Then, in the portion of the composite synchronization signal where only the horizontal synchronization signal exists, only one signal exists during the one cycle period, so that horizontal synchronization signal is extracted. Next, although there are a plurality of pulses in one period in which one period corresponds to the portion where the equalization pulse exists, only the first one is extracted and the others are not extracted. Similarly, for one cycle period corresponding to the part where the vertical synchronization signal exists, there are multiple pulses in the composite synchronization signal due to cutting pulses, but the first pulse (pulse corresponding to horizontal synchronization)
only are extracted. In this way, the horizontal synchronization signal is substantially obtained during the equalization pulse period and the vertical synchronization signal period as well.

【0100】[0100]

【実施例】以下、本発明の実施例を図面を参照して説明
する。本発明を実施した第1図において、水平同期分離
回路1は入力映像信号から複合同期信号を分離する複合
同期分離回路3と、自動周波数制御回路4と、遅延回路
5と、抽出回路6と、単安定マルチバイブレ−タ7とか
ら構成されている。複合同期分離回路3は入力端子2を
通して与えられる複合映像信号(a)を振幅分離して複
合同期信号(b)を出力する。この複合同期信号(b)
は自動周波数制御回路4と遅延回路5に供給される。
Embodiments Hereinafter, embodiments of the present invention will be described with reference to the drawings. In FIG. 1 in which the present invention is implemented, a horizontal synchronization separation circuit 1 includes a composite synchronization separation circuit 3 that separates a composite synchronization signal from an input video signal, an automatic frequency control circuit 4, a delay circuit 5, an extraction circuit 6, It is composed of a monostable multivibrator 7. The composite sync separation circuit 3 separates the amplitude of the composite video signal (a) applied through the input terminal 2 and outputs a composite sync signal (b). This composite synchronization signal (b)
is supplied to an automatic frequency control circuit 4 and a delay circuit 5.

【0110】自動周波数制御回路4は図2に示すように
水平周波数で発振する発振器11と、この発振器11の
出力を複合同期信号と位相比較し、その比較出力で発振
器11を制御する位相比較器10を有している。自動周
波数制御回路4の出力(従って、発振器11の出力)は
図3の(c)に示すようになるが、等化パルスEPや垂
直同期信号VD部分では位相が若干ずれたものとなる。 この信号(c)は次段の抽出回路6で遅延回路5からの
遅延複合同期信号(c’)とのロジックを受ける。尚、
遅延回路5は信号(c)が等化パルスや垂直同期信号の
期間等では多少前後にずれても信号(c)のパルス幅内
に水平同期位置が納まるように複合同期信号を遅延して
いる。抽出回路6は図4に示すようなロジック回路で構
成されている。
As shown in FIG. 2, the automatic frequency control circuit 4 includes an oscillator 11 that oscillates at a horizontal frequency, and a phase comparator that compares the phase of the output of this oscillator 11 with a composite synchronization signal and controls the oscillator 11 with the comparison output. It has 10. The output of the automatic frequency control circuit 4 (therefore, the output of the oscillator 11) is as shown in FIG. 3(c), but the equalization pulse EP and vertical synchronization signal VD portions are slightly out of phase. This signal (c) is logically received by the extraction circuit 6 at the next stage and the delayed composite synchronization signal (c') from the delay circuit 5. still,
The delay circuit 5 delays the composite synchronization signal so that the horizontal synchronization position is within the pulse width of the signal (c) even if the signal (c) is slightly shifted forward or backward during the equalization pulse or vertical synchronization signal period. . The extraction circuit 6 is composed of a logic circuit as shown in FIG.

【0120】図4において、自動周波数制御回路4の出
力信号(c)は端子13を介してクリア端子CLRに印
加され、遅延回路5からの遅延複合同期信号(c’)は
端子14を介してクロック端子CLKへ印加される。図
5はこの回路を説明するための波形図であり、各信号(
c)、(c’)、(d)はいずれも図3の波形(c)、
(c’)、(d)に対応している。図4のロジック回路
は信号(c)と(c’)が共にハイレベルのときQの反
転出力(d)が(c’)に同期して立ち下がり、(c)
の立ち下がりに同期して立ち上がる。その結果、このロ
ジック回路は(c)の各1周期Tにおいて、最初の(c
’)のみを抽出することになる。これにより、抽出回路
6の出力(d)は等化パルスや垂直同期信号の存する期
間においても水平同期信号のみが存する形となる。
In FIG. 4, the output signal (c) of the automatic frequency control circuit 4 is applied to the clear terminal CLR via the terminal 13, and the delayed composite synchronization signal (c') from the delay circuit 5 is applied via the terminal 14. It is applied to the clock terminal CLK. FIG. 5 is a waveform diagram for explaining this circuit, and each signal (
c), (c'), and (d) are all waveforms (c) in FIG.
This corresponds to (c') and (d). In the logic circuit of FIG. 4, when both signals (c) and (c') are at high level, the inverted output (d) of Q falls in synchronization with (c'), and (c)
It rises in synchronization with the fall of . As a result, this logic circuit performs the first (c) in each cycle T of (c).
') will be extracted. As a result, the output (d) of the extraction circuit 6 has a form in which only the horizontal synchronizing signal exists even during the period in which the equalization pulse and the vertical synchronizing signal exist.

【0130】尚、この抽出回路の出力(d)は図3に示
されている如く、そのパルス幅が必ずしも一定でないの
で、単安定マルチバイブレ−タ7で処理することにより
一定幅のパルスに整形する。
As shown in FIG. 3, the pulse width of the output (d) of this extraction circuit is not necessarily constant, so it is processed by the monostable multivibrator 7 to be shaped into a pulse with a constant width. do.

【0140】図1において、このようにして得られた水
平同期信号(e)はテレビジョン受像機における通常の
水平AFC回路8に供給される。この場合、水平AFC
回路8の制御動作は垂直同期信号期間も含め常時行なう
ことができ、しかも等化パルスEPや垂直同期信号VD
の期間の不要パルス等は入力されないので、位相ずれ等
の誤動作が生じない。
In FIG. 1, the horizontal synchronizing signal (e) thus obtained is supplied to a normal horizontal AFC circuit 8 in a television receiver. In this case, horizontal AFC
The control operation of the circuit 8 can be performed at all times including the vertical synchronization signal period, and moreover, the control operation of the circuit 8 can be performed at all times including the vertical synchronization signal period, and moreover
Since unnecessary pulses and the like during the period are not input, malfunctions such as phase shifts do not occur.

【0150】[0150]

【発明の効果】以上説明した通り本発明によれば、等化
パルス期間及び垂直同期信号期間も水平同期信号のみが
実質的に得られるので、水平AFCを行なう場合、良好
な制御動作が実現される。従って、その水平同期分離回
路を用いて水平AFC制御を行なうテレビジョン受像機
は画面上部で画像が曲がったりすることがなく、安定し
た画像を形成することができる。
As explained above, according to the present invention, since only the horizontal synchronizing signal is substantially obtained during the equalization pulse period and the vertical synchronizing signal period, good control operation can be achieved when performing horizontal AFC. Ru. Therefore, a television receiver that performs horizontal AFC control using the horizontal synchronization separation circuit can form a stable image without distorting the image at the top of the screen.

【図面の簡単な説明】[Brief explanation of the drawing]

【図1】  本発明を実施した水平同期分離回路を示す
ブロック回路図
[Fig. 1] Block circuit diagram showing a horizontal synchronization separation circuit implementing the present invention

【図2】  その水平同期分離回路の一部の構成図[Figure 2] Partial configuration diagram of the horizontal synchronization separation circuit

【図
3】  図1の各部の信号波形図
[Figure 3] Signal waveform diagram of each part in Figure 1

【図4】  図1の要部の回路図[Figure 4] Circuit diagram of the main parts of Figure 1

【図5】  図4の各部の信号波形図[Figure 5] Signal waveform diagram of each part in Figure 4

【図6】  従来例のブロック回路図[Figure 6] Block circuit diagram of conventional example

【符号の説明】[Explanation of symbols]

1  水平同期分離回路 3  分離回路 4  自動周波数制御回路 5  遅延回路 6  抽出回路 7  単安定マルチバイブレ−タ 8  水平AFC回路 1 Horizontal synchronization separation circuit 3 Separation circuit 4 Automatic frequency control circuit 5 Delay circuit 6 Extraction circuit 7 Monostable multivibrator 8 Horizontal AFC circuit

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】複合映像信号から複合同期信号を分離する
複合同期分離手段と、水平周波数で発振する発振器を有
するとともに前記複合同期分離手段からの複合同期信号
を用いて前記発振器の周波数を制御する自動周波数制御
回路と、前記自動周波数制御回路から出力された水平信
号の各1周期期間内において該期間に存する前記複合同
期信号の最初の同期信号を順次抽出する抽出手段と、か
ら成る水平同期分離回路。
Claims: 1. Composite synchronization separation means for separating a composite synchronization signal from a composite video signal; and an oscillator that oscillates at a horizontal frequency, and controlling the frequency of the oscillator using the composite synchronization signal from the composite synchronization separation means. Horizontal synchronization separation comprising: an automatic frequency control circuit; and extraction means for sequentially extracting the first synchronization signal of the composite synchronization signal existing in each period of the horizontal signal output from the automatic frequency control circuit. circuit.
【請求項2】複合映像信号から複合同期信号を分離する
複合同期分離手段と、水平周波数で発振する発振器を有
するとともに前記複合同期分離手段からの複合同期信号
を用いて前記発振器の周波数を制御する自動周波数制御
回路と、前記複合同期分離手段から出力された複合同期
信号を所定時間遅延する遅延手段と、前記自動周波数制
御回路と前記遅延手段の出力を入力し前記自動周波数制
御回路から出力された水平パルスの各1周期期間内にお
いて前記遅延手段からの複合同期信号の最初の信号を抽
出するゲ−ト手段と、から成る水平同期分離回路。
2. Composite synchronization separation means for separating a composite synchronization signal from a composite video signal, and an oscillator that oscillates at a horizontal frequency, and controlling the frequency of the oscillator using the composite synchronization signal from the composite synchronization separation means. an automatic frequency control circuit; a delay means for delaying the composite synchronization signal outputted from the composite synchronization separation means for a predetermined time; and an output of the automatic frequency control circuit and the delay means that is inputted and outputted from the automatic frequency control circuit. gate means for extracting the first signal of the composite synchronization signal from the delay means within each period of the horizontal pulse.
【請求項3】複合映像信号から複合同期信号を分離する
複合同期分離手段と、水平周波数で発振する発振器を有
するとともに前記複合同期分離手段からの複合同期信号
を用いて前記発振器の周波数を制御する自動周波数制御
回路と、前記複合同期分離手段から出力された複合同期
信号を所定時間遅延する遅延手段と、前記自動周波数制
御回路と前記遅延手段の出力を入力し前記自動周波数制
御回路から出力された水平パルスの各1周期期間内にお
いて前記遅延手段からの複合同期信号の最初の信号を抽
出するゲ−ト手段と、前記抽出手段から出力された水平
同期信号のパルス幅を一定に揃えるパルス整形回路と、
から成る水平同期分離回路。
3. Composite synchronization separation means for separating a composite synchronization signal from a composite video signal, and an oscillator that oscillates at a horizontal frequency, and controlling the frequency of the oscillator using the composite synchronization signal from the composite synchronization separation means. an automatic frequency control circuit; a delay means for delaying the composite synchronization signal outputted from the composite synchronization separation means for a predetermined time; and an output of the automatic frequency control circuit and the delay means that is inputted and outputted from the automatic frequency control circuit. gate means for extracting the first signal of the composite synchronization signal from the delay means within each period of one horizontal pulse; and a pulse shaping circuit for making the pulse width of the horizontal synchronization signal outputted from the extraction means constant. and,
Horizontal sync separation circuit consisting of:
【請求項4】複合映像信号から複合同期信号を分離する
複合同期分離手段と、水平周波数で発振する発振器を有
するとともに前記複合同期分離手段からの複合同期信号
を用いて前記発振器の周波数を制御する自動周波数制御
回路と、前記自動周波数制御回路から出力された水平信
号の各1周期期間内において該期間に存する前記複合同
期信号の最初の同期信号を順次抽出する抽出手段と、前
記抽出手段で抽出された水平同期信号を入力して水平A
FCを行なう水平AFC回路と、を備えるテレビジョン
受像機。
4. Composite synchronization separation means for separating a composite synchronization signal from a composite video signal, and an oscillator that oscillates at a horizontal frequency, and controlling the frequency of the oscillator using the composite synchronization signal from the composite synchronization separation means. an automatic frequency control circuit; an extraction means for sequentially extracting the first synchronization signal of the composite synchronization signal existing in each period of the horizontal signal output from the automatic frequency control circuit; and extraction by the extraction means. Horizontal A
A television receiver comprising a horizontal AFC circuit that performs FC.
JP2563491A 1991-01-25 1991-01-25 Horizontal synchronizing separator circuit and television receiver Pending JPH04250777A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2563491A JPH04250777A (en) 1991-01-25 1991-01-25 Horizontal synchronizing separator circuit and television receiver

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2563491A JPH04250777A (en) 1991-01-25 1991-01-25 Horizontal synchronizing separator circuit and television receiver

Publications (1)

Publication Number Publication Date
JPH04250777A true JPH04250777A (en) 1992-09-07

Family

ID=12171293

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2563491A Pending JPH04250777A (en) 1991-01-25 1991-01-25 Horizontal synchronizing separator circuit and television receiver

Country Status (1)

Country Link
JP (1) JPH04250777A (en)

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