JPS6055770A - Horizontal pulse generator of television receiver - Google Patents

Abstract

PURPOSE:To obtain a stable horizontal pulse having high resistance to external noises by comparing the phases between a signal obtained by deleting a vertical synchronizing signal from the output of a synchronizing separator circuit and a square wave obtained from a horizontal oscillating circuit through an output circuit. CONSTITUTION:The composite video signal supplied from a ternimal 1 undergoes the synchronizing separation through a synchronizing separator circuit 2. The output of the circuit 2 is supplied to a phase comparator 3. At the same time, the output of a horizontal oscillating circuit 5 is supplied to an output circuit 6 and a pulse of a fixed width is obtained as the output of the circuit 6. This pulse is supplied to a gate circuit 8. While the other output of the circuit 6 is supplied to the comparator 3 in the form of a square wave having a 50% duty ratio. The comparator 3 performs the phase comparison between the outputs of circuits 2 and 6 and applies the output of comparison to the circuit 5 through an LPF4 to control the oscillating frequency. The circuit 8 gates the outputs of the circuits 6 and 2 and delivers a horizontal pulse to an output terminal 7.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a horizontal pulse generator for use in television receivers.

Conventional configuration and its problems When generating horizontal pulses in a television receiver, a conventional configuration as shown in FIG. 1 is used. In FIG. 1, 1 is a video signal input terminal, 2 is a synchronization separation circuit, 3 is a phase comparison circuit, 4 is a low-pass filter, 6 is a horizontal oscillation circuit, 6 is an output circuit, and 7 is an output terminal.

In FIG. 1, a synchronization separation circuit 2 extracts a synchronization signal from a composite video signal input from a video signal input terminal 1, and the synchronization signal is input to a phase comparator circuit 3. On the other hand, the output of the horizontal oscillation circuit 5 has a duty ratio of 60 in the output circuit 6.
% square wave, and the output of the output circuit 6 is input to the phase comparison circuit 3. 3. The phase comparison circuit 3 compares the phases of the synchronizing signal and the output of the output circuit 6, and passes the output through the low-pass filter 4. The output of the low-pass filter 4 is applied to a horizontal oscillation circuit 6 to control oscillation. The output of the horizontal oscillation circuit 6 is input to the output circuit 6, and a horizontal pulse to be input to the output terminal 7 is obtained.

However, the conventional circuit shown in FIG. 1 has the following drawbacks. First, during the vertical retrace period, a vertical synchronizing signal whose width is wider than that of the horizontal synchronizing signal is input to the phase comparator circuit 3. Therefore, a ratio-phase comparison is performed over the period of the vertical synchronizing signal, and the output of the two-phase comparator circuit 3 is performed. appears as a large error voltage, and since the horizontal oscillation circuit 5 is controlled, the phase of the horizontal pulse obtained at the output terminal 7 and the horizontal synchronization signal is largely shifted. If this phase shift remains in the video display period 1 after the 22nd H, an image with a shifted upper part will be displayed on the cathode ray tube (CRT) of the television receiver, making it impossible to display an accurate image. was there.

In addition, in teletext receivers, in order to extract the character signal (digital signal) inserted during the vertical retrace interval, a horizontal pulse with an accurate phase is transmitted between the 10th and 21st H within the vertical retrace interval. However, in the conventional apparatus, for the reason stated above, the phase of the horizontal nozzle is inaccurate and the 9-character signal cannot be extracted correctly.

In addition, when a video signal to be displayed is generated and displayed by a clock signal obtained from an internal oscillator in a teletext receiver, the display is based on horizontal pulses that are correctly synchronized to one horizontal period. Therefore, if the phase of the horizontal pulse is unstable, the display screen will also fluctuate in the horizontal direction in response to the fluctuation in the phase of the horizontal pulse, making it difficult to see the two display screens.However, in conventional devices, the horizontal oscillation is controlled by the AFC loop. Because of the control, the horizontal pulse obtained at the output terminal 7 essentially contains a phase error due to AFC looseness, which has the above-mentioned drawback.

OBJECTS OF THE INVENTION The present invention eliminates the above-mentioned drawbacks of the conventional art, and is capable of completely eliminating phase errors in the AFC loop with a simple configuration, and obtaining horizontal pulses with accurate phase as output. can. It is an object of the present invention to provide a horizontal pulse generator that is particularly advantageous when implemented as an IC.

Structure of the Invention The horizontal pulse generator for a television receiver of the present invention comprises:
A sync separation circuit connected to the video signal input terminal, a phase comparison circuit connected to the sync separation circuit, a low-pass filter connected to the phase comparison circuit, and a low-pass filter connected to the video signal input terminal; The phase comparison circuit includes a horizontal oscillation circuit connected to a pass filter, an output circuit connected to the horizontal oscillation circuit, and a gate circuit connected to the output circuit and the synchronous separation circuit, and the phase comparison circuit is connected to the output circuit. Since the vertical synchronizing signal removal circuit is connected between the period separating circuit and the phase comparator circuit, which are connected to each other or are switched, the AFC during the vertical retrace period is It is possible to reduce the error, match the start phase of the horizontal pulse obtained as the output of the gate circuit with the start phase of the horizontal synchronization signal, and completely eliminate the influence of phase error in the AFC loop.

DESCRIPTION OF EMBODIMENTS Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 2 is a block diagram of one embodiment of the present invention. Second
In the figure, 1, 2, 3, 4, 6°6.7 are the same as in FIG. 1, and 8 is a gate circuit.

In FIG. 2, a composite video signal inputted from a video signal input terminal 1 is synchronously separated by a synchronous separation circuit 2, and its output is inputted to a phase comparator circuit 3.

On the other hand, the output of the horizontal oscillation circuit 5 is input to the output circuit 6, and a pulse with a constant width is obtained as the output of the output circuit 6, and this pulse is input to the gate circuit 8.

On the other hand, the other outputs of the output circuit 6 have a duty ratio of 50%.
It becomes a square wave and is input to the phase comparator circuit 3. The phase comparison circuit 3 compares the phases of the output of the synchronous separation circuit 2 and the output of the output circuit 6, and provides the output to the horizontal oscillation circuit 5 through the low-pass filter 4 to control the oscillation frequency. In the gate circuit 8, the output of the output circuit 6 and
By gating the synchronization signal, that is, the output of the synchronization separation circuit 2.

A horizontal pulse is output to the output terminal 7.

A block diagram of another embodiment of the present invention is not shown in FIG. 3. In FIG. 3, 1 to 8 are the same as in FIG. 2, and 9 is a vertical synchronization signal removal circuit.

In FIG. 3, a composite video signal inputted from a video signal input terminal 1 is synchronously separated by a sync separation circuit 2, and its output is sent to a vertical sync signal removal circuit 9, where the sync signal from which the vertical sync signal has been removed is The signal is input to the I phase comparator circuit 3. On the other hand, the output of the horizontal oscillation circuit 5 is input to an output circuit 6, and a pulse with a constant width is obtained as an output of the output circuit 6, and this pulse is input to a gate circuit 8. On the other hand, the other output of the output circuit 6 becomes a square wave with a duty ratio of 50% and is input to the phase comparator circuit 3. In the phase comparison circuit 3, the output of the vertical synchronization signal removal circuit 9 and the output of the vertical synchronization signal removal circuit 9.

The phase is compared with the output of the output circuit 6, and the output is
The signal is applied to a horizontal oscillation circuit 6 through a low-pass filter 4 to control the oscillation frequency. In the gate circuit 8, the output circuit 6
and the synchronization signal, that is, the output of the synchronization separation circuit 2, to output a horizontal pulse to the output terminal 7.

In this way, the phase comparator circuit 3. Low pass filter 4. By using the AFC loop formed by the horizontal oscillation circuit 5 and the output circuit 6, even if noise is mixed in the output of the synchronization separation circuit 2, the influence of the noise on the output of the output circuit 6 is reduced.

The output circuit 6 generates, from the horizontal oscillation output of the horizontal oscillation circuit 5, a square wave with a duty ratio of 60% that is input to the gate circuit 8 and a two-phase comparator circuit 3. The required waveform can be obtained by using a flyback breaker circuit or by waveform shaping the output of a flyback transformer.

The vertical synchronization signal removal circuit 9 integrates the synchronization signal output from the synchronization separation circuit 2 to separate the vertical synchronization signal, and gates the synchronization signal with the vertical synchronization signal to remove the vertical synchronization signal from the input synchronization signal. are doing. By removing the vertical synchronizing signal, the horizontal oscillation circuit 5 becomes self-oscillating between the vertical synchronizing signals g and IJ, and the AFC error caused by the vertical synchronizing signal can be extremely reduced.

However, on the other hand, the above-mentioned AFC loose essentially includes a phase error. That is, in a steady state, a steady phase error occurs in the phase difference between the output of the output circuit 6 and the input synchronizing signal due to fluctuations in the oscillation frequency of the horizontal oscillation circuit 5, which appears as jitter in the output pulse. This can be reduced by increasing the loop gain of the AFC loop, but increasing the loop gain worsens the transient response characteristics. That is, the phase error from the open state to the time when the AFC loop is pulled in and synchronized becomes large.

Therefore, it is necessary to increase the loop gain within a range that does not impair the transient response characteristics for practical purposes.

In the present invention, the game control circuit 8 is used to solve the above-mentioned problem. The period of the square wave applied to this gate circuit 11 is the same as the period of the horizontal synchronizing signal, with the leading edge slightly ahead of the leading edge of the horizontal synchronizing signal, and the trailing edge of the waveform being slightly ahead of the trailing edge of the horizontal synchronizing signal. Set it to be later. In other words, the output circuit 6 generates a square wave that is slightly wider than the horizontal sync signal and includes the horizontal sync signal, and inputs it to the gate circuit 8. Figure 4 shows the input and output of the gate circuit 8. This shows the waveform. The horizontal axis shows the time axis. Figure 4 (al is synchronous separation circuit 2
4(b) is the input waveform input from the output circuit 6 to the gate circuit 8, and FIG. 4(C) is the output waveform of the gate circuit 8.
This is the output waveform of In Figure 4, the signal input from the output circuit 6 to the gate circuit 8 is a ζ pulse that is slightly wider than the horizontal synchronizing signal, so the output is as shown in Figure 4 (
As shown in C), a horizontal pulse that always matches the horizontal synchronization signal is obtained.

In the case of the waveform diagrams of FIGS. 4(a), t(b), and (C), the gate circuit 8 can be realized by a NOR circuit.

Next, FIG. 5 shows waveform diagrams before and after the vertical synchronization signal. Figure 6(,) is the output waveform of the synchronous separation circuit 2, Figure 5(b)
is the input waveform input from the output circuit 6 to the gate circuit 8,
FIG. 5(C) shows the output waveform of the gate circuit 8.

In Fig. 6, as in Fig. 4, the signal input from the output circuit 6 to the gate circuit 8 is a pulse slightly wider than the horizontal synchronizing signal, so as shown in Fig. 5 (C). During the 1st to 3rd H and 7th to 9th H periods, an equivalent pulse is gated and output every 1H, and during the vertical synchronization signal period (4th to eH), the leading edge is the equivalent pulse of the vertical synchronization signal. A pulse whose trailing edge matches the output of the output circuit 6 is output.

However, in the output waveform of FIG. 6(C), since the leading edge interval is always 1H, the output of the gate circuit 8 is in the leading edge phase regardless of whether it is within the vertical retrace period or not. Accurate horizontal pulses can be obtained.

The horizontal pulse obtained at the output terminal 7 is a pulse obtained by gating the pulse obtained from the horizontal oscillation circuit 6 through the output circuit 6 and the output of the synchronous separation circuit 2, so the two-phase comparison circuit 3. Low pass filter 4. Horizontal oscillation circuit6. The phase error appearing at the output of the output circuit 6 in the AFC loop of the output circuit 6 is completely removed at the output terminal 7.

Also, as can be seen from the block diagram in Figure 2.

The configuration of the present invention has the advantage of being easy to integrate into an IC.

Note that the characteristics of the vertical synchronization signal removal circuit 9 are that the AFC loop should be open during the period including the vertical synchronization signal.
For example, 4th to 6th H such as 1st to 6th H, 1st to 1°H
Any device that applies a gate to the synchronization signal during the period including the above may be used.

Effects of the Invention As is clear from the above explanation, the present invention has two advantages: by AFC loose, which compares the phase of the signal from which the vertical synchronization signal has been removed from the output of the synchronization separation circuit and the square wave obtained from the horizontal oscillation circuit through the output circuit; with a wide pulse obtained as the output of the output circuit.

Since the horizontal pulse is obtained by applying a gate to the synchronization signal, it is resistant to external noise and the vertical retrace period (first to
9H), both phase and width match the horizontal synchronizing signal, and during the vertical retrace period (1st to 9th H), a pulse with a front line interval of exactly 1H is obtained, and the horizontal pulse of this output is A
Since the phase error that essentially exists in FC loose is completely removed, the output has the advantage of providing a stable and accurate horizontal pulse. Furthermore, the configuration of the present invention is suitable for IC implementation, and has a significant cost reduction effect.

[Brief explanation of the drawing]

Figure 1 is a circuit block diagram of a conventional horizontal pulse generator.
FIG. 2 is a circuit block diagram of a horizontal pulse generator according to one embodiment of the present invention, FIG. 3 is a circuit block diagram of a horizontal pulse generator according to another embodiment of the present invention, and FIG. 4 is a circuit block diagram of a horizontal pulse generator according to another embodiment of the present invention. A waveform diagram of the synchronization signal in the embodiment, the output of the output circuit, and the output of the gate circuit. FIG. 6 shows the synchronization signal in the embodiment of the present invention. FIG. 6 is a waveform diagram of the output of the output circuit and the output of the gate circuit during the vertical retrace period. 2... Synchronization separation circuit, 3... Phase comparison circuit, 4... Low pass filter, 6...
・Horizontal oscillation circuit, 6... Output circuit, 8...
...Gate circuit, 9... Vertical synchronization signal removal circuit.

Claims (2)

[Claims] (1) a video signal input terminal, a sync separation circuit connected to the video signal input terminal, a phase comparison circuit connected to the sync separation circuit, and a low-pass filter connected to the phase comparison circuit; The phase comparison circuit includes a horizontal oscillation circuit connected to the low-pass filter, an output circuit connected to the horizontal oscillation circuit, and a gate circuit connected to the output circuit and the synchronous separation circuit. A horizontal pulse generator for a television receiver, characterized in that it is connected to the output circuit. (2) A video signal input terminal, a sync separation circuit connected to the video signal input terminal, a vertical sync signal removal circuit connected to the sync separation circuit, and a phase comparison connected to the vertical sync signal removal circuit. a low-pass filter connected to the phase comparison circuit, a horizontal oscillation circuit connected to the low-pass filter, an output circuit connected to the horizontal oscillation circuit, and the output circuit and the synchronous separation. A horizontal pulse generator for a television receiver, characterized in that the phase comparator circuit is connected to the output circuit, and the phase comparator circuit is connected to the output circuit.