JP3675050B2 - Synchronization determination circuit and television receiver - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a synchronization determination circuit for determining whether an input video signal is a standard signal formed by a regular television system or a non-standard signal, and a television receiver including the synchronization determination circuit. .
[0002]
[Prior art]
Currently, for example, a television receiver can receive a broadcast radio wave transmitted from a broadcast station, select a broadcast program with a tuner and view it, and can be reproduced by an external input device such as a video deck. You can watch movies.
Recently, it has become possible to connect a game device as an external input device and display a video of dedicated game software on the screen for playing.
[0003]
When watching software such as a movie normally played from a broadcast program or a video deck selected by a tuner, these video signals are, for example, NTSC (National Television System Committee ... horizontal synchronization frequency 15.734 KHz, number of horizontal scanning lines 262.5 lines) system and PAL (Phase Alternation by Line) system standard signal.
Also, during special playback (such as fast forward / rewind search and still image playback) using a video deck, the vertical and horizontal sync signals of the video signal have different periodic relationships depending on the model, and are non-standard signals that differ from the standard signals. Entered. Furthermore, the video signal output from the game device is also input as a non-standard signal (for example, 262 horizontal scanning lines, 263 lines, etc.) generated by various game devices themselves.
[0004]
By the way, in the case of a standard signal input as a received signal, for example, noise is superimposed on the broadcast radio wave in some form, or in the area of weak electric field, the vertical synchronization signal is temporarily lost and the synchronization performance deteriorates There is. Therefore, in the case of a standard signal, when it is detected that a vertical synchronization signal is missing, it is considered that an interpolation process is performed based on predictions from the preceding and succeeding vertical synchronization signals. As a result, the vertical synchronization becomes stable, and a good image can be obtained.
On the other hand, for example, the video signal supplied from the game device is a non-standard signal, but the synchronization signal is not lost and is supplied at a predetermined cycle (for example, 262 horizontal scanning lines, 263). Therefore, it is not necessary to perform interpolation processing on the input video signal in this case. Therefore, when there is no vertical synchronization signal with a period of 262.5, it is necessary to determine whether the standard signal is missing or the non-standard signal has a different vertical synchronization period.
[0005]
FIG. 4 is a diagram showing a configuration example of a synchronization determination circuit in a deflection control unit applied to, for example, an NTSC television receiver as a conventional example.
A horizontal synchronization signal HSync (about 15.734 kHz in the case of the NTSC system) extracted by a video signal processing system (not shown) is supplied to an oscillator 20 constituted by, for example, a PLL. The oscillator 20 is configured to oscillate using the horizontal synchronization signal HSync as a reference clock. For example, the oscillator 20 generates a clock CLK having a frequency n times (where n is a natural number) with respect to the horizontal synchronization signal HSync. Here, as an example, assume that n = 2 and a clock CLK having a frequency twice that of the horizontal synchronizing signal HSync is generated. Therefore, the clock CLK is output at a frequency of 31.468 kHz.
[0006]
The clock CLK is supplied as a counting clock to the frequency divider 21 configured as a 10-bit counter by flip-flops 21a, 21b,. The count output (output of the output terminal Q of each flip-flop 21a to 21j) output from the frequency divider 21 is output to the timing generator 22. The timing generator 22 is configured to output, for example, a count pulse P525 that becomes L level at a timing of 525 counts, for example, a reset pulse R526 that becomes L level at a timing of 526 counts, according to the count output.
In addition, an AND circuit 23 is provided at the input stage of the frequency divider 21, and the vertical synchronization pulse Vsync is lost by setting it at the falling edge of the vertical synchronization pulse Vsync or the reset pulse R526 that becomes L level at the timing of the vertical synchronization signal. Even if it is possible to reset.
[0007]
The flip-flops 24 and 25 are provided so as to constitute a determination unit that determines whether or not the input signal is a standard signal from the vertical synchronization pulse Vsync, and the vertical synchronization pulse Vsync is supplied to each data terminal D. Further, the count pulse P525 output from the timing generator 22 is supplied to the clock terminal, but the count pulse P525r whose phase is inverted is supplied to the clock terminal of the flip-flop 25 via the inverter 26. Become.
Therefore, the flip-flops 24 and 25 determine the output levels of the output terminals Q1 and Q2 at the falling timing of the count pulses P525 and P525r, respectively, and can determine the presence or absence of the vertical synchronization pulse together with the AND circuit 27 as will be described later. .
[0008]
Since the “0” period after the frequency divider 21 is reset is always shorter than the cycle of one clock, the 525th clock, that is, the count pulse P525 rises earlier than the vertical synchronization pulse Vsync of the standard signal. Therefore, with respect to the vertical synchronization pulse Vsync schematically shown in FIG. 5A, the count pulse P525 and the inverted count pulse P525r are shown in FIGS. 5B and 5C, respectively. It becomes a trigger signal for the flip-flops 24 and 25 at the timing of the arrow. Therefore, at the time of the normal vertical synchronizing signal Vsync, the H level is output from the output terminal Q1 and the H level is also output from the inverted output terminal Q2 at the timing of the falling points A and B. The output of the AND circuit 27 becomes H level, and it is determined that this case is a standard signal.
[0009]
Further, as shown in FIGS. 5D, 5E and 5F, when the timing of the vertical synchronizing signal Vsync and the count pulse P525 do not coincide with each other, the output terminal Q1 is set to the H level and the inverted output terminal Q2 is set. Outputs an L level. In this case, since the output of the AND circuit 27 becomes L level, it is determined that this is a non-standard signal.
The determination result here is supplied to a synchronous interpolation processing system (not shown), and interpolation processing is performed when the vertical synchronization pulse Vsync is lost in the case of a standard signal.
[0010]
Thus, for example, even when a noisy video signal is input, once it can be determined that the signal is a standard signal, the frequency divider 21 provides a dead zone up to, for example, 524 counts with respect to the vertical synchronization pulse Vsync. Even in a weak electric field, the video screen can be controlled so as not to be disturbed.
[0011]
[Problems to be solved by the invention]
By the way, as described above, in the case of a standard signal, for example, in a region with a weak electric field, it may be difficult to extract the synchronization signal itself, and in an extreme case, the vertical synchronization signal may be lost.
FIG. 6 is a diagram showing the output timing of each signal when a part of the vertical synchronization signal is lost. FIG. 6A shows the clock CLK, FIG. 6B shows the vertical synchronization pulse Vsync, and FIG. Is the count pulse P525, FIG. 6D is the output level of the output terminal Q1 of the flip-flop 24, FIG. 6E is the output level of the inverting output terminal Q2 of the flip-flop 25, and FIG. Output is shown.
[0012]
As described above with reference to FIG. 3, it is determined whether or not there is the vertical synchronization pulse Vsync at the timing of the count pulses P525 and P525r output according to the clock CLK. For example, FIG. When the vertical synchronization pulse Vsync to be input at the timing indicated by the broken line is lost, the output of the inverted output terminal Q2 becomes H level (FIG. 6 (e)) as described above. The output is at the L level (FIG. 6F), and it is determined that the currently input video signal is not a standard signal.
[0013]
For this reason, for example, it has been considered that an integration circuit or the like is provided in the subsequent stage of the AND circuit 27 so as to have a time constant in determining whether the signal is a standard signal.
However, once it is determined that the signal is not a standard signal, the dead zone must be narrowed due to the diversity of input signals (262, 263, etc. due to non-standard signals). The synchronization between the frequency divider 21 and the vertical synchronization pulse Vsync is disturbed due to noise superposition or the like, and it becomes difficult to determine that the signal is the standard signal again.
Therefore, even when the vertical synchronization pulse Vsync is lost, interpolation processing or the like is not performed, so that there is a problem in that an image with disordered synchronization is displayed.
[0014]
[Means for Solving the Problems]
The present invention has been made to solve such problems, and an oscillation means for generating a clock having an oscillation frequency n times (however, n ≧ 2) of a horizontal synchronization pulse extracted from an input video signal; A frequency dividing means that is reset by a reset pulse output corresponding to a vertical synchronizing pulse extracted from a video signal or m times (where m ≧ 2) of the vertical synchronizing pulse and outputs a count value based on the clock And a first count pulse having the same period as the vertical synchronization pulse, a second count pulse m times the vertical synchronization pulse, and the reset pulse based on the count value output from the frequency dividing means And a timing determination means for determining the presence or absence of the vertical synchronization pulse at the timing of the first and second count pulses. Constitute a.
In addition, a television receiver is configured using this synchronization determination circuit.
[0015]
According to the present invention, even when the vertical synchronization signal of the input video signal is missing and is not input at a predetermined cycle, if the vertical synchronization signal is input at the next cycle, the standard signal is input. You can make a decision. As a result, for example, it is possible to make a determination that a video signal that is easily missing a vertical synchronization signal received due to a weak electric field is also a standard signal without timing delay, and synchronous interpolation processing is performed on the missing vertical synchronization signal. Will be able to do.
[0016]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, an embodiment when the embodiment of the present invention is applied to, for example, an NTSC television receiver will be described.
FIG. 1 is a diagram showing a partial circuit block of a video system of the television receiver of this embodiment.
The tuner 1 is composed of, for example, a BS tuner, a CS tuner, a U / V tuner, and the like, and selects a broadcast wave received by the antenna A. The reception signal selected by the tuner 1 is supplied to the video signal processing unit 3 through the intermediate frequency amplification unit (VIF) 2 and the switch SW. The switch SW is a received signal selected by the tuner 1 and an external input device connected to the external input terminals t1 and t2 (for example, an AV (Audio Visual) device such as a video deck or a laser disk player, or a game device, etc.) Is omitted) and the video signal supplied is selected and supplied to the video signal processing unit 3.
[0017]
The video signal supply unit 3 performs various signal processing such as color signal separation, color difference signal formation, and synchronization signal extraction, and supplies RGB video signals to the CRT 4. The synchronization signal extracted here is supplied to the control unit 5.
The control unit 5 generates an operation clock synchronized with the horizontal scanning period for synchronizing various signal processing and the like in each functional circuit from the input synchronization signal. In addition, a command output from the remote commander RC provided with various operation keys, selection keys, and the like is input via the light receiving unit 6, and tuning control of the tuner 1, switching of the switch SW, or video signal processing unit 3 is performed. Various image quality adjustments and the like are performed.
[0018]
The deflection control unit 7 is attached to the neck portion of the CRT 4 by forming the horizontal deflection signal H at the timing of the horizontal cycle based on the operation clock output from the control unit 5 to which the video signal synchronization information is input. Supply to the deflection yoke 8.
Also, the normal playback in which the video signal currently selected by the switch SW is supplied from an external input device such as a broadcast program selected by the tuner 1 or a video deck connected to the external input terminal t1 or t2 is used. Judgment whether it is a standard signal such as a video, or a special playback video supplied from an external input device connected to the external input terminal t1 or t2, or a non-standard signal supplied from a game device Configured to do.
[0019]
When the video signal currently selected by the deflection processing unit 7 is determined to be a standard signal, the synchronous interpolation processing unit 9 performs vertical synchronization signal every 262.5 horizontal scanning lines due to lack of weak electric fields, for example. When there is no signal, interpolation processing is performed by predicting the vertical synchronizing signal before and after that, and the vertical synchronizing signal is generated at a predetermined timing.
[0020]
As a result, even when the vertical sync signal for every 262.5 horizontal scanning lines is lost in the standard signal, for example, the vertical synchronizing signal can be generated by the interpolation process, and for example, every 262.5 horizontal scanning lines. If a non-standard signal having no vertical synchronizing signal is selected, interpolation processing can be prevented.
[0021]
Next, the synchronization determination circuit in the deflection control unit 7 will be described in detail with reference to FIG. In FIG. 2, the deflection output system is not shown.
The horizontal synchronization signal HSync (about 15.734 kHz) extracted by the video signal processing unit 3 shown in FIG. 1 is supplied to the oscillator 10 constituted by, for example, a PLL. The oscillator 10 is configured to oscillate based on the period of the horizontal synchronization signal HSync, and generates a clock CLK having a frequency n times (where n is a natural number), for example, with respect to the horizontal synchronization signal HSync. Here, as an example, assume that n = 2 and a clock CLK having a frequency twice that of the horizontal synchronizing signal HSync is generated. Therefore, the clock CLK is output with a period of 31.468 kHz.
[0022]
The clock CLK is supplied as a counting clock to the frequency divider 11 constituted as an 11-bit counter by flip-flops 11a, 11b,. By configuring the frequency divider 11 with 11 bits, it is possible to count from 0 to 2047. Although shown here as an asynchronous counter, it may be configured as a synchronous counter.
The count output (output of the Q output terminals of the flip-flops 11a to 11k) output from the frequency divider 11 is output to the timing generator 13. The timing generator 13 outputs a pulse signal that becomes L level at a timing corresponding to the count output. The count pulse P525 is a pulse signal having the same cycle as that of the vertical synchronization pulse Vsync, and the count pulse P1050 is output as a pulse signal m times the vertical synchronization pulse Vsync, that is, in this embodiment, m = 2 times.
[0023]
In addition, an AND circuit 12 is provided at the input stage of the frequency divider 11, and is output every 1051 counts corresponding to the vertical synchronization pulse Vsync which becomes L level at the timing of the vertical synchronization signal or a period of m times the vertical synchronization pulse Vsync. By resetting at the fall timing of the reset pulse R1051, the vertical synchronization pulse Vsync can be reset if it is lost.
Further, the latch pulse La is output at a timing earlier than the count pulse P525 for holding the determination result of the standard / non-standard signal. In this embodiment, the latch pulse La is output at the timing of the 490th count, for example. .
[0024]
The determination unit Jad indicated by a broken line includes, for example, AND circuits 14 and 18, an inverter 15, flip-flops 16 and 17 that determine the presence or absence of the vertical synchronization signal Vsync, and a flip-flop that holds the output level of the flip-flops 16 and 17. 20 or the like.
[0025]
The flip-flops 16 and 17 are provided as means for determining whether or not the input signal is a standard signal from the vertical synchronization pulse Vsync, and the vertical synchronization pulse Vsync is supplied to each data terminal. Further, a count pulse P525 or a count pulse P1050 output from the timing generator 13 via the AND circuit 14 is supplied to the clock terminal (hereinafter, the output of the AND circuit 14 is referred to as a trigger pulse Pt). The trigger pulse Ptr whose phase is inverted is supplied to the clock terminal of the second clock terminal via the inverter 15.
Accordingly, the flip-flops 16 and 17 are configured such that the output level of the output terminal Q is determined at the falling edges of the trigger pulses Pt and Ptr, respectively.
[0026]
Since the “0” period after the frequency divider 11 is reset is always shorter than the cycle of one clock, the 525th clock, that is, the count pulse P525 rises earlier than the vertical synchronizing pulse Vsync of the standard signal. Therefore, the trigger pulse Pt, Ptr is input to the clock terminal at the same timing as described in FIG. 4 with respect to the vertical synchronization pulse Vsync, and the output terminal Q1 of the flip-flop 16 at the timing of each falling point A, B. Are output at H level, and the inverted output terminals Q2 of the flip-flop 17 are output at H level. As a result, when the standard vertical synchronization pulse Vsync is detected, the output of the AND circuit 18 becomes H level, and this case is used as the standard signal.
[0027]
Further, when there is no vertical synchronizing pulse Vsync, it is H level from the output terminal Q1 of the flip-flop 16 at the falling timing of the trigger pulse Pt, and L from the inverted output terminal Q2 of the flip-flop 17 at the falling timing of the trigger pulse Ptr. The level is output. In this case, since the output of the AND circuit 18 is at the L level, this case is determined as a non-standard signal.
[0028]
The determination result output from the AND circuit 18 is supplied to the data terminal of the flip-flop 19. Further, since the latch pulse La is supplied to the clock terminal of the flip-flop 19, the output level of the AND circuit 18, that is, the determination result of the standard / nonstandard signal can be held as will be described later with reference to FIG. It becomes like this. Then, the determination result is supplied to the synchronous interpolation processing unit 9.
[0029]
Hereinafter, a case where a part of the vertical synchronization pulse Vsync is lost due to, for example, a weak electric field will be described.
FIG. 3 is a diagram showing the output timing of each signal of the deflection control unit 7 shown in FIG. 2. FIG. 3 (a) shows the clock CLK, FIG. 3 (b) shows the vertical sync pulse Vsync of the standard signal, and FIG. 3C shows the count pulse P525, FIG. 3D shows the count pulse P1050, FIG. 3E shows the output level of the Q output terminal of the flip-flop 16, and FIG. 3F shows the output of the inverted Q output terminal of the flip-flop 17. 3G shows the latch pulse La, and FIG. 3H shows the output level of the Q output terminal of the flip-flop 10.
[0030]
For example, as shown by the broken line in FIG. 3B, when the vertical synchronization pulse Vsync is lost due to a weak electric field, the flip-flop is used at the timing of the count pulse P525 shown in FIG. As shown in FIGS. 3E and 3F, the output levels 16 and 17 become the H level and the L level, and are judged as non-standard signals. However, in the present invention, the frequency divider 13 continues counting and the latch pulse Lar is not output at the timing indicated by the broken line as shown in FIG. Therefore, at this time, the determination that the signal is a non-standard signal is not output. As the count operation of the frequency divider 11 continues, the count pulse P1050 is output from the timing generator 13 and supplied to the clock terminals of the flip-flops 16 and 17 as shown in FIG. The
[0031]
In other words, the standard / non-standard signal is determined by the count pulse P1050. When the vertical synchronization pulse Vsync2 is temporarily lost due to a weak electric field, as shown in FIG. The possibility that the vertical synchronization pulse Vsync3 of the next period is input is very high. In addition, since non-standard signals at the time of special playback of game machines and video decks have different periods, the possibility that the vertical synchronization pulse Vsync is input at a timing of 1050 counts is low.
[0032]
Therefore, if the vertical synchronization pulse VSync is input at the timing of the count pulse P1050 and the output of the AND circuit 18 becomes H level, it can be determined that the standard signal is currently input. At this time, the frequency divider 11 is reset by the reset pulse R1051 and the vertical synchronization pulse Vsync and starts counting again. Then, the latch pulse La is output at the 490th count from the reset timing.
The determination result obtained by the previous count pulse P1050 is held by the flip-flop 19 by the latch pulse La shown in FIG. That is, as shown in FIG. 3B, when the vertical synchronization pulse Vsync is lost, the frequency divider 11 is not reset. Therefore, as shown in FIG. 3F, the output level of the inverted Q output terminal is temporarily set. Even when the signal becomes L level, the output of the flip-flop 19 is held at H level. Therefore, even when a temporary vertical synchronization pulse Vsync is lost in the standard signal, erroneous determination that the signal is a non-standard signal can be prevented.
[0033]
In the above embodiment, the description has been made assuming that the clock frequency CLK is a multiple n = 2 of the oscillation frequency in the oscillator 10, that is, twice the frequency of the horizontal synchronizing pulse, but other numerical values may be used as long as they are natural numbers. In addition, the reset pulse R1051 is set to the L level at the timing of 1051 count, but this can also be set to a numerical value corresponding to a cycle of m times the vertical synchronization pulse Vsync.
For example, when the multiple n = 3 (525 × 3 = 1575) is set, 1575 counts or more are set, and if 1575 is set as the window of the standard signal, the vertical sync pulse Vsync is not affected. .
In the above embodiment, the NTSC system has been described as an example. However, other television systems such as a PAL system, a SECAM system, and the like can be applied.
[0034]
【The invention's effect】
As described above, the monitor device of the present invention has a case where the vertical synchronization signal is input in the next cycle even if the vertical synchronization signal of the input video signal is missing and is not input in a predetermined cycle. It can be determined that the standard signal is input. As a result, it is possible to determine that a video signal in which a vertical synchronization signal such as a weak electric field is easily lost is also a standard signal.
As a result, when the vertical synchronization signal is lost, the interpolation process is performed, so that a good synchronized image can be displayed.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a part of a television receiver according to an embodiment of the present invention.
FIG. 2 is a diagram illustrating a synchronization determination circuit in the deflection control unit of the television receiver shown in FIG.
FIG. 3 is a diagram illustrating signal waveform timings in each unit of the determination unit illustrated in FIG. 2;
FIG. 4 is a diagram illustrating a synchronization determination circuit in a conventional deflection control unit.
FIG. 5 is a diagram for explaining timings of a vertical synchronization pulse and a count pulse.
6 is a diagram illustrating signal waveform timing in each unit of the determination unit illustrated in FIG. 4; FIG.
[Explanation of symbols]
10 Oscillator, 11 Frequency Divider, 13 Timing Generator, Jad Judgment Unit, P525, P1050 Count Pulse, R1051 Reset Pulse, Pt, Ptr Trigger Pulse, La Latch Pulse

Claims (4)

Oscillation means for generating a clock having an oscillation frequency n times (where n ≧ 2) the horizontal synchronization pulse extracted from the input video signal;
Frequency division which is reset by a reset pulse output corresponding to a vertical synchronization pulse extracted from the video signal or m times (however, m ≧ 2) of the vertical synchronization pulse and outputs a count value based on the clock Means,
Timing of outputting the first count pulse having the same period as the vertical synchronization pulse, the second count pulse m times the vertical synchronization pulse, and the reset pulse based on the count value output from the frequency dividing means Generating means;
Determination means for determining the presence or absence of the vertical synchronization pulse at the timing of the first and second count pulses;
A synchronization determination circuit comprising: A determination holding means for holding a determination result of the determination output means by a third count pulse output from the timing generation means at a timing earlier than the output timing of the first count pulse is provided. The synchronization determination circuit according to claim 1. Television receiver provided with a synchronization determination circuit for determining whether the video signal is a standard signal that is a regular television system or a non-standard signal from a vertical synchronization pulse of the input video signal In
The synchronization determination circuit includes:
Oscillation means for generating a clock having an oscillation frequency n times (where n ≧ 2) the horizontal synchronization pulse extracted from the input video signal;
Frequency division which is reset by a reset pulse output corresponding to a vertical synchronization pulse extracted from the video signal or m times (however, m ≧ 2) of the vertical synchronization pulse and outputs a count value based on the clock Means,
Timing of outputting the first count pulse having the same period as the vertical synchronization pulse, the second count pulse m times the vertical synchronization pulse, and the reset pulse based on the count value output from the frequency dividing means Generating means;
Determination means for determining the presence or absence of the vertical synchronization pulse at the timing of the first and second count pulses;
A television receiver comprising: A determination holding means for holding a determination result of the determination means by a third count pulse output from the timing generation means at a timing earlier than an output timing of the first count pulse is provided. Item 4. The television receiver according to Item 3.

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